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drm/radeon/dpm/rs780: add some sanity checking to sclk scaling
[deliverable/linux.git] / drivers / gpu / drm / radeon / rs780_dpm.c
CommitLineData
9d67006e
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include "drmP.h"
26#include "radeon.h"
27#include "rs780d.h"
28#include "r600_dpm.h"
29#include "rs780_dpm.h"
30#include "atom.h"
444bddc4 31#include <linux/seq_file.h>
9d67006e
AD		 32
33static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
34{
35 struct igp_ps *ps = rps->ps_priv;
36
37 return ps;
38}
39
40static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
41{
42 struct igp_power_info *pi = rdev->pm.dpm.priv;
43
44 return pi;
45}
46
47static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
48{
49 struct igp_power_info *pi = rs780_get_pi(rdev);
50 struct radeon_mode_info *minfo = &rdev->mode_info;
51 struct drm_crtc *crtc;
52 struct radeon_crtc *radeon_crtc;
53 int i;
54
55 /* defaults */
56 pi->crtc_id = 0;
57 pi->refresh_rate = 60;
58
59 for (i = 0; i < rdev->num_crtc; i++) {
60 crtc = (struct drm_crtc *)minfo->crtcs[i];
61 if (crtc && crtc->enabled) {
62 radeon_crtc = to_radeon_crtc(crtc);
63 pi->crtc_id = radeon_crtc->crtc_id;
64 if (crtc->mode.htotal && crtc->mode.vtotal)
c3eaa088 65 pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
9d67006e
AD		 66 break;
67 }
68 }
69}
70
71static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
72
f5d73a80
AD		 73static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
74 struct radeon_ps *boot_ps)
9d67006e
AD		 75{
76 struct atom_clock_dividers dividers;
f5d73a80 77 struct igp_ps *default_state = rs780_get_ps(boot_ps);
9d67006e
AD		 78 int i, ret;
79
80 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
81 default_state->sclk_low, false, &dividers);
82 if (ret)
83 return ret;
84
85 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
86 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
87 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
88
89 if (dividers.enable_post_div)
90 r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
91 else
92 r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
93
94 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
95 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
96
97 r600_engine_clock_entry_enable(rdev, 0, true);
98 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
99 r600_engine_clock_entry_enable(rdev, i, false);
100
101 r600_enable_mclk_control(rdev, false);
102 r600_voltage_control_enable_pins(rdev, 0);
103
104 return 0;
105}
106
f5d73a80
AD		 107static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
108 struct radeon_ps *boot_ps)
9d67006e
AD		 109{
110 int ret = 0;
111 int i;
112
113 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
114
115 r600_set_at(rdev, 0, 0, 0, 0);
116
117 r600_set_git(rdev, R600_GICST_DFLT);
118
119 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
120 r600_set_tc(rdev, i, 0, 0);
121
122 r600_select_td(rdev, R600_TD_DFLT);
123 r600_set_vrc(rdev, 0);
124
125 r600_set_tpu(rdev, R600_TPU_DFLT);
126 r600_set_tpc(rdev, R600_TPC_DFLT);
127
128 r600_set_sstu(rdev, R600_SSTU_DFLT);
129 r600_set_sst(rdev, R600_SST_DFLT);
130
131 r600_set_fctu(rdev, R600_FCTU_DFLT);
132 r600_set_fct(rdev, R600_FCT_DFLT);
133
134 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
135 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
136 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
137 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
138 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
139
140 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
141 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
142 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
143
f5d73a80 144 ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
9d67006e
AD		 145
146 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
147 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
148 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0);
149
150 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
151 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
152 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
153
154 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
155 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
156 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
157
158 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH);
159 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
160 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH);
161
162 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
163 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
164 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
165 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
166
167 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
168
169 r600_set_vrc(rdev, RS780_CGFTV_DFLT);
170
171 return ret;
172}
173
174static void rs780_start_dpm(struct radeon_device *rdev)
175{
176 r600_enable_sclk_control(rdev, false);
177 r600_enable_mclk_control(rdev, false);
178
179 r600_dynamicpm_enable(rdev, true);
180
181 radeon_wait_for_vblank(rdev, 0);
182 radeon_wait_for_vblank(rdev, 1);
183
184 r600_enable_spll_bypass(rdev, true);
185 r600_wait_for_spll_change(rdev);
186 r600_enable_spll_bypass(rdev, false);
187 r600_wait_for_spll_change(rdev);
188
189 r600_enable_spll_bypass(rdev, true);
190 r600_wait_for_spll_change(rdev);
191 r600_enable_spll_bypass(rdev, false);
192 r600_wait_for_spll_change(rdev);
193
194 r600_enable_sclk_control(rdev, true);
195}
196
197
198static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
199{
200 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
201 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
202
203 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
204 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
205 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
206}
207
208static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
209{
210 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
211
212 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
213 ~STARTING_FEEDBACK_DIV_MASK);
214
215 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
216 ~FORCED_FEEDBACK_DIV_MASK);
217
218 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
219}
220
221static void rs780_voltage_scaling_init(struct radeon_device *rdev)
222{
223 struct igp_power_info *pi = rs780_get_pi(rdev);
224 struct drm_device *dev = rdev->ddev;
225 u32 fv_throt_pwm_fb_div_range[3];
226 u32 fv_throt_pwm_range[4];
227
228 if (dev->pdev->device == 0x9614) {
229 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
230 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
231 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
232 } else if ((dev->pdev->device == 0x9714) ||
233 (dev->pdev->device == 0x9715)) {
234 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
235 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
236 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
237 } else {
238 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
239 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
240 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
241 }
242
243 if (pi->pwm_voltage_control) {
244 fv_throt_pwm_range[0] = pi->min_voltage;
245 fv_throt_pwm_range[1] = pi->min_voltage;
246 fv_throt_pwm_range[2] = pi->max_voltage;
247 fv_throt_pwm_range[3] = pi->max_voltage;
248 } else {
249 fv_throt_pwm_range[0] = pi->invert_pwm_required ?
250 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
251 fv_throt_pwm_range[1] = pi->invert_pwm_required ?
252 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
253 fv_throt_pwm_range[2] = pi->invert_pwm_required ?
254 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
255 fv_throt_pwm_range[3] = pi->invert_pwm_required ?
256 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
257 }
258
259 WREG32_P(FVTHROT_PWM_CTRL_REG0,
260 STARTING_PWM_HIGHTIME(pi->max_voltage),
261 ~STARTING_PWM_HIGHTIME_MASK);
262
263 WREG32_P(FVTHROT_PWM_CTRL_REG0,
264 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
265 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
266
267 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
268 ~FORCE_STARTING_PWM_HIGHTIME);
269
270 if (pi->invert_pwm_required)
271 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
272 else
273 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
274
275 rs780_voltage_scaling_enable(rdev, true);
276
277 WREG32(FVTHROT_PWM_CTRL_REG1,
278 (MIN_PWM_HIGHTIME(pi->min_voltage) |
279 MAX_PWM_HIGHTIME(pi->max_voltage)));
280
281 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
282 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
283 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
284 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
285
286 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
287 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
288 ~RANGE0_PWM_FEEDBACK_DIV_MASK);
289
290 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
291 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
292 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
293
294 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
295 (RANGE0_PWM(fv_throt_pwm_range[1]) |
296 RANGE1_PWM(fv_throt_pwm_range[2])));
297 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
298 (RANGE2_PWM(fv_throt_pwm_range[1]) |
299 RANGE3_PWM(fv_throt_pwm_range[2])));
300}
301
302static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
303{
304 if (enable)
305 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
306 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
307 else
308 WREG32_P(FVTHROT_CNTRL_REG, 0,
309 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
310}
311
312static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
313{
314 if (enable)
315 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
316 else
317 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
318}
319
320static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
321{
322 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
323 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
324 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
325 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
326 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
327
328 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
329 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
330 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
331 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
332 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
333}
334
335static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
336{
337 WREG32_P(FVTHROT_FBDIV_REG2,
338 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
339 ~FB_DIV_TIMER_VAL_MASK);
340
341 WREG32_P(FVTHROT_CNTRL_REG,
342 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
343 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
344}
345
346static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
347{
348 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
349}
350
351static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
352{
353 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
354 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
355 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
356 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
357
358 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
359}
360
361static void rs780_program_at(struct radeon_device *rdev)
362{
363 struct igp_power_info *pi = rs780_get_pi(rdev);
364
365 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
366 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
367 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
368 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
369 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
370}
371
372static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
373{
374 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
375}
376
63580c3e 377static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
9d67006e 378{
9d67006e
AD		 379 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
380
381 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
382 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
383 return;
384
385 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
386
387 udelay(1);
388
389 WREG32_P(FVTHROT_PWM_CTRL_REG0,
63580c3e 390 STARTING_PWM_HIGHTIME(voltage),
9d67006e
AD		 391 ~STARTING_PWM_HIGHTIME_MASK);
392
393 WREG32_P(FVTHROT_PWM_CTRL_REG0,
394 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
395
396 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
397 ~RANGE_PWM_FEEDBACK_DIV_EN);
398
399 udelay(1);
400
401 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
402}
403
63580c3e
AB		 404static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
405{
406 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
407
408 if (current_state->sclk_low == current_state->sclk_high)
409 return;
410
411 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
412
413 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
414 ~FORCED_FEEDBACK_DIV_MASK);
415 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
416 ~STARTING_FEEDBACK_DIV_MASK);
417 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
418
419 udelay(100);
420
421 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
422}
423
f5d73a80
AD		 424static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
425 struct radeon_ps *new_ps,
426 struct radeon_ps *old_ps)
9d67006e
AD		 427{
428 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
f5d73a80
AD		 429 struct igp_ps *new_state = rs780_get_ps(new_ps);
430 struct igp_ps *old_state = rs780_get_ps(old_ps);
9d67006e
AD		 431 int ret;
432
433 if ((new_state->sclk_high == old_state->sclk_high) &&
434 (new_state->sclk_low == old_state->sclk_low))
435 return 0;
436
437 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
438 new_state->sclk_low, false, &min_dividers);
439 if (ret)
440 return ret;
441
442 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
443 new_state->sclk_high, false, &max_dividers);
444 if (ret)
445 return ret;
446
447 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
448 old_state->sclk_high, false, &current_max_dividers);
449 if (ret)
450 return ret;
451
ce7b30e0
AD		 452 if ((min_dividers.ref_div != max_dividers.ref_div) ||
453 (min_dividers.post_div != max_dividers.post_div) ||
454 (max_dividers.ref_div != current_max_dividers.ref_div) ||
455 (max_dividers.post_div != current_max_dividers.post_div))
456 return -EINVAL;
457
63580c3e 458 rs780_force_fbdiv(rdev, max_dividers.fb_div);
9d67006e
AD		 459
460 if (max_dividers.fb_div > min_dividers.fb_div) {
461 WREG32_P(FVTHROT_FBDIV_REG0,
462 MIN_FEEDBACK_DIV(min_dividers.fb_div) |
463 MAX_FEEDBACK_DIV(max_dividers.fb_div),
464 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
465
466 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
467 }
468
469 return 0;
470}
471
f5d73a80
AD		 472static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
473 struct radeon_ps *new_ps,
474 struct radeon_ps *old_ps)
9d67006e 475{
f5d73a80
AD		 476 struct igp_ps *new_state = rs780_get_ps(new_ps);
477 struct igp_ps *old_state = rs780_get_ps(old_ps);
9d67006e
AD		 478 struct igp_power_info *pi = rs780_get_pi(rdev);
479
480 if ((new_state->sclk_high == old_state->sclk_high) &&
481 (new_state->sclk_low == old_state->sclk_low))
482 return;
483
484 if (pi->crtc_id == 0)
485 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
486 else
487 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
488
489}
490
f5d73a80
AD		 491static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
492 struct radeon_ps *new_ps,
493 struct radeon_ps *old_ps)
9d67006e 494{
f5d73a80
AD		 495 struct igp_ps *new_state = rs780_get_ps(new_ps);
496 struct igp_ps *old_state = rs780_get_ps(old_ps);
9d67006e
AD		 497
498 if ((new_state->sclk_high == old_state->sclk_high) &&
499 (new_state->sclk_low == old_state->sclk_low))
500 return;
501
502 rs780_clk_scaling_enable(rdev, true);
503}
504
505static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
506 enum rs780_vddc_level vddc)
507{
508 struct igp_power_info *pi = rs780_get_pi(rdev);
509
510 if (vddc == RS780_VDDC_LEVEL_HIGH)
511 return pi->max_voltage;
512 else if (vddc == RS780_VDDC_LEVEL_LOW)
513 return pi->min_voltage;
514 else
515 return pi->max_voltage;
516}
517
f5d73a80
AD		 518static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
519 struct radeon_ps *new_ps)
9d67006e 520{
f5d73a80 521 struct igp_ps *new_state = rs780_get_ps(new_ps);
9d67006e
AD		 522 struct igp_power_info *pi = rs780_get_pi(rdev);
523 enum rs780_vddc_level vddc_high, vddc_low;
524
525 udelay(100);
526
527 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
528 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
529 return;
530
531 vddc_high = rs780_get_voltage_for_vddc_level(rdev,
532 new_state->max_voltage);
533 vddc_low = rs780_get_voltage_for_vddc_level(rdev,
534 new_state->min_voltage);
535
536 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
537
538 udelay(1);
539 if (vddc_high > vddc_low) {
540 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
541 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
542
543 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
544 } else if (vddc_high == vddc_low) {
545 if (pi->max_voltage != vddc_high) {
546 WREG32_P(FVTHROT_PWM_CTRL_REG0,
547 STARTING_PWM_HIGHTIME(vddc_high),
548 ~STARTING_PWM_HIGHTIME_MASK);
549
550 WREG32_P(FVTHROT_PWM_CTRL_REG0,
551 FORCE_STARTING_PWM_HIGHTIME,
552 ~FORCE_STARTING_PWM_HIGHTIME);
553 }
554 }
555
556 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
557}
558
915203c1
AD		 559static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
560 struct radeon_ps *new_ps,
561 struct radeon_ps *old_ps)
562{
563 struct igp_ps *new_state = rs780_get_ps(new_ps);
564 struct igp_ps *current_state = rs780_get_ps(old_ps);
565
566 if ((new_ps->vclk == old_ps->vclk) &&
567 (new_ps->dclk == old_ps->dclk))
568 return;
569
570 if (new_state->sclk_high >= current_state->sclk_high)
571 return;
572
573 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
574}
575
576static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
577 struct radeon_ps *new_ps,
578 struct radeon_ps *old_ps)
579{
580 struct igp_ps *new_state = rs780_get_ps(new_ps);
581 struct igp_ps *current_state = rs780_get_ps(old_ps);
582
583 if ((new_ps->vclk == old_ps->vclk) &&
584 (new_ps->dclk == old_ps->dclk))
585 return;
586
587 if (new_state->sclk_high < current_state->sclk_high)
588 return;
589
590 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
591}
592
9d67006e
AD		 593int rs780_dpm_enable(struct radeon_device *rdev)
594{
595 struct igp_power_info *pi = rs780_get_pi(rdev);
f5d73a80 596 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
a172230f 597 int ret;
9d67006e
AD		 598
599 rs780_get_pm_mode_parameters(rdev);
600 rs780_disable_vbios_powersaving(rdev);
601
602 if (r600_dynamicpm_enabled(rdev))
603 return -EINVAL;
a172230f
AD		 604 ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
605 if (ret)
606 return ret;
9d67006e
AD		 607 rs780_start_dpm(rdev);
608
609 rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
610 rs780_preset_starting_fbdiv(rdev);
611 if (pi->voltage_control)
612 rs780_voltage_scaling_init(rdev);
613 rs780_clk_scaling_enable(rdev, true);
614 rs780_set_engine_clock_sc(rdev);
615 rs780_set_engine_clock_wfc(rdev);
616 rs780_program_at(rdev);
617 rs780_set_engine_clock_tdc(rdev);
618 rs780_set_engine_clock_ssc(rdev);
619
620 if (pi->gfx_clock_gating)
621 r600_gfx_clockgating_enable(rdev, true);
622
4a6369e9 623 if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
a172230f
AD		 624 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
625 if (ret)
626 return ret;
4a6369e9
AD		 627 rdev->irq.dpm_thermal = true;
628 radeon_irq_set(rdev);
629 }
630
9d67006e
AD		 631 return 0;
632}
633
634void rs780_dpm_disable(struct radeon_device *rdev)
635{
636 struct igp_power_info *pi = rs780_get_pi(rdev);
637
638 r600_dynamicpm_enable(rdev, false);
639
640 rs780_clk_scaling_enable(rdev, false);
641 rs780_voltage_scaling_enable(rdev, false);
642
643 if (pi->gfx_clock_gating)
644 r600_gfx_clockgating_enable(rdev, false);
4a6369e9
AD		 645
646 if (rdev->irq.installed &&
647 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
648 rdev->irq.dpm_thermal = false;
649 radeon_irq_set(rdev);
650 }
9d67006e
AD		 651}
652
653int rs780_dpm_set_power_state(struct radeon_device *rdev)
654{
655 struct igp_power_info *pi = rs780_get_pi(rdev);
f5d73a80
AD		 656 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
657 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
a172230f 658 int ret;
9d67006e
AD		 659
660 rs780_get_pm_mode_parameters(rdev);
661
915203c1
AD		 662 rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
663
9d67006e 664 if (pi->voltage_control) {
63580c3e 665 rs780_force_voltage(rdev, pi->max_voltage);
9d67006e
AD		 666 mdelay(5);
667 }
668
a172230f
AD		 669 ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
670 if (ret)
671 return ret;
f5d73a80 672 rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
9d67006e 673
f5d73a80 674 rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
9d67006e
AD		 675
676 if (pi->voltage_control)
f5d73a80 677 rs780_enable_voltage_scaling(rdev, new_ps);
9d67006e 678
915203c1
AD		 679 rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
680
9d67006e
AD		 681 return 0;
682}
683
684void rs780_dpm_setup_asic(struct radeon_device *rdev)
685{
686
687}
688
689void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
690{
691 rs780_get_pm_mode_parameters(rdev);
692 rs780_program_at(rdev);
693}
694
695union igp_info {
696 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
697 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
698};
699
700union power_info {
701 struct _ATOM_POWERPLAY_INFO info;
702 struct _ATOM_POWERPLAY_INFO_V2 info_2;
703 struct _ATOM_POWERPLAY_INFO_V3 info_3;
704 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
705 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
706 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
707};
708
709union pplib_clock_info {
710 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
711 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
712 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
713 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
714};
715
716union pplib_power_state {
717 struct _ATOM_PPLIB_STATE v1;
718 struct _ATOM_PPLIB_STATE_V2 v2;
719};
720
721static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
722 struct radeon_ps *rps,
723 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
724 u8 table_rev)
725{
726 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
727 rps->class = le16_to_cpu(non_clock_info->usClassification);
728 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
729
730 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
731 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
732 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
9d67006e
AD		 733 } else {
734 rps->vclk = 0;
735 rps->dclk = 0;
736 }
737
84f3d9f7
AD		 738 if (r600_is_uvd_state(rps->class, rps->class2)) {
739 if ((rps->vclk == 0) || (rps->dclk == 0)) {
740 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
741 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
742 }
743 }
744
9d67006e
AD		 745 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
746 rdev->pm.dpm.boot_ps = rps;
747 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
748 rdev->pm.dpm.uvd_ps = rps;
749}
750
751static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
752 struct radeon_ps *rps,
753 union pplib_clock_info *clock_info)
754{
755 struct igp_ps *ps = rs780_get_ps(rps);
756 u32 sclk;
757
758 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
759 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
760 ps->sclk_low = sclk;
761 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
762 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
763 ps->sclk_high = sclk;
764 switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
765 case ATOM_PPLIB_RS780_VOLTAGE_NONE:
766 default:
767 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
768 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
769 break;
770 case ATOM_PPLIB_RS780_VOLTAGE_LOW:
771 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
772 ps->max_voltage = RS780_VDDC_LEVEL_LOW;
773 break;
774 case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
775 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
776 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
777 break;
778 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
779 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
780 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
781 break;
782 }
783 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
784
785 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
786 ps->sclk_low = rdev->clock.default_sclk;
787 ps->sclk_high = rdev->clock.default_sclk;
788 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
789 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
790 }
791}
792
793static int rs780_parse_power_table(struct radeon_device *rdev)
794{
795 struct radeon_mode_info *mode_info = &rdev->mode_info;
796 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
797 union pplib_power_state *power_state;
798 int i;
799 union pplib_clock_info *clock_info;
800 union power_info *power_info;
801 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
802 u16 data_offset;
803 u8 frev, crev;
804 struct igp_ps *ps;
805
806 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
807 &frev, &crev, &data_offset))
808 return -EINVAL;
809 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
810
811 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
812 power_info->pplib.ucNumStates, GFP_KERNEL);
813 if (!rdev->pm.dpm.ps)
814 return -ENOMEM;
815 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
816 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
817 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
818
819 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
820 power_state = (union pplib_power_state *)
821 (mode_info->atom_context->bios + data_offset +
822 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
823 i * power_info->pplib.ucStateEntrySize);
824 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
825 (mode_info->atom_context->bios + data_offset +
826 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
827 (power_state->v1.ucNonClockStateIndex *
828 power_info->pplib.ucNonClockSize));
829 if (power_info->pplib.ucStateEntrySize - 1) {
830 clock_info = (union pplib_clock_info *)
831 (mode_info->atom_context->bios + data_offset +
832 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
833 (power_state->v1.ucClockStateIndices[0] *
834 power_info->pplib.ucClockInfoSize));
835 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
836 if (ps == NULL) {
837 kfree(rdev->pm.dpm.ps);
838 return -ENOMEM;
839 }
840 rdev->pm.dpm.ps[i].ps_priv = ps;
841 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
842 non_clock_info,
843 power_info->pplib.ucNonClockSize);
844 rs780_parse_pplib_clock_info(rdev,
845 &rdev->pm.dpm.ps[i],
846 clock_info);
847 }
848 }
849 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
850 return 0;
851}
852
853int rs780_dpm_init(struct radeon_device *rdev)
854{
855 struct igp_power_info *pi;
856 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
857 union igp_info *info;
858 u16 data_offset;
859 u8 frev, crev;
860 int ret;
861
862 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
863 if (pi == NULL)
864 return -ENOMEM;
865 rdev->pm.dpm.priv = pi;
866
867 ret = rs780_parse_power_table(rdev);
868 if (ret)
869 return ret;
870
871 pi->voltage_control = false;
872 pi->gfx_clock_gating = true;
873
874 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
875 &frev, &crev, &data_offset)) {
876 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
877
878 /* Get various system informations from bios */
879 switch (crev) {
880 case 1:
881 pi->num_of_cycles_in_period =
882 info->info.ucNumberOfCyclesInPeriod;
883 pi->num_of_cycles_in_period |=
884 info->info.ucNumberOfCyclesInPeriodHi << 8;
885 pi->invert_pwm_required =
886 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
887 pi->boot_voltage = info->info.ucStartingPWM_HighTime;
888 pi->max_voltage = info->info.ucMaxNBVoltage;
889 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
890 pi->min_voltage = info->info.ucMinNBVoltage;
891 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
892 pi->inter_voltage_low =
893 le16_to_cpu(info->info.usInterNBVoltageLow);
894 pi->inter_voltage_high =
895 le16_to_cpu(info->info.usInterNBVoltageHigh);
896 pi->voltage_control = true;
897 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
898 break;
899 case 2:
900 pi->num_of_cycles_in_period =
901 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
902 pi->invert_pwm_required =
903 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
904 pi->boot_voltage =
905 le16_to_cpu(info->info_2.usBootUpNBVoltage);
906 pi->max_voltage =
907 le16_to_cpu(info->info_2.usMaxNBVoltage);
908 pi->min_voltage =
909 le16_to_cpu(info->info_2.usMinNBVoltage);
910 pi->system_config =
911 le32_to_cpu(info->info_2.ulSystemConfig);
912 pi->pwm_voltage_control =
913 (pi->system_config & 0x4) ? true : false;
914 pi->voltage_control = true;
915 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
916 break;
917 default:
918 DRM_ERROR("No integrated system info for your GPU\n");
919 return -EINVAL;
920 }
921 if (pi->min_voltage > pi->max_voltage)
922 pi->voltage_control = false;
923 if (pi->pwm_voltage_control) {
924 if ((pi->num_of_cycles_in_period == 0) ||
925 (pi->max_voltage == 0) ||
926 (pi->min_voltage == 0))
927 pi->voltage_control = false;
928 } else {
929 if ((pi->num_of_cycles_in_period == 0) ||
930 (pi->max_voltage == 0))
931 pi->voltage_control = false;
932 }
933
934 return 0;
935 }
936 radeon_dpm_fini(rdev);
937 return -EINVAL;
938}
939
940void rs780_dpm_print_power_state(struct radeon_device *rdev,
941 struct radeon_ps *rps)
942{
943 struct igp_ps *ps = rs780_get_ps(rps);
944
945 r600_dpm_print_class_info(rps->class, rps->class2);
946 r600_dpm_print_cap_info(rps->caps);
947 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
948 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n",
949 ps->sclk_low, ps->min_voltage);
950 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n",
951 ps->sclk_high, ps->max_voltage);
952 r600_dpm_print_ps_status(rdev, rps);
953}
954
955void rs780_dpm_fini(struct radeon_device *rdev)
956{
957 int i;
958
959 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
960 kfree(rdev->pm.dpm.ps[i].ps_priv);
961 }
962 kfree(rdev->pm.dpm.ps);
963 kfree(rdev->pm.dpm.priv);
964}
965
966u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
967{
968 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
969
970 if (low)
971 return requested_state->sclk_low;
972 else
973 return requested_state->sclk_high;
974}
975
976u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
977{
978 struct igp_power_info *pi = rs780_get_pi(rdev);
979
980 return pi->bootup_uma_clk;
981}
444bddc4
AD		 982
983void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
984 struct seq_file *m)
985{
986 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
987 struct igp_ps *ps = rs780_get_ps(rps);
988 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
989 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
990 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
991 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
992 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
993 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
994 (post_div * ref_div);
995
996 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
997
998 /* guess based on the current sclk */
999 if (sclk < (ps->sclk_low + 500))
1000 seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n",
1001 ps->sclk_low, ps->min_voltage);
1002 else
1003 seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",
1004 ps->sclk_high, ps->max_voltage);
1005}
63580c3e
AB		 1006
1007int rs780_dpm_force_performance_level(struct radeon_device *rdev,
1008 enum radeon_dpm_forced_level level)
1009{
1010 struct igp_power_info *pi = rs780_get_pi(rdev);
1011 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1012 struct igp_ps *ps = rs780_get_ps(rps);
1013 struct atom_clock_dividers dividers;
1014 int ret;
1015
1016 rs780_clk_scaling_enable(rdev, false);
1017 rs780_voltage_scaling_enable(rdev, false);
1018
1019 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1020 if (pi->voltage_control)
1021 rs780_force_voltage(rdev, pi->max_voltage);
1022
1023 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1024 ps->sclk_high, false, &dividers);
1025 if (ret)
1026 return ret;
1027
1028 rs780_force_fbdiv(rdev, dividers.fb_div);
1029 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1030 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1031 ps->sclk_low, false, &dividers);
1032 if (ret)
1033 return ret;
1034
1035 rs780_force_fbdiv(rdev, dividers.fb_div);
1036
1037 if (pi->voltage_control)
1038 rs780_force_voltage(rdev, pi->min_voltage);
1039 } else {
1040 if (pi->voltage_control)
1041 rs780_force_voltage(rdev, pi->max_voltage);
1042
1043 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
1044 rs780_clk_scaling_enable(rdev, true);
1045
1046 if (pi->voltage_control) {
1047 rs780_voltage_scaling_enable(rdev, true);
1048 rs780_enable_voltage_scaling(rdev, rps);
1049 }
1050 }
1051
1052 rdev->pm.dpm.forced_level = level;
1053
1054 return 0;
1055}
Linux kernel - Deliverables
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