Commit | Line | Data |
---|---|---|
9d67006e AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #ifndef __RS780_DPM_H__ | |
24 | #define __RS780_DPM_H__ | |
25 | ||
26 | enum rs780_vddc_level { | |
27 | RS780_VDDC_LEVEL_UNKNOWN = 0, | |
28 | RS780_VDDC_LEVEL_LOW = 1, | |
29 | RS780_VDDC_LEVEL_HIGH = 2, | |
30 | }; | |
31 | ||
32 | struct igp_power_info { | |
33 | /* flags */ | |
34 | bool invert_pwm_required; | |
35 | bool pwm_voltage_control; | |
36 | bool voltage_control; | |
37 | bool gfx_clock_gating; | |
38 | /* stored values */ | |
39 | u32 system_config; | |
40 | u32 bootup_uma_clk; | |
41 | u16 max_voltage; | |
42 | u16 min_voltage; | |
43 | u16 boot_voltage; | |
44 | u16 inter_voltage_low; | |
45 | u16 inter_voltage_high; | |
46 | u16 num_of_cycles_in_period; | |
47 | /* variable */ | |
48 | int crtc_id; | |
49 | int refresh_rate; | |
50 | }; | |
51 | ||
52 | struct igp_ps { | |
53 | enum rs780_vddc_level min_voltage; | |
54 | enum rs780_vddc_level max_voltage; | |
55 | u32 sclk_low; | |
56 | u32 sclk_high; | |
57 | u32 flags; | |
58 | }; | |
59 | ||
60 | #define RS780_CGFTV_DFLT 0x0303000f | |
61 | #define RS780_FBDIVTIMERVAL_DFLT 0x2710 | |
62 | ||
63 | #define RS780_FVTHROTUTC0_DFLT 0x04010040 | |
64 | #define RS780_FVTHROTUTC1_DFLT 0x04010040 | |
65 | #define RS780_FVTHROTUTC2_DFLT 0x04010040 | |
66 | #define RS780_FVTHROTUTC3_DFLT 0x04010040 | |
67 | #define RS780_FVTHROTUTC4_DFLT 0x04010040 | |
68 | ||
69 | #define RS780_FVTHROTDTC0_DFLT 0x04010040 | |
70 | #define RS780_FVTHROTDTC1_DFLT 0x04010040 | |
71 | #define RS780_FVTHROTDTC2_DFLT 0x04010040 | |
72 | #define RS780_FVTHROTDTC3_DFLT 0x04010040 | |
73 | #define RS780_FVTHROTDTC4_DFLT 0x04010040 | |
74 | ||
75 | #define RS780_FVTHROTFBUSREG0_DFLT 0x00001001 | |
76 | #define RS780_FVTHROTFBUSREG1_DFLT 0x00002002 | |
77 | #define RS780_FVTHROTFBDSREG0_DFLT 0x00004001 | |
78 | #define RS780_FVTHROTFBDSREG1_DFLT 0x00020010 | |
79 | ||
80 | #define RS780_FVTHROTPWMUSREG0_DFLT 0x00002001 | |
81 | #define RS780_FVTHROTPWMUSREG1_DFLT 0x00004003 | |
82 | #define RS780_FVTHROTPWMDSREG0_DFLT 0x00002001 | |
83 | #define RS780_FVTHROTPWMDSREG1_DFLT 0x00004003 | |
84 | ||
85 | #define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x37 | |
86 | #define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x4b | |
87 | #define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT 0x8b | |
88 | ||
89 | #define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8b | |
90 | #define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8c | |
91 | #define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xb5 | |
92 | ||
93 | #define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8d | |
94 | #define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8e | |
95 | #define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xBa | |
96 | ||
97 | #define RS780_FVTHROTPWMRANGE0_GPIO_DFLT 0x1a | |
98 | #define RS780_FVTHROTPWMRANGE1_GPIO_DFLT 0x1a | |
99 | #define RS780_FVTHROTPWMRANGE2_GPIO_DFLT 0x0 | |
100 | #define RS780_FVTHROTPWMRANGE3_GPIO_DFLT 0x0 | |
101 | ||
102 | #define RS780_SLOWCLKFEEDBACKDIV_DFLT 110 | |
103 | ||
104 | #define RS780_CGCLKGATING_DFLT 0x0000E204 | |
105 | ||
106 | #define RS780_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ | |
107 | #define RS780_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ | |
108 | ||
109 | #endif |