Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
29 | #include "drmP.h" | |
3ce0a23d | 30 | #include "rv515d.h" |
771fe6b9 | 31 | #include "radeon.h" |
d39c3b89 | 32 | #include "atom.h" |
50f15303 | 33 | #include "rv515_reg_safe.h" |
d39c3b89 JG |
34 | |
35 | /* This files gather functions specifics to: rv515 */ | |
771fe6b9 JG |
36 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
37 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); | |
38 | void rv515_gpu_init(struct radeon_device *rdev); | |
39 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); | |
40 | ||
f0ed1f65 | 41 | void rv515_debugfs(struct radeon_device *rdev) |
771fe6b9 | 42 | { |
771fe6b9 JG |
43 | if (r100_debugfs_rbbm_init(rdev)) { |
44 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
45 | } | |
46 | if (rv515_debugfs_pipes_info_init(rdev)) { | |
47 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
48 | } | |
49 | if (rv515_debugfs_ga_info_init(rdev)) { | |
50 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
51 | } | |
771fe6b9 JG |
52 | } |
53 | ||
771fe6b9 JG |
54 | void rv515_ring_start(struct radeon_device *rdev) |
55 | { | |
771fe6b9 JG |
56 | int r; |
57 | ||
771fe6b9 JG |
58 | r = radeon_ring_lock(rdev, 64); |
59 | if (r) { | |
60 | return; | |
61 | } | |
c93bb85b | 62 | radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); |
771fe6b9 | 63 | radeon_ring_write(rdev, |
c93bb85b JG |
64 | ISYNC_ANY2D_IDLE3D | |
65 | ISYNC_ANY3D_IDLE2D | | |
66 | ISYNC_WAIT_IDLEGUI | | |
67 | ISYNC_CPSCRATCH_IDLEGUI); | |
68 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); | |
69 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | |
771fe6b9 JG |
70 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
71 | radeon_ring_write(rdev, 1 << 31); | |
c93bb85b | 72 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
771fe6b9 | 73 | radeon_ring_write(rdev, 0); |
c93bb85b | 74 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
771fe6b9 JG |
75 | radeon_ring_write(rdev, 0); |
76 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); | |
77 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); | |
c93bb85b | 78 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
771fe6b9 | 79 | radeon_ring_write(rdev, 0); |
c93bb85b JG |
80 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
81 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); | |
82 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); | |
83 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); | |
84 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); | |
85 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | |
86 | radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); | |
771fe6b9 | 87 | radeon_ring_write(rdev, 0); |
c93bb85b JG |
88 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
89 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); | |
90 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); | |
91 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); | |
92 | radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); | |
771fe6b9 | 93 | radeon_ring_write(rdev, |
c93bb85b JG |
94 | ((6 << MS_X0_SHIFT) | |
95 | (6 << MS_Y0_SHIFT) | | |
96 | (6 << MS_X1_SHIFT) | | |
97 | (6 << MS_Y1_SHIFT) | | |
98 | (6 << MS_X2_SHIFT) | | |
99 | (6 << MS_Y2_SHIFT) | | |
100 | (6 << MSBD0_Y_SHIFT) | | |
101 | (6 << MSBD0_X_SHIFT))); | |
102 | radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); | |
771fe6b9 | 103 | radeon_ring_write(rdev, |
c93bb85b JG |
104 | ((6 << MS_X3_SHIFT) | |
105 | (6 << MS_Y3_SHIFT) | | |
106 | (6 << MS_X4_SHIFT) | | |
107 | (6 << MS_Y4_SHIFT) | | |
108 | (6 << MS_X5_SHIFT) | | |
109 | (6 << MS_Y5_SHIFT) | | |
110 | (6 << MSBD1_SHIFT))); | |
111 | radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); | |
112 | radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); | |
113 | radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); | |
114 | radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); | |
115 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); | |
116 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); | |
068a117c JG |
117 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
118 | radeon_ring_write(rdev, 0); | |
771fe6b9 JG |
119 | radeon_ring_unlock_commit(rdev); |
120 | } | |
121 | ||
771fe6b9 JG |
122 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
123 | { | |
124 | unsigned i; | |
125 | uint32_t tmp; | |
126 | ||
127 | for (i = 0; i < rdev->usec_timeout; i++) { | |
128 | /* read MC_STATUS */ | |
c93bb85b JG |
129 | tmp = RREG32_MC(MC_STATUS); |
130 | if (tmp & MC_STATUS_IDLE) { | |
771fe6b9 JG |
131 | return 0; |
132 | } | |
133 | DRM_UDELAY(1); | |
134 | } | |
135 | return -1; | |
136 | } | |
137 | ||
d39c3b89 JG |
138 | void rv515_vga_render_disable(struct radeon_device *rdev) |
139 | { | |
140 | WREG32(R_000300_VGA_RENDER_CONTROL, | |
141 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); | |
142 | } | |
143 | ||
771fe6b9 JG |
144 | void rv515_gpu_init(struct radeon_device *rdev) |
145 | { | |
146 | unsigned pipe_select_current, gb_pipe_select, tmp; | |
147 | ||
148 | r100_hdp_reset(rdev); | |
149 | r100_rb2d_reset(rdev); | |
150 | ||
151 | if (r100_gui_wait_for_idle(rdev)) { | |
152 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
153 | "reseting GPU. Bad things might happen.\n"); | |
154 | } | |
155 | ||
d39c3b89 | 156 | rv515_vga_render_disable(rdev); |
771fe6b9 JG |
157 | |
158 | r420_pipes_init(rdev); | |
159 | gb_pipe_select = RREG32(0x402C); | |
160 | tmp = RREG32(0x170C); | |
161 | pipe_select_current = (tmp >> 2) & 3; | |
162 | tmp = (1 << pipe_select_current) | | |
163 | (((gb_pipe_select >> 8) & 0xF) << 4); | |
164 | WREG32_PLL(0x000D, tmp); | |
165 | if (r100_gui_wait_for_idle(rdev)) { | |
166 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
167 | "reseting GPU. Bad things might happen.\n"); | |
168 | } | |
169 | if (rv515_mc_wait_for_idle(rdev)) { | |
170 | printk(KERN_WARNING "Failed to wait MC idle while " | |
171 | "programming pipes. Bad things might happen.\n"); | |
172 | } | |
173 | } | |
174 | ||
175 | int rv515_ga_reset(struct radeon_device *rdev) | |
176 | { | |
177 | uint32_t tmp; | |
178 | bool reinit_cp; | |
179 | int i; | |
180 | ||
181 | reinit_cp = rdev->cp.ready; | |
182 | rdev->cp.ready = false; | |
183 | for (i = 0; i < rdev->usec_timeout; i++) { | |
c93bb85b JG |
184 | WREG32(CP_CSQ_MODE, 0); |
185 | WREG32(CP_CSQ_CNTL, 0); | |
186 | WREG32(RBBM_SOFT_RESET, 0x32005); | |
187 | (void)RREG32(RBBM_SOFT_RESET); | |
771fe6b9 | 188 | udelay(200); |
c93bb85b | 189 | WREG32(RBBM_SOFT_RESET, 0); |
771fe6b9 JG |
190 | /* Wait to prevent race in RBBM_STATUS */ |
191 | mdelay(1); | |
c93bb85b | 192 | tmp = RREG32(RBBM_STATUS); |
771fe6b9 JG |
193 | if (tmp & ((1 << 20) | (1 << 26))) { |
194 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); | |
195 | /* GA still busy soft reset it */ | |
196 | WREG32(0x429C, 0x200); | |
c93bb85b | 197 | WREG32(VAP_PVS_STATE_FLUSH_REG, 0); |
771fe6b9 JG |
198 | WREG32(0x43E0, 0); |
199 | WREG32(0x43E4, 0); | |
200 | WREG32(0x24AC, 0); | |
201 | } | |
202 | /* Wait to prevent race in RBBM_STATUS */ | |
203 | mdelay(1); | |
c93bb85b | 204 | tmp = RREG32(RBBM_STATUS); |
771fe6b9 JG |
205 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
206 | break; | |
207 | } | |
208 | } | |
209 | for (i = 0; i < rdev->usec_timeout; i++) { | |
c93bb85b | 210 | tmp = RREG32(RBBM_STATUS); |
771fe6b9 JG |
211 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
212 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", | |
213 | tmp); | |
214 | DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C)); | |
215 | DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0)); | |
216 | DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724)); | |
217 | if (reinit_cp) { | |
218 | return r100_cp_init(rdev, rdev->cp.ring_size); | |
219 | } | |
220 | return 0; | |
221 | } | |
222 | DRM_UDELAY(1); | |
223 | } | |
c93bb85b | 224 | tmp = RREG32(RBBM_STATUS); |
771fe6b9 JG |
225 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
226 | return -1; | |
227 | } | |
228 | ||
229 | int rv515_gpu_reset(struct radeon_device *rdev) | |
230 | { | |
231 | uint32_t status; | |
232 | ||
233 | /* reset order likely matter */ | |
c93bb85b | 234 | status = RREG32(RBBM_STATUS); |
771fe6b9 JG |
235 | /* reset HDP */ |
236 | r100_hdp_reset(rdev); | |
237 | /* reset rb2d */ | |
238 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { | |
239 | r100_rb2d_reset(rdev); | |
240 | } | |
241 | /* reset GA */ | |
242 | if (status & ((1 << 20) | (1 << 26))) { | |
243 | rv515_ga_reset(rdev); | |
244 | } | |
245 | /* reset CP */ | |
c93bb85b | 246 | status = RREG32(RBBM_STATUS); |
771fe6b9 JG |
247 | if (status & (1 << 16)) { |
248 | r100_cp_reset(rdev); | |
249 | } | |
250 | /* Check if GPU is idle */ | |
c93bb85b | 251 | status = RREG32(RBBM_STATUS); |
771fe6b9 JG |
252 | if (status & (1 << 31)) { |
253 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); | |
254 | return -1; | |
255 | } | |
256 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); | |
257 | return 0; | |
258 | } | |
259 | ||
771fe6b9 JG |
260 | static void rv515_vram_get_type(struct radeon_device *rdev) |
261 | { | |
262 | uint32_t tmp; | |
263 | ||
264 | rdev->mc.vram_width = 128; | |
265 | rdev->mc.vram_is_ddr = true; | |
c93bb85b | 266 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
771fe6b9 JG |
267 | switch (tmp) { |
268 | case 0: | |
269 | rdev->mc.vram_width = 64; | |
270 | break; | |
271 | case 1: | |
272 | rdev->mc.vram_width = 128; | |
273 | break; | |
274 | default: | |
275 | rdev->mc.vram_width = 128; | |
276 | break; | |
277 | } | |
278 | } | |
279 | ||
280 | void rv515_vram_info(struct radeon_device *rdev) | |
281 | { | |
c93bb85b JG |
282 | fixed20_12 a; |
283 | ||
771fe6b9 | 284 | rv515_vram_get_type(rdev); |
c93bb85b | 285 | |
0924d942 | 286 | r100_vram_init_sizes(rdev); |
c93bb85b JG |
287 | /* FIXME: we should enforce default clock in case GPU is not in |
288 | * default setup | |
289 | */ | |
290 | a.full = rfixed_const(100); | |
291 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); | |
292 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | |
771fe6b9 JG |
293 | } |
294 | ||
771fe6b9 JG |
295 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
296 | { | |
297 | uint32_t r; | |
298 | ||
c93bb85b JG |
299 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
300 | r = RREG32(MC_IND_DATA); | |
301 | WREG32(MC_IND_INDEX, 0); | |
771fe6b9 JG |
302 | return r; |
303 | } | |
304 | ||
305 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
306 | { | |
c93bb85b JG |
307 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
308 | WREG32(MC_IND_DATA, (v)); | |
309 | WREG32(MC_IND_INDEX, 0); | |
771fe6b9 JG |
310 | } |
311 | ||
771fe6b9 JG |
312 | #if defined(CONFIG_DEBUG_FS) |
313 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) | |
314 | { | |
315 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
316 | struct drm_device *dev = node->minor->dev; | |
317 | struct radeon_device *rdev = dev->dev_private; | |
318 | uint32_t tmp; | |
319 | ||
c93bb85b | 320 | tmp = RREG32(GB_PIPE_SELECT); |
771fe6b9 | 321 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
c93bb85b | 322 | tmp = RREG32(SU_REG_DEST); |
771fe6b9 | 323 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
c93bb85b | 324 | tmp = RREG32(GB_TILE_CONFIG); |
771fe6b9 | 325 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
c93bb85b | 326 | tmp = RREG32(DST_PIPE_CONFIG); |
771fe6b9 JG |
327 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
328 | return 0; | |
329 | } | |
330 | ||
331 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) | |
332 | { | |
333 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
334 | struct drm_device *dev = node->minor->dev; | |
335 | struct radeon_device *rdev = dev->dev_private; | |
336 | uint32_t tmp; | |
337 | ||
338 | tmp = RREG32(0x2140); | |
339 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); | |
340 | radeon_gpu_reset(rdev); | |
341 | tmp = RREG32(0x425C); | |
342 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); | |
343 | return 0; | |
344 | } | |
345 | ||
346 | static struct drm_info_list rv515_pipes_info_list[] = { | |
347 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, | |
348 | }; | |
349 | ||
350 | static struct drm_info_list rv515_ga_info_list[] = { | |
351 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, | |
352 | }; | |
353 | #endif | |
354 | ||
355 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) | |
356 | { | |
357 | #if defined(CONFIG_DEBUG_FS) | |
358 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); | |
359 | #else | |
360 | return 0; | |
361 | #endif | |
362 | } | |
363 | ||
364 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev) | |
365 | { | |
366 | #if defined(CONFIG_DEBUG_FS) | |
367 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); | |
368 | #else | |
369 | return 0; | |
370 | #endif | |
371 | } | |
068a117c | 372 | |
d39c3b89 JG |
373 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
374 | { | |
375 | save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); | |
376 | save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); | |
377 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); | |
378 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); | |
379 | save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); | |
380 | save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); | |
381 | ||
382 | /* Stop all video */ | |
d39c3b89 JG |
383 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
384 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); | |
385 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); | |
386 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); | |
387 | WREG32(R_006080_D1CRTC_CONTROL, 0); | |
388 | WREG32(R_006880_D2CRTC_CONTROL, 0); | |
389 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | |
390 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | |
ef630627 DA |
391 | WREG32(R_000330_D1VGA_CONTROL, 0); |
392 | WREG32(R_000338_D2VGA_CONTROL, 0); | |
d39c3b89 JG |
393 | } |
394 | ||
395 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) | |
396 | { | |
397 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
398 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
399 | WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
400 | WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); | |
401 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); | |
402 | /* Unlock host access */ | |
403 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); | |
404 | mdelay(1); | |
405 | /* Restore video state */ | |
ef630627 DA |
406 | WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); |
407 | WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); | |
d39c3b89 JG |
408 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
409 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); | |
410 | WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); | |
411 | WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); | |
412 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | |
413 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | |
d39c3b89 JG |
414 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
415 | } | |
416 | ||
417 | void rv515_mc_program(struct radeon_device *rdev) | |
418 | { | |
419 | struct rv515_mc_save save; | |
420 | ||
421 | /* Stops all mc clients */ | |
422 | rv515_mc_stop(rdev, &save); | |
423 | ||
424 | /* Wait for mc idle */ | |
425 | if (rv515_mc_wait_for_idle(rdev)) | |
426 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
427 | /* Write VRAM size in case we are limiting it */ | |
428 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
429 | /* Program MC, should be a 32bits limited address space */ | |
430 | WREG32_MC(R_000001_MC_FB_LOCATION, | |
431 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | | |
432 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
433 | WREG32(R_000134_HDP_FB_LOCATION, | |
434 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
435 | if (rdev->flags & RADEON_IS_AGP) { | |
436 | WREG32_MC(R_000002_MC_AGP_LOCATION, | |
437 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
438 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
439 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
440 | WREG32_MC(R_000004_MC_AGP_BASE_2, | |
441 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); | |
442 | } else { | |
443 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); | |
444 | WREG32_MC(R_000003_MC_AGP_BASE, 0); | |
445 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); | |
446 | } | |
447 | ||
448 | rv515_mc_resume(rdev, &save); | |
449 | } | |
450 | ||
451 | void rv515_clock_startup(struct radeon_device *rdev) | |
452 | { | |
453 | if (radeon_dynclks != -1 && radeon_dynclks) | |
454 | radeon_atom_set_clock_gating(rdev, 1); | |
455 | /* We need to force on some of the block */ | |
456 | WREG32_PLL(R_00000F_CP_DYN_CNTL, | |
457 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); | |
458 | WREG32_PLL(R_000011_E2_DYN_CNTL, | |
459 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); | |
460 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, | |
461 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); | |
462 | } | |
463 | ||
464 | static int rv515_startup(struct radeon_device *rdev) | |
465 | { | |
466 | int r; | |
467 | ||
468 | rv515_mc_program(rdev); | |
469 | /* Resume clock */ | |
470 | rv515_clock_startup(rdev); | |
471 | /* Initialize GPU configuration (# pipes, ...) */ | |
472 | rv515_gpu_init(rdev); | |
473 | /* Initialize GART (initialize after TTM so we can allocate | |
474 | * memory through TTM but finalize after TTM) */ | |
475 | if (rdev->flags & RADEON_IS_PCIE) { | |
476 | r = rv370_pcie_gart_enable(rdev); | |
477 | if (r) | |
478 | return r; | |
479 | } | |
480 | /* Enable IRQ */ | |
481 | rdev->irq.sw_int = true; | |
ac447df4 | 482 | rs600_irq_set(rdev); |
d39c3b89 JG |
483 | /* 1M ring buffer */ |
484 | r = r100_cp_init(rdev, 1024 * 1024); | |
485 | if (r) { | |
486 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
487 | return r; | |
488 | } | |
489 | r = r100_wb_init(rdev); | |
490 | if (r) | |
491 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
492 | r = r100_ib_init(rdev); | |
493 | if (r) { | |
494 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
495 | return r; | |
496 | } | |
497 | return 0; | |
498 | } | |
499 | ||
500 | int rv515_resume(struct radeon_device *rdev) | |
501 | { | |
502 | /* Make sur GART are not working */ | |
503 | if (rdev->flags & RADEON_IS_PCIE) | |
504 | rv370_pcie_gart_disable(rdev); | |
505 | /* Resume clock before doing reset */ | |
506 | rv515_clock_startup(rdev); | |
507 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
508 | if (radeon_gpu_reset(rdev)) { | |
509 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
510 | RREG32(R_000E40_RBBM_STATUS), | |
511 | RREG32(R_0007C0_CP_STAT)); | |
512 | } | |
513 | /* post */ | |
514 | atom_asic_init(rdev->mode_info.atom_context); | |
515 | /* Resume clock after posting */ | |
516 | rv515_clock_startup(rdev); | |
517 | return rv515_startup(rdev); | |
518 | } | |
519 | ||
520 | int rv515_suspend(struct radeon_device *rdev) | |
521 | { | |
522 | r100_cp_disable(rdev); | |
523 | r100_wb_disable(rdev); | |
ac447df4 | 524 | rs600_irq_disable(rdev); |
d39c3b89 JG |
525 | if (rdev->flags & RADEON_IS_PCIE) |
526 | rv370_pcie_gart_disable(rdev); | |
527 | return 0; | |
528 | } | |
529 | ||
530 | void rv515_set_safe_registers(struct radeon_device *rdev) | |
068a117c | 531 | { |
50f15303 DA |
532 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
533 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); | |
d39c3b89 JG |
534 | } |
535 | ||
536 | void rv515_fini(struct radeon_device *rdev) | |
537 | { | |
538 | rv515_suspend(rdev); | |
539 | r100_cp_fini(rdev); | |
540 | r100_wb_fini(rdev); | |
541 | r100_ib_fini(rdev); | |
542 | radeon_gem_fini(rdev); | |
543 | rv370_pcie_gart_fini(rdev); | |
544 | radeon_agp_fini(rdev); | |
545 | radeon_irq_kms_fini(rdev); | |
546 | radeon_fence_driver_fini(rdev); | |
547 | radeon_object_fini(rdev); | |
548 | radeon_atombios_fini(rdev); | |
549 | kfree(rdev->bios); | |
550 | rdev->bios = NULL; | |
551 | } | |
552 | ||
553 | int rv515_init(struct radeon_device *rdev) | |
554 | { | |
555 | int r; | |
556 | ||
d39c3b89 JG |
557 | /* Initialize scratch registers */ |
558 | radeon_scratch_init(rdev); | |
559 | /* Initialize surface registers */ | |
560 | radeon_surface_init(rdev); | |
561 | /* TODO: disable VGA need to use VGA request */ | |
562 | /* BIOS*/ | |
563 | if (!radeon_get_bios(rdev)) { | |
564 | if (ASIC_IS_AVIVO(rdev)) | |
565 | return -EINVAL; | |
566 | } | |
567 | if (rdev->is_atom_bios) { | |
568 | r = radeon_atombios_init(rdev); | |
569 | if (r) | |
570 | return r; | |
571 | } else { | |
572 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | |
573 | return -EINVAL; | |
574 | } | |
575 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
576 | if (radeon_gpu_reset(rdev)) { | |
577 | dev_warn(rdev->dev, | |
578 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
579 | RREG32(R_000E40_RBBM_STATUS), | |
580 | RREG32(R_0007C0_CP_STAT)); | |
581 | } | |
582 | /* check if cards are posted or not */ | |
583 | if (!radeon_card_posted(rdev) && rdev->bios) { | |
584 | DRM_INFO("GPU not posted. posting now...\n"); | |
585 | atom_asic_init(rdev->mode_info.atom_context); | |
586 | } | |
587 | /* Initialize clocks */ | |
588 | radeon_get_clock_info(rdev->ddev); | |
7433874e RM |
589 | /* Initialize power management */ |
590 | radeon_pm_init(rdev); | |
d39c3b89 JG |
591 | /* Get vram informations */ |
592 | rv515_vram_info(rdev); | |
593 | /* Initialize memory controller (also test AGP) */ | |
594 | r = r420_mc_init(rdev); | |
595 | if (r) | |
596 | return r; | |
597 | rv515_debugfs(rdev); | |
598 | /* Fence driver */ | |
599 | r = radeon_fence_driver_init(rdev); | |
600 | if (r) | |
601 | return r; | |
602 | r = radeon_irq_kms_init(rdev); | |
603 | if (r) | |
604 | return r; | |
605 | /* Memory manager */ | |
606 | r = radeon_object_init(rdev); | |
607 | if (r) | |
608 | return r; | |
609 | r = rv370_pcie_gart_init(rdev); | |
610 | if (r) | |
611 | return r; | |
612 | rv515_set_safe_registers(rdev); | |
613 | rdev->accel_working = true; | |
614 | r = rv515_startup(rdev); | |
615 | if (r) { | |
616 | /* Somethings want wront with the accel init stop accel */ | |
617 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
618 | rv515_suspend(rdev); | |
619 | r100_cp_fini(rdev); | |
620 | r100_wb_fini(rdev); | |
621 | r100_ib_fini(rdev); | |
622 | rv370_pcie_gart_fini(rdev); | |
623 | radeon_agp_fini(rdev); | |
624 | radeon_irq_kms_fini(rdev); | |
625 | rdev->accel_working = false; | |
626 | } | |
068a117c JG |
627 | return 0; |
628 | } | |
c93bb85b | 629 | |
4ce001ab | 630 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
c93bb85b | 631 | { |
4ce001ab DA |
632 | int index_reg = 0x6578 + crtc->crtc_offset; |
633 | int data_reg = 0x657c + crtc->crtc_offset; | |
634 | ||
635 | WREG32(0x659C + crtc->crtc_offset, 0x0); | |
636 | WREG32(0x6594 + crtc->crtc_offset, 0x705); | |
637 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); | |
638 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); | |
639 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); | |
640 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); | |
641 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); | |
642 | WREG32(index_reg, 0x0); | |
643 | WREG32(data_reg, 0x841880A8); | |
644 | WREG32(index_reg, 0x1); | |
645 | WREG32(data_reg, 0x84208680); | |
646 | WREG32(index_reg, 0x2); | |
647 | WREG32(data_reg, 0xBFF880B0); | |
648 | WREG32(index_reg, 0x100); | |
649 | WREG32(data_reg, 0x83D88088); | |
650 | WREG32(index_reg, 0x101); | |
651 | WREG32(data_reg, 0x84608680); | |
652 | WREG32(index_reg, 0x102); | |
653 | WREG32(data_reg, 0xBFF080D0); | |
654 | WREG32(index_reg, 0x200); | |
655 | WREG32(data_reg, 0x83988068); | |
656 | WREG32(index_reg, 0x201); | |
657 | WREG32(data_reg, 0x84A08680); | |
658 | WREG32(index_reg, 0x202); | |
659 | WREG32(data_reg, 0xBFF080F8); | |
660 | WREG32(index_reg, 0x300); | |
661 | WREG32(data_reg, 0x83588058); | |
662 | WREG32(index_reg, 0x301); | |
663 | WREG32(data_reg, 0x84E08660); | |
664 | WREG32(index_reg, 0x302); | |
665 | WREG32(data_reg, 0xBFF88120); | |
666 | WREG32(index_reg, 0x400); | |
667 | WREG32(data_reg, 0x83188040); | |
668 | WREG32(index_reg, 0x401); | |
669 | WREG32(data_reg, 0x85008660); | |
670 | WREG32(index_reg, 0x402); | |
671 | WREG32(data_reg, 0xBFF88150); | |
672 | WREG32(index_reg, 0x500); | |
673 | WREG32(data_reg, 0x82D88030); | |
674 | WREG32(index_reg, 0x501); | |
675 | WREG32(data_reg, 0x85408640); | |
676 | WREG32(index_reg, 0x502); | |
677 | WREG32(data_reg, 0xBFF88180); | |
678 | WREG32(index_reg, 0x600); | |
679 | WREG32(data_reg, 0x82A08018); | |
680 | WREG32(index_reg, 0x601); | |
681 | WREG32(data_reg, 0x85808620); | |
682 | WREG32(index_reg, 0x602); | |
683 | WREG32(data_reg, 0xBFF081B8); | |
684 | WREG32(index_reg, 0x700); | |
685 | WREG32(data_reg, 0x82608010); | |
686 | WREG32(index_reg, 0x701); | |
687 | WREG32(data_reg, 0x85A08600); | |
688 | WREG32(index_reg, 0x702); | |
689 | WREG32(data_reg, 0x800081F0); | |
690 | WREG32(index_reg, 0x800); | |
691 | WREG32(data_reg, 0x8228BFF8); | |
692 | WREG32(index_reg, 0x801); | |
693 | WREG32(data_reg, 0x85E085E0); | |
694 | WREG32(index_reg, 0x802); | |
695 | WREG32(data_reg, 0xBFF88228); | |
696 | WREG32(index_reg, 0x10000); | |
697 | WREG32(data_reg, 0x82A8BF00); | |
698 | WREG32(index_reg, 0x10001); | |
699 | WREG32(data_reg, 0x82A08CC0); | |
700 | WREG32(index_reg, 0x10002); | |
701 | WREG32(data_reg, 0x8008BEF8); | |
702 | WREG32(index_reg, 0x10100); | |
703 | WREG32(data_reg, 0x81F0BF28); | |
704 | WREG32(index_reg, 0x10101); | |
705 | WREG32(data_reg, 0x83608CA0); | |
706 | WREG32(index_reg, 0x10102); | |
707 | WREG32(data_reg, 0x8018BED0); | |
708 | WREG32(index_reg, 0x10200); | |
709 | WREG32(data_reg, 0x8148BF38); | |
710 | WREG32(index_reg, 0x10201); | |
711 | WREG32(data_reg, 0x84408C80); | |
712 | WREG32(index_reg, 0x10202); | |
713 | WREG32(data_reg, 0x8008BEB8); | |
714 | WREG32(index_reg, 0x10300); | |
715 | WREG32(data_reg, 0x80B0BF78); | |
716 | WREG32(index_reg, 0x10301); | |
717 | WREG32(data_reg, 0x85008C20); | |
718 | WREG32(index_reg, 0x10302); | |
719 | WREG32(data_reg, 0x8020BEA0); | |
720 | WREG32(index_reg, 0x10400); | |
721 | WREG32(data_reg, 0x8028BF90); | |
722 | WREG32(index_reg, 0x10401); | |
723 | WREG32(data_reg, 0x85E08BC0); | |
724 | WREG32(index_reg, 0x10402); | |
725 | WREG32(data_reg, 0x8018BE90); | |
726 | WREG32(index_reg, 0x10500); | |
727 | WREG32(data_reg, 0xBFB8BFB0); | |
728 | WREG32(index_reg, 0x10501); | |
729 | WREG32(data_reg, 0x86C08B40); | |
730 | WREG32(index_reg, 0x10502); | |
731 | WREG32(data_reg, 0x8010BE90); | |
732 | WREG32(index_reg, 0x10600); | |
733 | WREG32(data_reg, 0xBF58BFC8); | |
734 | WREG32(index_reg, 0x10601); | |
735 | WREG32(data_reg, 0x87A08AA0); | |
736 | WREG32(index_reg, 0x10602); | |
737 | WREG32(data_reg, 0x8010BE98); | |
738 | WREG32(index_reg, 0x10700); | |
739 | WREG32(data_reg, 0xBF10BFF0); | |
740 | WREG32(index_reg, 0x10701); | |
741 | WREG32(data_reg, 0x886089E0); | |
742 | WREG32(index_reg, 0x10702); | |
743 | WREG32(data_reg, 0x8018BEB0); | |
744 | WREG32(index_reg, 0x10800); | |
745 | WREG32(data_reg, 0xBED8BFE8); | |
746 | WREG32(index_reg, 0x10801); | |
747 | WREG32(data_reg, 0x89408940); | |
748 | WREG32(index_reg, 0x10802); | |
749 | WREG32(data_reg, 0xBFE8BED8); | |
750 | WREG32(index_reg, 0x20000); | |
751 | WREG32(data_reg, 0x80008000); | |
752 | WREG32(index_reg, 0x20001); | |
753 | WREG32(data_reg, 0x90008000); | |
754 | WREG32(index_reg, 0x20002); | |
755 | WREG32(data_reg, 0x80008000); | |
756 | WREG32(index_reg, 0x20003); | |
757 | WREG32(data_reg, 0x80008000); | |
758 | WREG32(index_reg, 0x20100); | |
759 | WREG32(data_reg, 0x80108000); | |
760 | WREG32(index_reg, 0x20101); | |
761 | WREG32(data_reg, 0x8FE0BF70); | |
762 | WREG32(index_reg, 0x20102); | |
763 | WREG32(data_reg, 0xBFE880C0); | |
764 | WREG32(index_reg, 0x20103); | |
765 | WREG32(data_reg, 0x80008000); | |
766 | WREG32(index_reg, 0x20200); | |
767 | WREG32(data_reg, 0x8018BFF8); | |
768 | WREG32(index_reg, 0x20201); | |
769 | WREG32(data_reg, 0x8F80BF08); | |
770 | WREG32(index_reg, 0x20202); | |
771 | WREG32(data_reg, 0xBFD081A0); | |
772 | WREG32(index_reg, 0x20203); | |
773 | WREG32(data_reg, 0xBFF88000); | |
774 | WREG32(index_reg, 0x20300); | |
775 | WREG32(data_reg, 0x80188000); | |
776 | WREG32(index_reg, 0x20301); | |
777 | WREG32(data_reg, 0x8EE0BEC0); | |
778 | WREG32(index_reg, 0x20302); | |
779 | WREG32(data_reg, 0xBFB082A0); | |
780 | WREG32(index_reg, 0x20303); | |
781 | WREG32(data_reg, 0x80008000); | |
782 | WREG32(index_reg, 0x20400); | |
783 | WREG32(data_reg, 0x80188000); | |
784 | WREG32(index_reg, 0x20401); | |
785 | WREG32(data_reg, 0x8E00BEA0); | |
786 | WREG32(index_reg, 0x20402); | |
787 | WREG32(data_reg, 0xBF8883C0); | |
788 | WREG32(index_reg, 0x20403); | |
789 | WREG32(data_reg, 0x80008000); | |
790 | WREG32(index_reg, 0x20500); | |
791 | WREG32(data_reg, 0x80188000); | |
792 | WREG32(index_reg, 0x20501); | |
793 | WREG32(data_reg, 0x8D00BE90); | |
794 | WREG32(index_reg, 0x20502); | |
795 | WREG32(data_reg, 0xBF588500); | |
796 | WREG32(index_reg, 0x20503); | |
797 | WREG32(data_reg, 0x80008008); | |
798 | WREG32(index_reg, 0x20600); | |
799 | WREG32(data_reg, 0x80188000); | |
800 | WREG32(index_reg, 0x20601); | |
801 | WREG32(data_reg, 0x8BC0BE98); | |
802 | WREG32(index_reg, 0x20602); | |
803 | WREG32(data_reg, 0xBF308660); | |
804 | WREG32(index_reg, 0x20603); | |
805 | WREG32(data_reg, 0x80008008); | |
806 | WREG32(index_reg, 0x20700); | |
807 | WREG32(data_reg, 0x80108000); | |
808 | WREG32(index_reg, 0x20701); | |
809 | WREG32(data_reg, 0x8A80BEB0); | |
810 | WREG32(index_reg, 0x20702); | |
811 | WREG32(data_reg, 0xBF0087C0); | |
812 | WREG32(index_reg, 0x20703); | |
813 | WREG32(data_reg, 0x80008008); | |
814 | WREG32(index_reg, 0x20800); | |
815 | WREG32(data_reg, 0x80108000); | |
816 | WREG32(index_reg, 0x20801); | |
817 | WREG32(data_reg, 0x8920BED0); | |
818 | WREG32(index_reg, 0x20802); | |
819 | WREG32(data_reg, 0xBED08920); | |
820 | WREG32(index_reg, 0x20803); | |
821 | WREG32(data_reg, 0x80008010); | |
822 | WREG32(index_reg, 0x30000); | |
823 | WREG32(data_reg, 0x90008000); | |
824 | WREG32(index_reg, 0x30001); | |
825 | WREG32(data_reg, 0x80008000); | |
826 | WREG32(index_reg, 0x30100); | |
827 | WREG32(data_reg, 0x8FE0BF90); | |
828 | WREG32(index_reg, 0x30101); | |
829 | WREG32(data_reg, 0xBFF880A0); | |
830 | WREG32(index_reg, 0x30200); | |
831 | WREG32(data_reg, 0x8F60BF40); | |
832 | WREG32(index_reg, 0x30201); | |
833 | WREG32(data_reg, 0xBFE88180); | |
834 | WREG32(index_reg, 0x30300); | |
835 | WREG32(data_reg, 0x8EC0BF00); | |
836 | WREG32(index_reg, 0x30301); | |
837 | WREG32(data_reg, 0xBFC88280); | |
838 | WREG32(index_reg, 0x30400); | |
839 | WREG32(data_reg, 0x8DE0BEE0); | |
840 | WREG32(index_reg, 0x30401); | |
841 | WREG32(data_reg, 0xBFA083A0); | |
842 | WREG32(index_reg, 0x30500); | |
843 | WREG32(data_reg, 0x8CE0BED0); | |
844 | WREG32(index_reg, 0x30501); | |
845 | WREG32(data_reg, 0xBF7884E0); | |
846 | WREG32(index_reg, 0x30600); | |
847 | WREG32(data_reg, 0x8BA0BED8); | |
848 | WREG32(index_reg, 0x30601); | |
849 | WREG32(data_reg, 0xBF508640); | |
850 | WREG32(index_reg, 0x30700); | |
851 | WREG32(data_reg, 0x8A60BEE8); | |
852 | WREG32(index_reg, 0x30701); | |
853 | WREG32(data_reg, 0xBF2087A0); | |
854 | WREG32(index_reg, 0x30800); | |
855 | WREG32(data_reg, 0x8900BF00); | |
856 | WREG32(index_reg, 0x30801); | |
857 | WREG32(data_reg, 0xBF008900); | |
c93bb85b JG |
858 | } |
859 | ||
860 | struct rv515_watermark { | |
861 | u32 lb_request_fifo_depth; | |
862 | fixed20_12 num_line_pair; | |
863 | fixed20_12 estimated_width; | |
864 | fixed20_12 worst_case_latency; | |
865 | fixed20_12 consumption_rate; | |
866 | fixed20_12 active_time; | |
867 | fixed20_12 dbpp; | |
868 | fixed20_12 priority_mark_max; | |
869 | fixed20_12 priority_mark; | |
870 | fixed20_12 sclk; | |
871 | }; | |
872 | ||
873 | void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, | |
874 | struct radeon_crtc *crtc, | |
875 | struct rv515_watermark *wm) | |
876 | { | |
877 | struct drm_display_mode *mode = &crtc->base.mode; | |
878 | fixed20_12 a, b, c; | |
879 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; | |
880 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; | |
881 | ||
882 | if (!crtc->base.enabled) { | |
883 | /* FIXME: wouldn't it better to set priority mark to maximum */ | |
884 | wm->lb_request_fifo_depth = 4; | |
885 | return; | |
886 | } | |
887 | ||
888 | if (crtc->vsc.full > rfixed_const(2)) | |
889 | wm->num_line_pair.full = rfixed_const(2); | |
890 | else | |
891 | wm->num_line_pair.full = rfixed_const(1); | |
892 | ||
893 | b.full = rfixed_const(mode->crtc_hdisplay); | |
894 | c.full = rfixed_const(256); | |
895 | a.full = rfixed_mul(wm->num_line_pair, b); | |
896 | request_fifo_depth.full = rfixed_div(a, c); | |
897 | if (a.full < rfixed_const(4)) { | |
898 | wm->lb_request_fifo_depth = 4; | |
899 | } else { | |
900 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); | |
901 | } | |
902 | ||
903 | /* Determine consumption rate | |
904 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) | |
905 | * vtaps = number of vertical taps, | |
906 | * vsc = vertical scaling ratio, defined as source/destination | |
907 | * hsc = horizontal scaling ration, defined as source/destination | |
908 | */ | |
909 | a.full = rfixed_const(mode->clock); | |
910 | b.full = rfixed_const(1000); | |
911 | a.full = rfixed_div(a, b); | |
912 | pclk.full = rfixed_div(b, a); | |
913 | if (crtc->rmx_type != RMX_OFF) { | |
914 | b.full = rfixed_const(2); | |
915 | if (crtc->vsc.full > b.full) | |
916 | b.full = crtc->vsc.full; | |
917 | b.full = rfixed_mul(b, crtc->hsc); | |
918 | c.full = rfixed_const(2); | |
919 | b.full = rfixed_div(b, c); | |
920 | consumption_time.full = rfixed_div(pclk, b); | |
921 | } else { | |
922 | consumption_time.full = pclk.full; | |
923 | } | |
924 | a.full = rfixed_const(1); | |
925 | wm->consumption_rate.full = rfixed_div(a, consumption_time); | |
926 | ||
927 | ||
928 | /* Determine line time | |
929 | * LineTime = total time for one line of displayhtotal | |
930 | * LineTime = total number of horizontal pixels | |
931 | * pclk = pixel clock period(ns) | |
932 | */ | |
933 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
934 | line_time.full = rfixed_mul(a, pclk); | |
935 | ||
936 | /* Determine active time | |
937 | * ActiveTime = time of active region of display within one line, | |
938 | * hactive = total number of horizontal active pixels | |
939 | * htotal = total number of horizontal pixels | |
940 | */ | |
941 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); | |
942 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
943 | wm->active_time.full = rfixed_mul(line_time, b); | |
944 | wm->active_time.full = rfixed_div(wm->active_time, a); | |
945 | ||
946 | /* Determine chunk time | |
947 | * ChunkTime = the time it takes the DCP to send one chunk of data | |
948 | * to the LB which consists of pipeline delay and inter chunk gap | |
949 | * sclk = system clock(Mhz) | |
950 | */ | |
951 | a.full = rfixed_const(600 * 1000); | |
952 | chunk_time.full = rfixed_div(a, rdev->pm.sclk); | |
953 | read_delay_latency.full = rfixed_const(1000); | |
954 | ||
955 | /* Determine the worst case latency | |
956 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) | |
957 | * WorstCaseLatency = worst case time from urgent to when the MC starts | |
958 | * to return data | |
959 | * READ_DELAY_IDLE_MAX = constant of 1us | |
960 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB | |
961 | * which consists of pipeline delay and inter chunk gap | |
962 | */ | |
963 | if (rfixed_trunc(wm->num_line_pair) > 1) { | |
964 | a.full = rfixed_const(3); | |
965 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); | |
966 | wm->worst_case_latency.full += read_delay_latency.full; | |
967 | } else { | |
968 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; | |
969 | } | |
970 | ||
971 | /* Determine the tolerable latency | |
972 | * TolerableLatency = Any given request has only 1 line time | |
973 | * for the data to be returned | |
974 | * LBRequestFifoDepth = Number of chunk requests the LB can | |
975 | * put into the request FIFO for a display | |
976 | * LineTime = total time for one line of display | |
977 | * ChunkTime = the time it takes the DCP to send one chunk | |
978 | * of data to the LB which consists of | |
979 | * pipeline delay and inter chunk gap | |
980 | */ | |
981 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { | |
982 | tolerable_latency.full = line_time.full; | |
983 | } else { | |
984 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); | |
985 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; | |
986 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); | |
987 | tolerable_latency.full = line_time.full - tolerable_latency.full; | |
988 | } | |
989 | /* We assume worst case 32bits (4 bytes) */ | |
990 | wm->dbpp.full = rfixed_const(2 * 16); | |
991 | ||
992 | /* Determine the maximum priority mark | |
993 | * width = viewport width in pixels | |
994 | */ | |
995 | a.full = rfixed_const(16); | |
996 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); | |
997 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); | |
998 | ||
999 | /* Determine estimated width */ | |
1000 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; | |
1001 | estimated_width.full = rfixed_div(estimated_width, consumption_time); | |
1002 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
1003 | wm->priority_mark.full = rfixed_const(10); | |
1004 | } else { | |
1005 | a.full = rfixed_const(16); | |
1006 | wm->priority_mark.full = rfixed_div(estimated_width, a); | |
1007 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |
1012 | { | |
1013 | struct drm_display_mode *mode0 = NULL; | |
1014 | struct drm_display_mode *mode1 = NULL; | |
1015 | struct rv515_watermark wm0; | |
1016 | struct rv515_watermark wm1; | |
1017 | u32 tmp; | |
1018 | fixed20_12 priority_mark02, priority_mark12, fill_rate; | |
1019 | fixed20_12 a, b; | |
1020 | ||
1021 | if (rdev->mode_info.crtcs[0]->base.enabled) | |
1022 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
1023 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
1024 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
1025 | rs690_line_buffer_adjust(rdev, mode0, mode1); | |
1026 | ||
1027 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); | |
1028 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); | |
1029 | ||
1030 | tmp = wm0.lb_request_fifo_depth; | |
1031 | tmp |= wm1.lb_request_fifo_depth << 16; | |
1032 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); | |
1033 | ||
1034 | if (mode0 && mode1) { | |
1035 | if (rfixed_trunc(wm0.dbpp) > 64) | |
1036 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | |
1037 | else | |
1038 | a.full = wm0.num_line_pair.full; | |
1039 | if (rfixed_trunc(wm1.dbpp) > 64) | |
1040 | b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | |
1041 | else | |
1042 | b.full = wm1.num_line_pair.full; | |
1043 | a.full += b.full; | |
1044 | fill_rate.full = rfixed_div(wm0.sclk, a); | |
1045 | if (wm0.consumption_rate.full > fill_rate.full) { | |
1046 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
1047 | b.full = rfixed_mul(b, wm0.active_time); | |
1048 | a.full = rfixed_const(16); | |
1049 | b.full = rfixed_div(b, a); | |
1050 | a.full = rfixed_mul(wm0.worst_case_latency, | |
1051 | wm0.consumption_rate); | |
1052 | priority_mark02.full = a.full + b.full; | |
1053 | } else { | |
1054 | a.full = rfixed_mul(wm0.worst_case_latency, | |
1055 | wm0.consumption_rate); | |
1056 | b.full = rfixed_const(16 * 1000); | |
1057 | priority_mark02.full = rfixed_div(a, b); | |
1058 | } | |
1059 | if (wm1.consumption_rate.full > fill_rate.full) { | |
1060 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
1061 | b.full = rfixed_mul(b, wm1.active_time); | |
1062 | a.full = rfixed_const(16); | |
1063 | b.full = rfixed_div(b, a); | |
1064 | a.full = rfixed_mul(wm1.worst_case_latency, | |
1065 | wm1.consumption_rate); | |
1066 | priority_mark12.full = a.full + b.full; | |
1067 | } else { | |
1068 | a.full = rfixed_mul(wm1.worst_case_latency, | |
1069 | wm1.consumption_rate); | |
1070 | b.full = rfixed_const(16 * 1000); | |
1071 | priority_mark12.full = rfixed_div(a, b); | |
1072 | } | |
1073 | if (wm0.priority_mark.full > priority_mark02.full) | |
1074 | priority_mark02.full = wm0.priority_mark.full; | |
1075 | if (rfixed_trunc(priority_mark02) < 0) | |
1076 | priority_mark02.full = 0; | |
1077 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
1078 | priority_mark02.full = wm0.priority_mark_max.full; | |
1079 | if (wm1.priority_mark.full > priority_mark12.full) | |
1080 | priority_mark12.full = wm1.priority_mark.full; | |
1081 | if (rfixed_trunc(priority_mark12) < 0) | |
1082 | priority_mark12.full = 0; | |
1083 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
1084 | priority_mark12.full = wm1.priority_mark_max.full; | |
1085 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); | |
1086 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); | |
1087 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); | |
1088 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); | |
1089 | } else if (mode0) { | |
1090 | if (rfixed_trunc(wm0.dbpp) > 64) | |
1091 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); | |
1092 | else | |
1093 | a.full = wm0.num_line_pair.full; | |
1094 | fill_rate.full = rfixed_div(wm0.sclk, a); | |
1095 | if (wm0.consumption_rate.full > fill_rate.full) { | |
1096 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
1097 | b.full = rfixed_mul(b, wm0.active_time); | |
1098 | a.full = rfixed_const(16); | |
1099 | b.full = rfixed_div(b, a); | |
1100 | a.full = rfixed_mul(wm0.worst_case_latency, | |
1101 | wm0.consumption_rate); | |
1102 | priority_mark02.full = a.full + b.full; | |
1103 | } else { | |
1104 | a.full = rfixed_mul(wm0.worst_case_latency, | |
1105 | wm0.consumption_rate); | |
1106 | b.full = rfixed_const(16); | |
1107 | priority_mark02.full = rfixed_div(a, b); | |
1108 | } | |
1109 | if (wm0.priority_mark.full > priority_mark02.full) | |
1110 | priority_mark02.full = wm0.priority_mark.full; | |
1111 | if (rfixed_trunc(priority_mark02) < 0) | |
1112 | priority_mark02.full = 0; | |
1113 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
1114 | priority_mark02.full = wm0.priority_mark_max.full; | |
1115 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); | |
1116 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); | |
1117 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | |
1118 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | |
1119 | } else { | |
1120 | if (rfixed_trunc(wm1.dbpp) > 64) | |
1121 | a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); | |
1122 | else | |
1123 | a.full = wm1.num_line_pair.full; | |
1124 | fill_rate.full = rfixed_div(wm1.sclk, a); | |
1125 | if (wm1.consumption_rate.full > fill_rate.full) { | |
1126 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
1127 | b.full = rfixed_mul(b, wm1.active_time); | |
1128 | a.full = rfixed_const(16); | |
1129 | b.full = rfixed_div(b, a); | |
1130 | a.full = rfixed_mul(wm1.worst_case_latency, | |
1131 | wm1.consumption_rate); | |
1132 | priority_mark12.full = a.full + b.full; | |
1133 | } else { | |
1134 | a.full = rfixed_mul(wm1.worst_case_latency, | |
1135 | wm1.consumption_rate); | |
1136 | b.full = rfixed_const(16 * 1000); | |
1137 | priority_mark12.full = rfixed_div(a, b); | |
1138 | } | |
1139 | if (wm1.priority_mark.full > priority_mark12.full) | |
1140 | priority_mark12.full = wm1.priority_mark.full; | |
1141 | if (rfixed_trunc(priority_mark12) < 0) | |
1142 | priority_mark12.full = 0; | |
1143 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
1144 | priority_mark12.full = wm1.priority_mark_max.full; | |
1145 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | |
1146 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | |
1147 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); | |
1148 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | void rv515_bandwidth_update(struct radeon_device *rdev) | |
1153 | { | |
1154 | uint32_t tmp; | |
1155 | struct drm_display_mode *mode0 = NULL; | |
1156 | struct drm_display_mode *mode1 = NULL; | |
1157 | ||
1158 | if (rdev->mode_info.crtcs[0]->base.enabled) | |
1159 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
1160 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
1161 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
1162 | /* | |
1163 | * Set display0/1 priority up in the memory controller for | |
1164 | * modes if the user specifies HIGH for displaypriority | |
1165 | * option. | |
1166 | */ | |
1167 | if (rdev->disp_priority == 2) { | |
1168 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); | |
1169 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; | |
1170 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; | |
1171 | if (mode1) | |
1172 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); | |
1173 | if (mode0) | |
1174 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); | |
1175 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); | |
1176 | } | |
1177 | rv515_bandwidth_avivo_update(rdev); | |
1178 | } |