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1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #ifndef SMU7_H | |
25 | #define SMU7_H | |
26 | ||
27 | #pragma pack(push, 1) | |
28 | ||
29 | #define SMU7_CONTEXT_ID_SMC 1 | |
30 | #define SMU7_CONTEXT_ID_VBIOS 2 | |
31 | ||
32 | ||
33 | #define SMU7_CONTEXT_ID_SMC 1 | |
34 | #define SMU7_CONTEXT_ID_VBIOS 2 | |
35 | ||
36 | #define SMU7_MAX_LEVELS_VDDC 8 | |
37 | #define SMU7_MAX_LEVELS_VDDCI 4 | |
38 | #define SMU7_MAX_LEVELS_MVDD 4 | |
39 | #define SMU7_MAX_LEVELS_VDDNB 8 | |
40 | ||
41 | #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV | |
42 | #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM | |
43 | #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels | |
44 | #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. | |
45 | #define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. | |
46 | #define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. | |
47 | #define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. | |
48 | #define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. | |
49 | #define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. | |
50 | ||
51 | #define DPM_NO_LIMIT 0 | |
52 | #define DPM_NO_UP 1 | |
53 | #define DPM_GO_DOWN 2 | |
54 | #define DPM_GO_UP 3 | |
55 | ||
56 | #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 | |
57 | #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 | |
58 | ||
59 | #define GPIO_CLAMP_MODE_VRHOT 1 | |
60 | #define GPIO_CLAMP_MODE_THERM 2 | |
61 | #define GPIO_CLAMP_MODE_DC 4 | |
62 | ||
63 | #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 | |
64 | #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) | |
65 | #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 | |
66 | #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) | |
67 | #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 | |
68 | #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) | |
69 | #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 | |
70 | #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) | |
71 | #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 | |
72 | #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) | |
73 | #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 | |
74 | #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) | |
75 | #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 | |
76 | #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) | |
77 | #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 | |
78 | #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) | |
79 | #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 | |
80 | #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) | |
81 | #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 | |
82 | #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) | |
83 | ||
84 | ||
85 | struct SMU7_PIDController | |
86 | { | |
87 | uint32_t Ki; | |
88 | int32_t LFWindupUL; | |
89 | int32_t LFWindupLL; | |
90 | uint32_t StatePrecision; | |
91 | uint32_t LfPrecision; | |
92 | uint32_t LfOffset; | |
93 | uint32_t MaxState; | |
94 | uint32_t MaxLfFraction; | |
95 | uint32_t StateShift; | |
96 | }; | |
97 | ||
98 | typedef struct SMU7_PIDController SMU7_PIDController; | |
99 | ||
100 | // ------------------------------------------------------------------------------------------------------------------------- | |
101 | #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ | |
102 | ||
103 | #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 | |
104 | #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 | |
105 | #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 | |
106 | #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 | |
107 | #define SMU7_UVD_DPM_CONFIG_MASK 0x10 | |
108 | #define SMU7_VCE_DPM_CONFIG_MASK 0x20 | |
109 | #define SMU7_ACP_DPM_CONFIG_MASK 0x40 | |
110 | #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 | |
111 | #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 | |
112 | ||
113 | #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 | |
114 | #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 | |
115 | #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 | |
116 | #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 | |
117 | #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 | |
118 | #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 | |
119 | ||
120 | struct SMU7_Firmware_Header | |
121 | { | |
122 | uint32_t Digest[5]; | |
123 | uint32_t Version; | |
124 | uint32_t HeaderSize; | |
125 | uint32_t Flags; | |
126 | uint32_t EntryPoint; | |
127 | uint32_t CodeSize; | |
128 | uint32_t ImageSize; | |
129 | ||
130 | uint32_t Rtos; | |
131 | uint32_t SoftRegisters; | |
132 | uint32_t DpmTable; | |
133 | uint32_t FanTable; | |
134 | uint32_t CacConfigTable; | |
135 | uint32_t CacStatusTable; | |
136 | ||
137 | uint32_t mcRegisterTable; | |
138 | ||
139 | uint32_t mcArbDramTimingTable; | |
140 | ||
141 | uint32_t PmFuseTable; | |
142 | uint32_t Globals; | |
143 | uint32_t Reserved[42]; | |
144 | uint32_t Signature; | |
145 | }; | |
146 | ||
147 | typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; | |
148 | ||
149 | #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 | |
150 | ||
151 | enum DisplayConfig { | |
152 | PowerDown = 1, | |
153 | DP54x4, | |
154 | DP54x2, | |
155 | DP54x1, | |
156 | DP27x4, | |
157 | DP27x2, | |
158 | DP27x1, | |
159 | HDMI297, | |
160 | HDMI162, | |
161 | LVDS, | |
162 | DP324x4, | |
163 | DP324x2, | |
164 | DP324x1 | |
165 | }; | |
166 | ||
167 | #pragma pack(pop) | |
168 | ||
169 | #endif | |
170 |