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80ea2c12 AD |
1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include "drmP.h" | |
25 | #include "radeon.h" | |
26 | #include "sumod.h" | |
27 | #include "r600_dpm.h" | |
28 | #include "cypress_dpm.h" | |
29 | #include "sumo_dpm.h" | |
80ea2c12 AD |
30 | |
31 | #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5 | |
32 | #define SUMO_MINIMUM_ENGINE_CLOCK 800 | |
33 | #define BOOST_DPM_LEVEL 7 | |
34 | ||
35 | static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = | |
36 | { | |
37 | SUMO_UTC_DFLT_00, | |
38 | SUMO_UTC_DFLT_01, | |
39 | SUMO_UTC_DFLT_02, | |
40 | SUMO_UTC_DFLT_03, | |
41 | SUMO_UTC_DFLT_04, | |
42 | SUMO_UTC_DFLT_05, | |
43 | SUMO_UTC_DFLT_06, | |
44 | SUMO_UTC_DFLT_07, | |
45 | SUMO_UTC_DFLT_08, | |
46 | SUMO_UTC_DFLT_09, | |
47 | SUMO_UTC_DFLT_10, | |
48 | SUMO_UTC_DFLT_11, | |
49 | SUMO_UTC_DFLT_12, | |
50 | SUMO_UTC_DFLT_13, | |
51 | SUMO_UTC_DFLT_14, | |
52 | }; | |
53 | ||
54 | static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = | |
55 | { | |
56 | SUMO_DTC_DFLT_00, | |
57 | SUMO_DTC_DFLT_01, | |
58 | SUMO_DTC_DFLT_02, | |
59 | SUMO_DTC_DFLT_03, | |
60 | SUMO_DTC_DFLT_04, | |
61 | SUMO_DTC_DFLT_05, | |
62 | SUMO_DTC_DFLT_06, | |
63 | SUMO_DTC_DFLT_07, | |
64 | SUMO_DTC_DFLT_08, | |
65 | SUMO_DTC_DFLT_09, | |
66 | SUMO_DTC_DFLT_10, | |
67 | SUMO_DTC_DFLT_11, | |
68 | SUMO_DTC_DFLT_12, | |
69 | SUMO_DTC_DFLT_13, | |
70 | SUMO_DTC_DFLT_14, | |
71 | }; | |
72 | ||
73 | struct sumo_ps *sumo_get_ps(struct radeon_ps *rps) | |
74 | { | |
75 | struct sumo_ps *ps = rps->ps_priv; | |
76 | ||
77 | return ps; | |
78 | } | |
79 | ||
80 | struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev) | |
81 | { | |
82 | struct sumo_power_info *pi = rdev->pm.dpm.priv; | |
83 | ||
84 | return pi; | |
85 | } | |
86 | ||
87 | u32 sumo_get_xclk(struct radeon_device *rdev) | |
88 | { | |
89 | return rdev->clock.spll.reference_freq; | |
90 | } | |
91 | ||
92 | static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) | |
93 | { | |
94 | if (enable) | |
95 | WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); | |
96 | else { | |
97 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); | |
98 | WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); | |
99 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); | |
100 | RREG32(GB_ADDR_CONFIG); | |
101 | } | |
102 | } | |
103 | ||
104 | #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF | |
105 | #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF | |
106 | ||
107 | static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable) | |
108 | { | |
109 | u32 local0; | |
110 | u32 local1; | |
111 | ||
112 | local0 = RREG32(CG_CGTT_LOCAL_0); | |
113 | local1 = RREG32(CG_CGTT_LOCAL_1); | |
114 | ||
115 | if (enable) { | |
116 | WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); | |
117 | WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); | |
118 | } else { | |
119 | WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); | |
120 | WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); | |
121 | } | |
122 | } | |
123 | ||
124 | static void sumo_program_git(struct radeon_device *rdev) | |
125 | { | |
126 | u32 p, u; | |
127 | u32 xclk = sumo_get_xclk(rdev); | |
128 | ||
129 | r600_calculate_u_and_p(SUMO_GICST_DFLT, | |
130 | xclk, 16, &p, &u); | |
131 | ||
132 | WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); | |
133 | } | |
134 | ||
135 | static void sumo_program_grsd(struct radeon_device *rdev) | |
136 | { | |
137 | u32 p, u; | |
138 | u32 xclk = sumo_get_xclk(rdev); | |
139 | u32 grs = 256 * 25 / 100; | |
140 | ||
141 | r600_calculate_u_and_p(1, xclk, 14, &p, &u); | |
142 | ||
143 | WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); | |
144 | } | |
145 | ||
d70229f7 | 146 | void sumo_gfx_clockgating_initialize(struct radeon_device *rdev) |
80ea2c12 AD |
147 | { |
148 | sumo_program_git(rdev); | |
149 | sumo_program_grsd(rdev); | |
150 | } | |
151 | ||
152 | static void sumo_gfx_powergating_initialize(struct radeon_device *rdev) | |
153 | { | |
154 | u32 rcu_pwr_gating_cntl; | |
155 | u32 p, u; | |
156 | u32 p_c, p_p, d_p; | |
157 | u32 r_t, i_t; | |
158 | u32 xclk = sumo_get_xclk(rdev); | |
159 | ||
160 | if (rdev->family == CHIP_PALM) { | |
161 | p_c = 4; | |
162 | d_p = 10; | |
163 | r_t = 10; | |
164 | i_t = 4; | |
165 | p_p = 50 + 1000/200 + 6 * 32; | |
166 | } else { | |
167 | p_c = 16; | |
168 | d_p = 50; | |
169 | r_t = 50; | |
170 | i_t = 50; | |
171 | p_p = 113; | |
172 | } | |
173 | ||
174 | WREG32(CG_SCRATCH2, 0x01B60A17); | |
175 | ||
176 | r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT, | |
177 | xclk, 16, &p, &u); | |
178 | ||
179 | WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), | |
180 | ~(PGP_MASK | PGU_MASK)); | |
181 | ||
182 | r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT, | |
183 | xclk, 16, &p, &u); | |
184 | ||
185 | WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), | |
186 | ~(PGP_MASK | PGU_MASK)); | |
187 | ||
188 | if (rdev->family == CHIP_PALM) { | |
189 | WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210); | |
190 | WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010); | |
191 | } else { | |
192 | WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210); | |
193 | WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98); | |
194 | } | |
195 | ||
196 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); | |
197 | rcu_pwr_gating_cntl &= | |
198 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); | |
199 | rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN; | |
200 | if (rdev->family == CHIP_PALM) { | |
201 | rcu_pwr_gating_cntl &= ~PCP_MASK; | |
202 | rcu_pwr_gating_cntl |= PCP(0x77); | |
203 | } | |
204 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); | |
205 | ||
206 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); | |
207 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); | |
208 | rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50); | |
209 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); | |
210 | ||
211 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); | |
212 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); | |
213 | rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50); | |
214 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); | |
215 | ||
216 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4); | |
217 | rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK); | |
218 | rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t); | |
219 | WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl); | |
220 | ||
221 | if (rdev->family == CHIP_PALM) | |
222 | WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02); | |
223 | ||
224 | sumo_smu_pg_init(rdev); | |
225 | ||
226 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); | |
227 | rcu_pwr_gating_cntl &= | |
228 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); | |
229 | rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN; | |
230 | if (rdev->family == CHIP_PALM) { | |
231 | rcu_pwr_gating_cntl &= ~PCP_MASK; | |
232 | rcu_pwr_gating_cntl |= PCP(0x77); | |
233 | } | |
234 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); | |
235 | ||
236 | if (rdev->family == CHIP_PALM) { | |
237 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); | |
238 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); | |
239 | rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); | |
240 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); | |
241 | ||
242 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); | |
243 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); | |
244 | rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50); | |
245 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); | |
246 | } | |
247 | ||
248 | sumo_smu_pg_init(rdev); | |
249 | ||
250 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); | |
251 | rcu_pwr_gating_cntl &= | |
252 | ~(RSVD_MASK | PCV_MASK | PGS_MASK); | |
253 | rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN; | |
254 | ||
255 | if (rdev->family == CHIP_PALM) { | |
256 | rcu_pwr_gating_cntl |= PCV(4); | |
257 | rcu_pwr_gating_cntl &= ~PCP_MASK; | |
258 | rcu_pwr_gating_cntl |= PCP(0x77); | |
259 | } else | |
260 | rcu_pwr_gating_cntl |= PCV(11); | |
261 | WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); | |
262 | ||
263 | if (rdev->family == CHIP_PALM) { | |
264 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); | |
265 | rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); | |
266 | rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); | |
267 | WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); | |
268 | ||
269 | rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); | |
270 | rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); | |
271 | rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50); | |
272 | WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); | |
273 | } | |
274 | ||
275 | sumo_smu_pg_init(rdev); | |
276 | } | |
277 | ||
278 | static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable) | |
279 | { | |
280 | if (enable) | |
281 | WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); | |
282 | else { | |
283 | WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); | |
284 | RREG32(GB_ADDR_CONFIG); | |
285 | } | |
286 | } | |
287 | ||
288 | static int sumo_enable_clock_power_gating(struct radeon_device *rdev) | |
289 | { | |
290 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
291 | ||
292 | if (pi->enable_gfx_clock_gating) | |
293 | sumo_gfx_clockgating_initialize(rdev); | |
294 | if (pi->enable_gfx_power_gating) | |
295 | sumo_gfx_powergating_initialize(rdev); | |
296 | if (pi->enable_mg_clock_gating) | |
297 | sumo_mg_clockgating_enable(rdev, true); | |
298 | if (pi->enable_gfx_clock_gating) | |
299 | sumo_gfx_clockgating_enable(rdev, true); | |
300 | if (pi->enable_gfx_power_gating) | |
301 | sumo_gfx_powergating_enable(rdev, true); | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | static void sumo_disable_clock_power_gating(struct radeon_device *rdev) | |
307 | { | |
308 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
309 | ||
310 | if (pi->enable_gfx_clock_gating) | |
311 | sumo_gfx_clockgating_enable(rdev, false); | |
312 | if (pi->enable_gfx_power_gating) | |
313 | sumo_gfx_powergating_enable(rdev, false); | |
314 | if (pi->enable_mg_clock_gating) | |
315 | sumo_mg_clockgating_enable(rdev, false); | |
316 | } | |
317 | ||
318 | static void sumo_calculate_bsp(struct radeon_device *rdev, | |
319 | u32 high_clk) | |
320 | { | |
321 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
322 | u32 xclk = sumo_get_xclk(rdev); | |
323 | ||
324 | pi->pasi = 65535 * 100 / high_clk; | |
325 | pi->asi = 65535 * 100 / high_clk; | |
326 | ||
327 | r600_calculate_u_and_p(pi->asi, | |
328 | xclk, 16, &pi->bsp, &pi->bsu); | |
329 | ||
330 | r600_calculate_u_and_p(pi->pasi, | |
331 | xclk, 16, &pi->pbsp, &pi->pbsu); | |
332 | ||
333 | pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); | |
334 | pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); | |
335 | } | |
336 | ||
337 | static void sumo_init_bsp(struct radeon_device *rdev) | |
338 | { | |
339 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
340 | ||
341 | WREG32(CG_BSP_0, pi->psp); | |
342 | } | |
343 | ||
344 | ||
345 | static void sumo_program_bsp(struct radeon_device *rdev) | |
346 | { | |
347 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
348 | struct sumo_ps *ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
349 | u32 i; | |
350 | u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; | |
351 | ||
352 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
353 | highest_engine_clock = pi->boost_pl.sclk; | |
354 | ||
355 | sumo_calculate_bsp(rdev, highest_engine_clock); | |
356 | ||
357 | for (i = 0; i < ps->num_levels - 1; i++) | |
358 | WREG32(CG_BSP_0 + (i * 4), pi->dsp); | |
359 | ||
360 | WREG32(CG_BSP_0 + (i * 4), pi->psp); | |
361 | ||
362 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
363 | WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp); | |
364 | } | |
365 | ||
366 | static void sumo_write_at(struct radeon_device *rdev, | |
367 | u32 index, u32 value) | |
368 | { | |
369 | if (index == 0) | |
370 | WREG32(CG_AT_0, value); | |
371 | else if (index == 1) | |
372 | WREG32(CG_AT_1, value); | |
373 | else if (index == 2) | |
374 | WREG32(CG_AT_2, value); | |
375 | else if (index == 3) | |
376 | WREG32(CG_AT_3, value); | |
377 | else if (index == 4) | |
378 | WREG32(CG_AT_4, value); | |
379 | else if (index == 5) | |
380 | WREG32(CG_AT_5, value); | |
381 | else if (index == 6) | |
382 | WREG32(CG_AT_6, value); | |
383 | else if (index == 7) | |
384 | WREG32(CG_AT_7, value); | |
385 | } | |
386 | ||
387 | static void sumo_program_at(struct radeon_device *rdev) | |
388 | { | |
389 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
390 | struct sumo_ps *ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
391 | u32 asi; | |
392 | u32 i; | |
393 | u32 m_a; | |
394 | u32 a_t; | |
395 | u32 r[SUMO_MAX_HARDWARE_POWERLEVELS]; | |
396 | u32 l[SUMO_MAX_HARDWARE_POWERLEVELS]; | |
397 | ||
398 | r[0] = SUMO_R_DFLT0; | |
399 | r[1] = SUMO_R_DFLT1; | |
400 | r[2] = SUMO_R_DFLT2; | |
401 | r[3] = SUMO_R_DFLT3; | |
402 | r[4] = SUMO_R_DFLT4; | |
403 | ||
404 | l[0] = SUMO_L_DFLT0; | |
405 | l[1] = SUMO_L_DFLT1; | |
406 | l[2] = SUMO_L_DFLT2; | |
407 | l[3] = SUMO_L_DFLT3; | |
408 | l[4] = SUMO_L_DFLT4; | |
409 | ||
410 | for (i = 0; i < ps->num_levels; i++) { | |
411 | asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; | |
412 | ||
413 | m_a = asi * ps->levels[i].sclk / 100; | |
414 | ||
415 | a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100); | |
416 | ||
417 | sumo_write_at(rdev, i, a_t); | |
418 | } | |
419 | ||
420 | if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { | |
421 | asi = pi->pasi; | |
422 | ||
423 | m_a = asi * pi->boost_pl.sclk / 100; | |
424 | ||
425 | a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | | |
426 | CG_L(m_a * l[ps->num_levels - 1] / 100); | |
427 | ||
428 | sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t); | |
429 | } | |
430 | } | |
431 | ||
432 | static void sumo_program_tp(struct radeon_device *rdev) | |
433 | { | |
434 | int i; | |
435 | enum r600_td td = R600_TD_DFLT; | |
436 | ||
437 | for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) { | |
438 | WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); | |
439 | WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK); | |
440 | } | |
441 | ||
442 | if (td == R600_TD_AUTO) | |
443 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); | |
444 | else | |
445 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); | |
446 | ||
447 | if (td == R600_TD_UP) | |
448 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); | |
449 | ||
450 | if (td == R600_TD_DOWN) | |
451 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); | |
452 | } | |
453 | ||
d70229f7 | 454 | void sumo_program_vc(struct radeon_device *rdev, u32 vrc) |
80ea2c12 | 455 | { |
d70229f7 | 456 | WREG32(CG_FTV, vrc); |
80ea2c12 AD |
457 | } |
458 | ||
d70229f7 | 459 | void sumo_clear_vc(struct radeon_device *rdev) |
80ea2c12 AD |
460 | { |
461 | WREG32(CG_FTV, 0); | |
462 | } | |
463 | ||
d70229f7 | 464 | void sumo_program_sstp(struct radeon_device *rdev) |
80ea2c12 AD |
465 | { |
466 | u32 p, u; | |
467 | u32 xclk = sumo_get_xclk(rdev); | |
468 | ||
469 | r600_calculate_u_and_p(SUMO_SST_DFLT, | |
470 | xclk, 16, &p, &u); | |
471 | ||
472 | WREG32(CG_SSP, SSTU(u) | SST(p)); | |
473 | } | |
474 | ||
475 | static void sumo_set_divider_value(struct radeon_device *rdev, | |
476 | u32 index, u32 divider) | |
477 | { | |
478 | u32 reg_index = index / 4; | |
479 | u32 field_index = index % 4; | |
480 | ||
481 | if (field_index == 0) | |
482 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
483 | SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK); | |
484 | else if (field_index == 1) | |
485 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
486 | SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK); | |
487 | else if (field_index == 2) | |
488 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
489 | SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK); | |
490 | else if (field_index == 3) | |
491 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
492 | SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK); | |
493 | } | |
494 | ||
495 | static void sumo_set_ds_dividers(struct radeon_device *rdev, | |
496 | u32 index, u32 divider) | |
497 | { | |
498 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
499 | ||
500 | if (pi->enable_sclk_ds) { | |
501 | u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6); | |
502 | ||
503 | dpm_ctrl &= ~(0x7 << (index * 3)); | |
504 | dpm_ctrl |= (divider << (index * 3)); | |
505 | WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl); | |
506 | } | |
507 | } | |
508 | ||
509 | static void sumo_set_ss_dividers(struct radeon_device *rdev, | |
510 | u32 index, u32 divider) | |
511 | { | |
512 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
513 | ||
514 | if (pi->enable_sclk_ds) { | |
515 | u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11); | |
516 | ||
517 | dpm_ctrl &= ~(0x7 << (index * 3)); | |
518 | dpm_ctrl |= (divider << (index * 3)); | |
519 | WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl); | |
520 | } | |
521 | } | |
522 | ||
523 | static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid) | |
524 | { | |
525 | u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL); | |
526 | ||
527 | voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2)); | |
528 | voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2)); | |
529 | WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl); | |
530 | } | |
531 | ||
532 | static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow) | |
533 | { | |
534 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
535 | u32 temp = gnb_slow; | |
536 | u32 cg_sclk_dpm_ctrl_3; | |
537 | ||
538 | if (pi->driver_nbps_policy_disable) | |
539 | temp = 1; | |
540 | ||
541 | cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); | |
542 | cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index); | |
543 | cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index)); | |
544 | ||
545 | WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); | |
546 | } | |
547 | ||
548 | static void sumo_program_power_level(struct radeon_device *rdev, | |
549 | struct sumo_pl *pl, u32 index) | |
550 | { | |
551 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
552 | int ret; | |
553 | struct atom_clock_dividers dividers; | |
554 | u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS; | |
555 | ||
556 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
557 | pl->sclk, false, ÷rs); | |
558 | if (ret) | |
559 | return; | |
560 | ||
561 | sumo_set_divider_value(rdev, index, dividers.post_div); | |
562 | ||
563 | sumo_set_vid(rdev, index, pl->vddc_index); | |
564 | ||
565 | if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) { | |
566 | if (ds_en) | |
567 | WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); | |
568 | } else { | |
569 | sumo_set_ss_dividers(rdev, index, pl->ss_divider_index); | |
570 | sumo_set_ds_dividers(rdev, index, pl->ds_divider_index); | |
571 | ||
572 | if (!ds_en) | |
573 | WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS); | |
574 | } | |
575 | ||
576 | sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow); | |
577 | ||
578 | if (pi->enable_boost) | |
579 | sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit); | |
580 | } | |
581 | ||
582 | static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable) | |
583 | { | |
584 | u32 reg_index = index / 4; | |
585 | u32 field_index = index % 4; | |
586 | ||
587 | if (field_index == 0) | |
588 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
589 | enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD); | |
590 | else if (field_index == 1) | |
591 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
592 | enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD); | |
593 | else if (field_index == 2) | |
594 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
595 | enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD); | |
596 | else if (field_index == 3) | |
597 | WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), | |
598 | enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD); | |
599 | } | |
600 | ||
601 | static bool sumo_dpm_enabled(struct radeon_device *rdev) | |
602 | { | |
603 | if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) | |
604 | return true; | |
605 | else | |
606 | return false; | |
607 | } | |
608 | ||
609 | static void sumo_start_dpm(struct radeon_device *rdev) | |
610 | { | |
611 | WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE); | |
612 | } | |
613 | ||
614 | static void sumo_stop_dpm(struct radeon_device *rdev) | |
615 | { | |
616 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE); | |
617 | } | |
618 | ||
619 | static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable) | |
620 | { | |
621 | if (enable) | |
622 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN); | |
623 | else | |
624 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN); | |
625 | } | |
626 | ||
627 | static void sumo_set_forced_mode_enabled(struct radeon_device *rdev) | |
628 | { | |
629 | int i; | |
630 | ||
631 | sumo_set_forced_mode(rdev, true); | |
632 | for (i = 0; i < rdev->usec_timeout; i++) { | |
633 | if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT) | |
634 | break; | |
635 | udelay(1); | |
636 | } | |
637 | } | |
638 | ||
639 | static void sumo_wait_for_level_0(struct radeon_device *rdev) | |
640 | { | |
641 | int i; | |
642 | ||
643 | for (i = 0; i < rdev->usec_timeout; i++) { | |
644 | if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0) | |
645 | break; | |
646 | udelay(1); | |
647 | } | |
648 | for (i = 0; i < rdev->usec_timeout; i++) { | |
649 | if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0) | |
650 | break; | |
651 | udelay(1); | |
652 | } | |
653 | } | |
654 | ||
655 | static void sumo_set_forced_mode_disabled(struct radeon_device *rdev) | |
656 | { | |
657 | sumo_set_forced_mode(rdev, false); | |
658 | } | |
659 | ||
660 | static void sumo_enable_power_level_0(struct radeon_device *rdev) | |
661 | { | |
662 | sumo_power_level_enable(rdev, 0, true); | |
663 | } | |
664 | ||
665 | static void sumo_patch_boost_state(struct radeon_device *rdev) | |
666 | { | |
667 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
668 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
669 | ||
670 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { | |
671 | pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; | |
672 | pi->boost_pl.sclk = pi->sys_info.boost_sclk; | |
673 | pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit; | |
674 | pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost; | |
675 | } | |
676 | } | |
677 | ||
678 | static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev) | |
679 | { | |
680 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
681 | struct sumo_ps *old_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
682 | u32 nbps1_old = 0; | |
683 | u32 nbps1_new = 0; | |
684 | ||
685 | if (old_ps != NULL) | |
686 | nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; | |
687 | ||
688 | nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; | |
689 | ||
690 | if (nbps1_old == 1 && nbps1_new == 0) | |
691 | sumo_smu_notify_alt_vddnb_change(rdev, 0, 0); | |
692 | } | |
693 | ||
694 | static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev) | |
695 | { | |
696 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
697 | struct sumo_ps *old_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
698 | u32 nbps1_old = 0; | |
699 | u32 nbps1_new = 0; | |
700 | ||
701 | if (old_ps != NULL) | |
702 | nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; | |
703 | ||
704 | nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; | |
705 | ||
706 | if (nbps1_old == 0 && nbps1_new == 1) | |
707 | sumo_smu_notify_alt_vddnb_change(rdev, 1, 1); | |
708 | } | |
709 | ||
710 | static void sumo_enable_boost(struct radeon_device *rdev, bool enable) | |
711 | { | |
712 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
713 | ||
714 | if (enable) { | |
715 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
716 | sumo_boost_state_enable(rdev, true); | |
717 | } else | |
718 | sumo_boost_state_enable(rdev, false); | |
719 | } | |
720 | ||
721 | static void sumo_update_current_power_levels(struct radeon_device *rdev) | |
722 | { | |
723 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
724 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
725 | ||
726 | pi->current_ps = *new_ps; | |
727 | } | |
728 | ||
729 | static void sumo_set_forced_level(struct radeon_device *rdev, u32 index) | |
730 | { | |
731 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK); | |
732 | } | |
733 | ||
734 | static void sumo_set_forced_level_0(struct radeon_device *rdev) | |
735 | { | |
736 | sumo_set_forced_level(rdev, 0); | |
737 | } | |
738 | ||
739 | static void sumo_program_wl(struct radeon_device *rdev) | |
740 | { | |
741 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
742 | u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); | |
743 | ||
744 | dpm_ctrl4 &= 0xFFFFFF00; | |
745 | dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); | |
746 | ||
747 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
748 | dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL); | |
749 | ||
750 | WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); | |
751 | } | |
752 | ||
753 | static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev) | |
754 | { | |
755 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
756 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
757 | struct sumo_ps *old_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
758 | u32 i; | |
759 | u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; | |
760 | ||
761 | for (i = 0; i < new_ps->num_levels; i++) { | |
762 | sumo_program_power_level(rdev, &new_ps->levels[i], i); | |
763 | sumo_power_level_enable(rdev, i, true); | |
764 | } | |
765 | ||
766 | for (i = new_ps->num_levels; i < n_current_state_levels; i++) | |
767 | sumo_power_level_enable(rdev, i, false); | |
768 | ||
769 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) | |
770 | sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL); | |
771 | } | |
772 | ||
773 | static void sumo_enable_acpi_pm(struct radeon_device *rdev) | |
774 | { | |
775 | WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); | |
776 | } | |
777 | ||
778 | static void sumo_program_power_level_enter_state(struct radeon_device *rdev) | |
779 | { | |
780 | WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK); | |
781 | } | |
782 | ||
783 | static void sumo_program_acpi_power_level(struct radeon_device *rdev) | |
784 | { | |
785 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
786 | struct atom_clock_dividers dividers; | |
787 | int ret; | |
788 | ||
789 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
790 | pi->acpi_pl.sclk, | |
791 | false, ÷rs); | |
792 | if (ret) | |
793 | return; | |
794 | ||
795 | WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK); | |
796 | WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN); | |
797 | } | |
798 | ||
799 | static void sumo_program_bootup_state(struct radeon_device *rdev) | |
800 | { | |
801 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
802 | u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); | |
803 | u32 i; | |
804 | ||
805 | sumo_program_power_level(rdev, &pi->boot_pl, 0); | |
806 | ||
807 | dpm_ctrl4 &= 0xFFFFFF00; | |
808 | WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); | |
809 | ||
810 | for (i = 1; i < 8; i++) | |
811 | sumo_power_level_enable(rdev, i, false); | |
812 | } | |
813 | ||
d70229f7 | 814 | void sumo_take_smu_control(struct radeon_device *rdev, bool enable) |
80ea2c12 | 815 | { |
65676d06 AD |
816 | /* This bit selects who handles display phy powergating. |
817 | * Clear the bit to let atom handle it. | |
818 | * Set it to let the driver handle it. | |
819 | * For now we just let atom handle it. | |
820 | */ | |
821 | #if 0 | |
80ea2c12 AD |
822 | u32 v = RREG32(DOUT_SCRATCH3); |
823 | ||
824 | if (enable) | |
825 | v |= 0x4; | |
826 | else | |
827 | v &= 0xFFFFFFFB; | |
828 | ||
829 | WREG32(DOUT_SCRATCH3, v); | |
65676d06 | 830 | #endif |
80ea2c12 AD |
831 | } |
832 | ||
833 | static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable) | |
834 | { | |
835 | if (enable) { | |
836 | u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL); | |
837 | u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2); | |
838 | u32 t = 1; | |
839 | ||
840 | deep_sleep_cntl &= ~R_DIS; | |
841 | deep_sleep_cntl &= ~HS_MASK; | |
842 | deep_sleep_cntl |= HS(t > 4095 ? 4095 : t); | |
843 | ||
844 | deep_sleep_cntl2 |= LB_UFP_EN; | |
845 | deep_sleep_cntl2 &= INOUT_C_MASK; | |
846 | deep_sleep_cntl2 |= INOUT_C(0xf); | |
847 | ||
848 | WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2); | |
849 | WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl); | |
850 | } else | |
851 | WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); | |
852 | } | |
853 | ||
854 | static void sumo_program_bootup_at(struct radeon_device *rdev) | |
855 | { | |
856 | WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK); | |
857 | WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); | |
858 | } | |
859 | ||
860 | static void sumo_reset_am(struct radeon_device *rdev) | |
861 | { | |
862 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); | |
863 | } | |
864 | ||
865 | static void sumo_start_am(struct radeon_device *rdev) | |
866 | { | |
867 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET); | |
868 | } | |
869 | ||
870 | static void sumo_program_ttp(struct radeon_device *rdev) | |
871 | { | |
872 | u32 xclk = sumo_get_xclk(rdev); | |
873 | u32 p, u; | |
874 | u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); | |
875 | ||
876 | r600_calculate_u_and_p(1000, | |
877 | xclk, 16, &p, &u); | |
878 | ||
879 | cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK); | |
880 | cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u); | |
881 | ||
882 | WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5); | |
883 | } | |
884 | ||
885 | static void sumo_program_ttt(struct radeon_device *rdev) | |
886 | { | |
887 | u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); | |
888 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
889 | ||
890 | cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK); | |
891 | cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49); | |
892 | ||
893 | WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); | |
894 | } | |
895 | ||
896 | ||
897 | static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable) | |
898 | { | |
899 | if (enable) { | |
900 | WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN); | |
901 | WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN); | |
902 | } else { | |
903 | WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN); | |
904 | WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN); | |
905 | } | |
906 | } | |
907 | ||
908 | static void sumo_override_cnb_thermal_events(struct radeon_device *rdev) | |
909 | { | |
910 | WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK, | |
911 | ~CNB_THERMTHRO_MASK_SCLK); | |
912 | } | |
913 | ||
914 | static void sumo_program_dc_hto(struct radeon_device *rdev) | |
915 | { | |
916 | u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); | |
917 | u32 p, u; | |
918 | u32 xclk = sumo_get_xclk(rdev); | |
919 | ||
920 | r600_calculate_u_and_p(100000, | |
921 | xclk, 14, &p, &u); | |
922 | ||
923 | cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK); | |
924 | cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u); | |
925 | ||
926 | WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4); | |
927 | } | |
928 | ||
929 | static void sumo_force_nbp_state(struct radeon_device *rdev) | |
930 | { | |
931 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
932 | struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
933 | ||
934 | if (!pi->driver_nbps_policy_disable) { | |
935 | if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) | |
936 | WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1); | |
937 | else | |
938 | WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1); | |
939 | } | |
940 | } | |
941 | ||
d70229f7 | 942 | u32 sumo_get_sleep_divider_from_id(u32 id) |
80ea2c12 AD |
943 | { |
944 | return 1 << id; | |
945 | } | |
946 | ||
d70229f7 AD |
947 | u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, |
948 | u32 sclk, | |
949 | u32 min_sclk_in_sr) | |
80ea2c12 AD |
950 | { |
951 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
952 | u32 i; | |
953 | u32 temp; | |
954 | u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ? | |
955 | min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK; | |
956 | ||
957 | if (sclk < min) | |
958 | return 0; | |
959 | ||
960 | if (!pi->enable_sclk_ds) | |
961 | return 0; | |
962 | ||
963 | for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { | |
964 | temp = sclk / sumo_get_sleep_divider_from_id(i); | |
965 | ||
966 | if (temp >= min || i == 0) | |
967 | break; | |
968 | } | |
969 | return i; | |
970 | } | |
971 | ||
972 | static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev, | |
973 | u32 lower_limit) | |
974 | { | |
975 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
976 | u32 i; | |
977 | ||
978 | for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { | |
979 | if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) | |
980 | return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; | |
981 | } | |
982 | ||
983 | return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency; | |
984 | } | |
985 | ||
986 | static void sumo_patch_thermal_state(struct radeon_device *rdev, | |
987 | struct sumo_ps *ps, | |
988 | struct sumo_ps *current_ps) | |
989 | { | |
990 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
991 | u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ | |
992 | u32 current_vddc; | |
993 | u32 current_sclk; | |
994 | u32 current_index = 0; | |
995 | ||
996 | if (current_ps) { | |
997 | current_vddc = current_ps->levels[current_index].vddc_index; | |
998 | current_sclk = current_ps->levels[current_index].sclk; | |
999 | } else { | |
1000 | current_vddc = pi->boot_pl.vddc_index; | |
1001 | current_sclk = pi->boot_pl.sclk; | |
1002 | } | |
1003 | ||
1004 | ps->levels[0].vddc_index = current_vddc; | |
1005 | ||
1006 | if (ps->levels[0].sclk > current_sclk) | |
1007 | ps->levels[0].sclk = current_sclk; | |
1008 | ||
1009 | ps->levels[0].ss_divider_index = | |
1010 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); | |
1011 | ||
1012 | ps->levels[0].ds_divider_index = | |
1013 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK); | |
1014 | ||
1015 | if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1) | |
1016 | ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1; | |
1017 | ||
1018 | if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) { | |
1019 | if (ps->levels[0].ss_divider_index > 1) | |
1020 | ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1; | |
1021 | } | |
1022 | ||
1023 | if (ps->levels[0].ss_divider_index == 0) | |
1024 | ps->levels[0].ds_divider_index = 0; | |
1025 | ||
1026 | if (ps->levels[0].ds_divider_index == 0) | |
1027 | ps->levels[0].ss_divider_index = 0; | |
1028 | } | |
1029 | ||
1030 | static void sumo_apply_state_adjust_rules(struct radeon_device *rdev) | |
1031 | { | |
1032 | struct radeon_ps *rps = rdev->pm.dpm.requested_ps; | |
1033 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1034 | struct sumo_ps *current_ps = sumo_get_ps(rdev->pm.dpm.current_ps); | |
1035 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1036 | u32 min_voltage = 0; /* ??? */ | |
1037 | u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ | |
1038 | u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ | |
1039 | u32 i; | |
1040 | ||
1041 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) | |
1042 | return sumo_patch_thermal_state(rdev, ps, current_ps); | |
1043 | ||
1044 | if (pi->enable_boost) { | |
1045 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) | |
1046 | ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE; | |
1047 | } | |
1048 | ||
1049 | if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) || | |
1050 | (rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) || | |
1051 | (rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)) | |
1052 | ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE; | |
1053 | ||
1054 | for (i = 0; i < ps->num_levels; i++) { | |
1055 | if (ps->levels[i].vddc_index < min_voltage) | |
1056 | ps->levels[i].vddc_index = min_voltage; | |
1057 | ||
1058 | if (ps->levels[i].sclk < min_sclk) | |
1059 | ps->levels[i].sclk = | |
1060 | sumo_get_valid_engine_clock(rdev, min_sclk); | |
1061 | ||
1062 | ps->levels[i].ss_divider_index = | |
1063 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); | |
1064 | ||
1065 | ps->levels[i].ds_divider_index = | |
1066 | sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK); | |
1067 | ||
1068 | if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1) | |
1069 | ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1; | |
1070 | ||
1071 | if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) { | |
1072 | if (ps->levels[i].ss_divider_index > 1) | |
1073 | ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1; | |
1074 | } | |
1075 | ||
1076 | if (ps->levels[i].ss_divider_index == 0) | |
1077 | ps->levels[i].ds_divider_index = 0; | |
1078 | ||
1079 | if (ps->levels[i].ds_divider_index == 0) | |
1080 | ps->levels[i].ss_divider_index = 0; | |
1081 | ||
1082 | if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) | |
1083 | ps->levels[i].allow_gnb_slow = 1; | |
1084 | else if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) || | |
1085 | (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)) | |
1086 | ps->levels[i].allow_gnb_slow = 0; | |
1087 | else if (i == ps->num_levels - 1) | |
1088 | ps->levels[i].allow_gnb_slow = 0; | |
1089 | else | |
1090 | ps->levels[i].allow_gnb_slow = 1; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | static void sumo_cleanup_asic(struct radeon_device *rdev) | |
1095 | { | |
1096 | sumo_take_smu_control(rdev, false); | |
1097 | } | |
1098 | ||
1099 | static int sumo_set_thermal_temperature_range(struct radeon_device *rdev, | |
1100 | int min_temp, int max_temp) | |
1101 | { | |
1102 | int low_temp = 0 * 1000; | |
1103 | int high_temp = 255 * 1000; | |
1104 | ||
1105 | if (low_temp < min_temp) | |
1106 | low_temp = min_temp; | |
1107 | if (high_temp > max_temp) | |
1108 | high_temp = max_temp; | |
1109 | if (high_temp < low_temp) { | |
1110 | DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); | |
1111 | return -EINVAL; | |
1112 | } | |
1113 | ||
1114 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); | |
1115 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); | |
1116 | ||
1117 | rdev->pm.dpm.thermal.min_temp = low_temp; | |
1118 | rdev->pm.dpm.thermal.max_temp = high_temp; | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | int sumo_dpm_enable(struct radeon_device *rdev) | |
1124 | { | |
1125 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1126 | ||
1127 | if (sumo_dpm_enabled(rdev)) | |
1128 | return -EINVAL; | |
1129 | ||
1130 | sumo_enable_clock_power_gating(rdev); | |
1131 | sumo_program_bootup_state(rdev); | |
1132 | sumo_init_bsp(rdev); | |
1133 | sumo_reset_am(rdev); | |
1134 | sumo_program_tp(rdev); | |
1135 | sumo_program_bootup_at(rdev); | |
1136 | sumo_start_am(rdev); | |
1137 | if (pi->enable_auto_thermal_throttling) { | |
1138 | sumo_program_ttp(rdev); | |
1139 | sumo_program_ttt(rdev); | |
1140 | } | |
1141 | sumo_program_dc_hto(rdev); | |
1142 | sumo_program_power_level_enter_state(rdev); | |
1143 | sumo_enable_voltage_scaling(rdev, true); | |
1144 | sumo_program_sstp(rdev); | |
d70229f7 | 1145 | sumo_program_vc(rdev, SUMO_VRC_DFLT); |
80ea2c12 AD |
1146 | sumo_override_cnb_thermal_events(rdev); |
1147 | sumo_start_dpm(rdev); | |
1148 | sumo_wait_for_level_0(rdev); | |
1149 | if (pi->enable_sclk_ds) | |
1150 | sumo_enable_sclk_ds(rdev, true); | |
1151 | if (pi->enable_boost) | |
1152 | sumo_enable_boost_timer(rdev); | |
1153 | ||
1154 | if (rdev->irq.installed && | |
1155 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { | |
1156 | sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); | |
1157 | rdev->irq.dpm_thermal = true; | |
1158 | radeon_irq_set(rdev); | |
1159 | } | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | void sumo_dpm_disable(struct radeon_device *rdev) | |
1165 | { | |
1166 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1167 | ||
1168 | if (!sumo_dpm_enabled(rdev)) | |
1169 | return; | |
1170 | sumo_disable_clock_power_gating(rdev); | |
1171 | if (pi->enable_sclk_ds) | |
1172 | sumo_enable_sclk_ds(rdev, false); | |
1173 | sumo_clear_vc(rdev); | |
1174 | sumo_wait_for_level_0(rdev); | |
1175 | sumo_stop_dpm(rdev); | |
1176 | sumo_enable_voltage_scaling(rdev, false); | |
1177 | ||
1178 | if (rdev->irq.installed && | |
1179 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { | |
1180 | rdev->irq.dpm_thermal = false; | |
1181 | radeon_irq_set(rdev); | |
1182 | } | |
1183 | } | |
1184 | ||
1185 | int sumo_dpm_set_power_state(struct radeon_device *rdev) | |
1186 | { | |
1187 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1188 | ||
1189 | if (pi->enable_dynamic_patch_ps) | |
1190 | sumo_apply_state_adjust_rules(rdev); | |
1191 | sumo_update_current_power_levels(rdev); | |
1192 | if (pi->enable_boost) { | |
1193 | sumo_enable_boost(rdev, false); | |
1194 | sumo_patch_boost_state(rdev); | |
1195 | } | |
1196 | if (pi->enable_dpm) { | |
1197 | sumo_pre_notify_alt_vddnb_change(rdev); | |
1198 | sumo_enable_power_level_0(rdev); | |
1199 | sumo_set_forced_level_0(rdev); | |
1200 | sumo_set_forced_mode_enabled(rdev); | |
1201 | sumo_wait_for_level_0(rdev); | |
1202 | sumo_program_power_levels_0_to_n(rdev); | |
1203 | sumo_program_wl(rdev); | |
1204 | sumo_program_bsp(rdev); | |
1205 | sumo_program_at(rdev); | |
1206 | sumo_force_nbp_state(rdev); | |
1207 | sumo_set_forced_mode_disabled(rdev); | |
1208 | sumo_set_forced_mode_enabled(rdev); | |
1209 | sumo_set_forced_mode_disabled(rdev); | |
1210 | sumo_post_notify_alt_vddnb_change(rdev); | |
1211 | } | |
1212 | if (pi->enable_boost) | |
1213 | sumo_enable_boost(rdev, true); | |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | void sumo_dpm_reset_asic(struct radeon_device *rdev) | |
1219 | { | |
1220 | sumo_program_bootup_state(rdev); | |
1221 | sumo_enable_power_level_0(rdev); | |
1222 | sumo_set_forced_level_0(rdev); | |
1223 | sumo_set_forced_mode_enabled(rdev); | |
1224 | sumo_wait_for_level_0(rdev); | |
1225 | sumo_set_forced_mode_disabled(rdev); | |
1226 | sumo_set_forced_mode_enabled(rdev); | |
1227 | sumo_set_forced_mode_disabled(rdev); | |
1228 | } | |
1229 | ||
1230 | void sumo_dpm_setup_asic(struct radeon_device *rdev) | |
1231 | { | |
1232 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1233 | ||
1234 | sumo_initialize_m3_arb(rdev); | |
1235 | pi->fw_version = sumo_get_running_fw_version(rdev); | |
1236 | DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version); | |
1237 | sumo_program_acpi_power_level(rdev); | |
1238 | sumo_enable_acpi_pm(rdev); | |
1239 | sumo_take_smu_control(rdev, true); | |
1240 | } | |
1241 | ||
1242 | void sumo_dpm_display_configuration_changed(struct radeon_device *rdev) | |
1243 | { | |
1244 | ||
1245 | } | |
1246 | ||
1247 | union power_info { | |
1248 | struct _ATOM_POWERPLAY_INFO info; | |
1249 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
1250 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
1251 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; | |
1252 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; | |
1253 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; | |
1254 | }; | |
1255 | ||
1256 | union pplib_clock_info { | |
1257 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; | |
1258 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; | |
1259 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; | |
1260 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; | |
1261 | }; | |
1262 | ||
1263 | union pplib_power_state { | |
1264 | struct _ATOM_PPLIB_STATE v1; | |
1265 | struct _ATOM_PPLIB_STATE_V2 v2; | |
1266 | }; | |
1267 | ||
1268 | static void sumo_patch_boot_state(struct radeon_device *rdev, | |
1269 | struct sumo_ps *ps) | |
1270 | { | |
1271 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1272 | ||
1273 | ps->num_levels = 1; | |
1274 | ps->flags = 0; | |
1275 | ps->levels[0] = pi->boot_pl; | |
1276 | } | |
1277 | ||
1278 | static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev, | |
1279 | struct radeon_ps *rps, | |
1280 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, | |
1281 | u8 table_rev) | |
1282 | { | |
1283 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1284 | ||
1285 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); | |
1286 | rps->class = le16_to_cpu(non_clock_info->usClassification); | |
1287 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); | |
1288 | ||
1289 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { | |
1290 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); | |
1291 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); | |
1292 | } else { | |
1293 | rps->vclk = 0; | |
1294 | rps->dclk = 0; | |
1295 | } | |
1296 | ||
1297 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { | |
1298 | rdev->pm.dpm.boot_ps = rps; | |
1299 | sumo_patch_boot_state(rdev, ps); | |
1300 | } | |
1301 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | |
1302 | rdev->pm.dpm.uvd_ps = rps; | |
1303 | } | |
1304 | ||
1305 | static void sumo_parse_pplib_clock_info(struct radeon_device *rdev, | |
1306 | struct radeon_ps *rps, int index, | |
1307 | union pplib_clock_info *clock_info) | |
1308 | { | |
1309 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1310 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1311 | struct sumo_pl *pl = &ps->levels[index]; | |
1312 | u32 sclk; | |
1313 | ||
1314 | sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); | |
1315 | sclk |= clock_info->sumo.ucEngineClockHigh << 16; | |
1316 | pl->sclk = sclk; | |
1317 | pl->vddc_index = clock_info->sumo.vddcIndex; | |
1318 | pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit; | |
1319 | ||
1320 | ps->num_levels = index + 1; | |
1321 | ||
1322 | if (pi->enable_sclk_ds) { | |
1323 | pl->ds_divider_index = 5; | |
1324 | pl->ss_divider_index = 4; | |
1325 | } | |
1326 | } | |
1327 | ||
1328 | static int sumo_parse_power_table(struct radeon_device *rdev) | |
1329 | { | |
1330 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1331 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
1332 | union pplib_power_state *power_state; | |
1333 | int i, j, k, non_clock_array_index, clock_array_index; | |
1334 | union pplib_clock_info *clock_info; | |
1335 | struct _StateArray *state_array; | |
1336 | struct _ClockInfoArray *clock_info_array; | |
1337 | struct _NonClockInfoArray *non_clock_info_array; | |
1338 | union power_info *power_info; | |
1339 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
1340 | u16 data_offset; | |
1341 | u8 frev, crev; | |
1342 | u8 *power_state_offset; | |
1343 | struct sumo_ps *ps; | |
1344 | ||
1345 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, | |
1346 | &frev, &crev, &data_offset)) | |
1347 | return -EINVAL; | |
1348 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
1349 | ||
1350 | state_array = (struct _StateArray *) | |
1351 | (mode_info->atom_context->bios + data_offset + | |
1352 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); | |
1353 | clock_info_array = (struct _ClockInfoArray *) | |
1354 | (mode_info->atom_context->bios + data_offset + | |
1355 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); | |
1356 | non_clock_info_array = (struct _NonClockInfoArray *) | |
1357 | (mode_info->atom_context->bios + data_offset + | |
1358 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); | |
1359 | ||
1360 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * | |
1361 | state_array->ucNumEntries, GFP_KERNEL); | |
1362 | if (!rdev->pm.dpm.ps) | |
1363 | return -ENOMEM; | |
1364 | power_state_offset = (u8 *)state_array->states; | |
1365 | rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); | |
1366 | rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); | |
1367 | rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); | |
1368 | for (i = 0; i < state_array->ucNumEntries; i++) { | |
1369 | power_state = (union pplib_power_state *)power_state_offset; | |
1370 | non_clock_array_index = power_state->v2.nonClockInfoIndex; | |
1371 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
1372 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; | |
1373 | if (!rdev->pm.power_state[i].clock_info) | |
1374 | return -EINVAL; | |
1375 | ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); | |
1376 | if (ps == NULL) { | |
1377 | kfree(rdev->pm.dpm.ps); | |
1378 | return -ENOMEM; | |
1379 | } | |
1380 | rdev->pm.dpm.ps[i].ps_priv = ps; | |
1381 | k = 0; | |
1382 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { | |
1383 | clock_array_index = power_state->v2.clockInfoIndex[j]; | |
1384 | if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) | |
1385 | break; | |
1386 | clock_info = (union pplib_clock_info *) | |
1387 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; | |
1388 | sumo_parse_pplib_clock_info(rdev, | |
1389 | &rdev->pm.dpm.ps[i], k, | |
1390 | clock_info); | |
1391 | k++; | |
1392 | } | |
1393 | sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], | |
1394 | non_clock_info, | |
1395 | non_clock_info_array->ucEntrySize); | |
1396 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; | |
1397 | } | |
1398 | rdev->pm.dpm.num_ps = state_array->ucNumEntries; | |
1399 | return 0; | |
1400 | } | |
1401 | ||
d70229f7 AD |
1402 | u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, |
1403 | struct sumo_vid_mapping_table *vid_mapping_table, | |
1404 | u32 vid_2bit) | |
80ea2c12 | 1405 | { |
80ea2c12 AD |
1406 | u32 i; |
1407 | ||
d70229f7 AD |
1408 | for (i = 0; i < vid_mapping_table->num_entries; i++) { |
1409 | if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) | |
1410 | return vid_mapping_table->entries[i].vid_7bit; | |
80ea2c12 AD |
1411 | } |
1412 | ||
d70229f7 | 1413 | return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; |
80ea2c12 AD |
1414 | } |
1415 | ||
1416 | static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev, | |
1417 | u32 vid_2bit) | |
1418 | { | |
d70229f7 AD |
1419 | struct sumo_power_info *pi = sumo_get_pi(rdev); |
1420 | u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit); | |
80ea2c12 AD |
1421 | |
1422 | if (vid_7bit > 0x7C) | |
1423 | return 0; | |
1424 | ||
1425 | return (15500 - vid_7bit * 125 + 5) / 10; | |
1426 | } | |
1427 | ||
1428 | static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev, | |
d70229f7 | 1429 | struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table, |
80ea2c12 AD |
1430 | ATOM_CLK_VOLT_CAPABILITY *table) |
1431 | { | |
80ea2c12 AD |
1432 | u32 i; |
1433 | ||
1434 | for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { | |
1435 | if (table[i].ulMaximumSupportedCLK == 0) | |
1436 | break; | |
1437 | ||
d70229f7 | 1438 | disp_clk_voltage_mapping_table->display_clock_frequency[i] = |
80ea2c12 AD |
1439 | table[i].ulMaximumSupportedCLK; |
1440 | } | |
1441 | ||
d70229f7 | 1442 | disp_clk_voltage_mapping_table->num_max_voltage_levels = i; |
80ea2c12 | 1443 | |
d70229f7 AD |
1444 | if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) { |
1445 | disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000; | |
1446 | disp_clk_voltage_mapping_table->num_max_voltage_levels = 1; | |
80ea2c12 AD |
1447 | } |
1448 | } | |
1449 | ||
d70229f7 AD |
1450 | void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, |
1451 | struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, | |
1452 | ATOM_AVAILABLE_SCLK_LIST *table) | |
80ea2c12 | 1453 | { |
80ea2c12 AD |
1454 | u32 i; |
1455 | u32 n = 0; | |
1456 | u32 prev_sclk = 0; | |
1457 | ||
1458 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { | |
1459 | if (table[i].ulSupportedSCLK > prev_sclk) { | |
d70229f7 | 1460 | sclk_voltage_mapping_table->entries[n].sclk_frequency = |
80ea2c12 | 1461 | table[i].ulSupportedSCLK; |
d70229f7 | 1462 | sclk_voltage_mapping_table->entries[n].vid_2bit = |
80ea2c12 AD |
1463 | table[i].usVoltageIndex; |
1464 | prev_sclk = table[i].ulSupportedSCLK; | |
1465 | n++; | |
1466 | } | |
1467 | } | |
1468 | ||
d70229f7 | 1469 | sclk_voltage_mapping_table->num_max_dpm_entries = n; |
80ea2c12 AD |
1470 | } |
1471 | ||
d70229f7 AD |
1472 | void sumo_construct_vid_mapping_table(struct radeon_device *rdev, |
1473 | struct sumo_vid_mapping_table *vid_mapping_table, | |
1474 | ATOM_AVAILABLE_SCLK_LIST *table) | |
80ea2c12 | 1475 | { |
80ea2c12 AD |
1476 | u32 i, j; |
1477 | ||
1478 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { | |
1479 | if (table[i].ulSupportedSCLK != 0) { | |
d70229f7 | 1480 | vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit = |
80ea2c12 | 1481 | table[i].usVoltageID; |
d70229f7 | 1482 | vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit = |
80ea2c12 AD |
1483 | table[i].usVoltageIndex; |
1484 | } | |
1485 | } | |
1486 | ||
1487 | for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { | |
d70229f7 | 1488 | if (vid_mapping_table->entries[i].vid_7bit == 0) { |
80ea2c12 | 1489 | for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { |
d70229f7 AD |
1490 | if (vid_mapping_table->entries[j].vid_7bit != 0) { |
1491 | vid_mapping_table->entries[i] = | |
1492 | vid_mapping_table->entries[j]; | |
1493 | vid_mapping_table->entries[j].vid_7bit = 0; | |
80ea2c12 AD |
1494 | break; |
1495 | } | |
1496 | } | |
1497 | ||
1498 | if (j == SUMO_MAX_NUMBER_VOLTAGES) | |
1499 | break; | |
1500 | } | |
1501 | } | |
1502 | ||
d70229f7 | 1503 | vid_mapping_table->num_entries = i; |
80ea2c12 AD |
1504 | } |
1505 | ||
1506 | union igp_info { | |
1507 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
1508 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; | |
1509 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; | |
1510 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; | |
1511 | }; | |
1512 | ||
1513 | static int sumo_parse_sys_info_table(struct radeon_device *rdev) | |
1514 | { | |
1515 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1516 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1517 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
1518 | union igp_info *igp_info; | |
1519 | u8 frev, crev; | |
1520 | u16 data_offset; | |
1521 | int i; | |
1522 | ||
1523 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, | |
1524 | &frev, &crev, &data_offset)) { | |
1525 | igp_info = (union igp_info *)(mode_info->atom_context->bios + | |
1526 | data_offset); | |
1527 | ||
1528 | if (crev != 6) { | |
1529 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
1530 | return -EINVAL; | |
1531 | } | |
1532 | pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock); | |
1533 | pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock); | |
1534 | pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock); | |
1535 | pi->sys_info.bootup_nb_voltage_index = | |
1536 | le16_to_cpu(igp_info->info_6.usBootUpNBVoltage); | |
1537 | if (igp_info->info_6.ucHtcTmpLmt == 0) | |
1538 | pi->sys_info.htc_tmp_lmt = 203; | |
1539 | else | |
1540 | pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt; | |
1541 | if (igp_info->info_6.ucHtcHystLmt == 0) | |
1542 | pi->sys_info.htc_hyst_lmt = 5; | |
1543 | else | |
1544 | pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt; | |
1545 | if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { | |
1546 | DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); | |
1547 | } | |
1548 | for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) { | |
1549 | pi->sys_info.csr_m3_arb_cntl_default[i] = | |
1550 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]); | |
1551 | pi->sys_info.csr_m3_arb_cntl_uvd[i] = | |
1552 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]); | |
1553 | pi->sys_info.csr_m3_arb_cntl_fs3d[i] = | |
1554 | le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]); | |
1555 | } | |
1556 | pi->sys_info.sclk_dpm_boost_margin = | |
1557 | le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin); | |
1558 | pi->sys_info.sclk_dpm_throttle_margin = | |
1559 | le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin); | |
1560 | pi->sys_info.sclk_dpm_tdp_limit_pg = | |
1561 | le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG); | |
1562 | pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit); | |
1563 | pi->sys_info.sclk_dpm_tdp_limit_boost = | |
1564 | le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost); | |
1565 | pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock); | |
1566 | pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit; | |
1567 | if (igp_info->info_6.EnableBoost) | |
1568 | pi->sys_info.enable_boost = true; | |
1569 | else | |
1570 | pi->sys_info.enable_boost = false; | |
1571 | sumo_construct_display_voltage_mapping_table(rdev, | |
d70229f7 | 1572 | &pi->sys_info.disp_clk_voltage_mapping_table, |
80ea2c12 AD |
1573 | igp_info->info_6.sDISPCLK_Voltage); |
1574 | sumo_construct_sclk_voltage_mapping_table(rdev, | |
d70229f7 | 1575 | &pi->sys_info.sclk_voltage_mapping_table, |
80ea2c12 | 1576 | igp_info->info_6.sAvail_SCLK); |
d70229f7 AD |
1577 | sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table, |
1578 | igp_info->info_6.sAvail_SCLK); | |
80ea2c12 AD |
1579 | |
1580 | } | |
1581 | return 0; | |
1582 | } | |
1583 | ||
1584 | static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev) | |
1585 | { | |
1586 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1587 | ||
1588 | pi->boot_pl.sclk = pi->sys_info.bootup_sclk; | |
1589 | pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; | |
1590 | pi->boot_pl.ds_divider_index = 0; | |
1591 | pi->boot_pl.ss_divider_index = 0; | |
1592 | pi->boot_pl.allow_gnb_slow = 1; | |
1593 | pi->acpi_pl = pi->boot_pl; | |
1594 | pi->current_ps.num_levels = 1; | |
1595 | pi->current_ps.levels[0] = pi->boot_pl; | |
1596 | } | |
1597 | ||
1598 | int sumo_dpm_init(struct radeon_device *rdev) | |
1599 | { | |
1600 | struct sumo_power_info *pi; | |
1601 | u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; | |
1602 | int ret; | |
1603 | ||
1604 | pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL); | |
1605 | if (pi == NULL) | |
1606 | return -ENOMEM; | |
1607 | rdev->pm.dpm.priv = pi; | |
1608 | ||
1609 | pi->driver_nbps_policy_disable = false; | |
1610 | if ((rdev->family == CHIP_PALM) && (hw_rev < 3)) | |
1611 | pi->disable_gfx_power_gating_in_uvd = true; | |
1612 | else | |
1613 | pi->disable_gfx_power_gating_in_uvd = false; | |
1614 | pi->enable_alt_vddnb = true; | |
1615 | pi->enable_sclk_ds = true; | |
1616 | pi->enable_dynamic_m3_arbiter = false; | |
1617 | pi->enable_dynamic_patch_ps = true; | |
1618 | pi->enable_gfx_power_gating = true; | |
1619 | pi->enable_gfx_clock_gating = true; | |
1620 | pi->enable_mg_clock_gating = true; | |
1621 | pi->enable_auto_thermal_throttling = true; | |
1622 | ||
1623 | ret = sumo_parse_sys_info_table(rdev); | |
1624 | if (ret) | |
1625 | return ret; | |
1626 | ||
1627 | sumo_construct_boot_and_acpi_state(rdev); | |
1628 | ||
1629 | ret = sumo_parse_power_table(rdev); | |
1630 | if (ret) | |
1631 | return ret; | |
1632 | ||
1633 | pi->pasi = CYPRESS_HASI_DFLT; | |
1634 | pi->asi = RV770_ASI_DFLT; | |
1635 | pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt; | |
1636 | pi->enable_boost = pi->sys_info.enable_boost; | |
1637 | pi->enable_dpm = true; | |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
1642 | void sumo_dpm_print_power_state(struct radeon_device *rdev, | |
1643 | struct radeon_ps *rps) | |
1644 | { | |
1645 | int i; | |
1646 | struct sumo_ps *ps = sumo_get_ps(rps); | |
1647 | ||
1648 | r600_dpm_print_class_info(rps->class, rps->class2); | |
1649 | r600_dpm_print_cap_info(rps->caps); | |
1650 | printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); | |
1651 | for (i = 0; i < ps->num_levels; i++) { | |
1652 | struct sumo_pl *pl = &ps->levels[i]; | |
1653 | printk("\t\tpower level %d sclk: %u vddc: %u\n", | |
1654 | i, pl->sclk, | |
1655 | sumo_convert_voltage_index_to_value(rdev, pl->vddc_index)); | |
1656 | } | |
1657 | r600_dpm_print_ps_status(rdev, rps); | |
1658 | } | |
1659 | ||
1660 | void sumo_dpm_fini(struct radeon_device *rdev) | |
1661 | { | |
1662 | int i; | |
1663 | ||
1664 | sumo_cleanup_asic(rdev); /* ??? */ | |
1665 | ||
1666 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { | |
1667 | kfree(rdev->pm.dpm.ps[i].ps_priv); | |
1668 | } | |
1669 | kfree(rdev->pm.dpm.ps); | |
1670 | kfree(rdev->pm.dpm.priv); | |
1671 | } | |
1672 | ||
1673 | u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low) | |
1674 | { | |
1675 | struct sumo_ps *requested_state = sumo_get_ps(rdev->pm.dpm.requested_ps); | |
1676 | ||
1677 | if (low) | |
1678 | return requested_state->levels[0].sclk; | |
1679 | else | |
1680 | return requested_state->levels[requested_state->num_levels - 1].sclk; | |
1681 | } | |
1682 | ||
1683 | u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low) | |
1684 | { | |
1685 | struct sumo_power_info *pi = sumo_get_pi(rdev); | |
1686 | ||
1687 | return pi->sys_info.bootup_uma_clk; | |
1688 | } |