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cb2025d2 LP |
1 | /* |
2 | * rcar_du_group.c -- R-Car Display Unit Channels Pair | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Corporation | |
5 | * | |
6 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | /* | |
15 | * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending | |
16 | * unit, timings generator, ...) and device-global resources (start/stop | |
17 | * control, planes, ...) shared between the two CRTCs. | |
18 | * | |
19 | * The R8A7790 introduced a third CRTC with its own set of global resources. | |
20 | * This would be modeled as two separate DU device instances if it wasn't for | |
21 | * a handful or resources that are shared between the three CRTCs (mostly | |
22 | * related to input and output routing). For this reason the R8A7790 DU must be | |
23 | * modeled as a single device with three CRTCs, two sets of "semi-global" | |
24 | * resources, and a few device-global resources. | |
25 | * | |
26 | * The rcar_du_group object is a driver specific object, without any real | |
27 | * counterpart in the DU documentation, that models those semi-global resources. | |
28 | */ | |
29 | ||
30 | #include <linux/io.h> | |
31 | ||
32 | #include "rcar_du_drv.h" | |
33 | #include "rcar_du_group.h" | |
34 | #include "rcar_du_regs.h" | |
35 | ||
a5f0ef59 | 36 | u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg) |
cb2025d2 LP |
37 | { |
38 | return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); | |
39 | } | |
40 | ||
a5f0ef59 | 41 | void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data) |
cb2025d2 LP |
42 | { |
43 | rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); | |
44 | } | |
45 | ||
46 | static void rcar_du_group_setup(struct rcar_du_group *rgrp) | |
47 | { | |
48 | /* Enable extended features */ | |
49 | rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE); | |
50 | rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G); | |
51 | rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3); | |
52 | rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE); | |
53 | rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); | |
38b62fb3 LP |
54 | if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_DEFR8)) |
55 | rcar_du_group_write(rgrp, DEFR8, DEFR8_CODE | DEFR8_DEFE8); | |
cb2025d2 LP |
56 | |
57 | /* Use DS1PR and DS2PR to configure planes priorities and connects the | |
58 | * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. | |
59 | */ | |
60 | rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); | |
61 | } | |
62 | ||
63 | /* | |
64 | * rcar_du_group_get - Acquire a reference to the DU channels group | |
65 | * | |
66 | * Acquiring the first reference setups core registers. A reference must be held | |
67 | * before accessing any hardware registers. | |
68 | * | |
69 | * This function must be called with the DRM mode_config lock held. | |
70 | * | |
71 | * Return 0 in case of success or a negative error code otherwise. | |
72 | */ | |
73 | int rcar_du_group_get(struct rcar_du_group *rgrp) | |
74 | { | |
75 | if (rgrp->use_count) | |
76 | goto done; | |
77 | ||
78 | rcar_du_group_setup(rgrp); | |
79 | ||
80 | done: | |
81 | rgrp->use_count++; | |
82 | return 0; | |
83 | } | |
84 | ||
85 | /* | |
86 | * rcar_du_group_put - Release a reference to the DU | |
87 | * | |
88 | * This function must be called with the DRM mode_config lock held. | |
89 | */ | |
90 | void rcar_du_group_put(struct rcar_du_group *rgrp) | |
91 | { | |
92 | --rgrp->use_count; | |
93 | } | |
94 | ||
95 | static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) | |
96 | { | |
97 | rcar_du_group_write(rgrp, DSYSR, | |
98 | (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) | | |
99 | (start ? DSYSR_DEN : DSYSR_DRES)); | |
100 | } | |
101 | ||
102 | void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) | |
103 | { | |
104 | /* Many of the configuration bits are only updated when the display | |
105 | * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some | |
106 | * of those bits could be pre-configured, but others (especially the | |
107 | * bits related to plane assignment to display timing controllers) need | |
108 | * to be modified at runtime. | |
109 | * | |
110 | * Restart the display controller if a start is requested. Sorry for the | |
111 | * flicker. It should be possible to move most of the "DRES-update" bits | |
112 | * setup to driver initialization time and minimize the number of cases | |
113 | * when the display controller will have to be restarted. | |
114 | */ | |
115 | if (start) { | |
116 | if (rgrp->used_crtcs++ != 0) | |
117 | __rcar_du_group_start_stop(rgrp, false); | |
118 | __rcar_du_group_start_stop(rgrp, true); | |
119 | } else { | |
120 | if (--rgrp->used_crtcs == 0) | |
121 | __rcar_du_group_start_stop(rgrp, false); | |
122 | } | |
123 | } | |
124 | ||
125 | void rcar_du_group_restart(struct rcar_du_group *rgrp) | |
126 | { | |
127 | __rcar_du_group_start_stop(rgrp, false); | |
128 | __rcar_du_group_start_stop(rgrp, true); | |
129 | } | |
2fd22dba LP |
130 | |
131 | void rcar_du_group_set_routing(struct rcar_du_group *rgrp) | |
132 | { | |
133 | struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2]; | |
134 | u32 dorcr = rcar_du_group_read(rgrp, DORCR); | |
135 | ||
136 | dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK); | |
137 | ||
138 | /* Set the DU1 pins sources. Select CRTC 0 if explicitly requested and | |
139 | * CRTC 1 in all other cases to avoid cloning CRTC 0 to DU0 and DU1 by | |
140 | * default. | |
141 | */ | |
142 | if (crtc0->outputs & (1 << 1)) | |
143 | dorcr |= DORCR_PG2D_DS1; | |
144 | else | |
145 | dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2; | |
146 | ||
147 | rcar_du_group_write(rgrp, DORCR, dorcr); | |
148 | } |