[deliverable/linux.git] / drivers / gpu / drm / rcar-du / rcar_du_group.c

/*
 * rcar_du_group.c  --  R-Car Display Unit Channels Pair
 *
 * Copyright (C) 2013-2014 Renesas Electronics Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

/*
 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
 * unit, timings generator, ...) and device-global resources (start/stop
 * control, planes, ...) shared between the two CRTCs.
 *
 * The R8A7790 introduced a third CRTC with its own set of global resources.
 * This would be modeled as two separate DU device instances if it wasn't for
 * a handful or resources that are shared between the three CRTCs (mostly
 * related to input and output routing). For this reason the R8A7790 DU must be
 * modeled as a single device with three CRTCs, two sets of "semi-global"
 * resources, and a few device-global resources.
 *
 * The rcar_du_group object is a driver specific object, without any real
 * counterpart in the DU documentation, that models those semi-global resources.
 */

#include <linux/clk.h>
#include <linux/io.h>

#include "rcar_du_drv.h"
#include "rcar_du_group.h"
#include "rcar_du_regs.h"

u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
{
	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
}

void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
{
	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
}

static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
{
	u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;

	/* The DEFR8 register for the first group also controls RGB output
	 * routing to DPAD0 and VSPD1 routing to DU0/1/2 for DU instances that
	 * support it.
	 */
	if (rgrp->index == 0) {
		if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1)
			defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
		if (rgrp->dev->vspd1_sink == 2)
			defr8 |= DEFR8_VSCS;
	}

	rcar_du_group_write(rgrp, DEFR8, defr8);
}

static void rcar_du_group_setup(struct rcar_du_group *rgrp)
{
	/* Enable extended features */
	rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
	rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
	rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
	rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
	rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);

	if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
		rcar_du_group_setup_defr8(rgrp);

		/* Configure input dot clock routing. We currently hardcode the
		 * configuration to routing DOTCLKINn to DUn.
		 */
		rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE |
				    DIDSR_LCDS_DCLKIN(2) |
				    DIDSR_LCDS_DCLKIN(1) |
				    DIDSR_LCDS_DCLKIN(0) |
				    DIDSR_PDCS_CLK(2, 0) |
				    DIDSR_PDCS_CLK(1, 0) |
				    DIDSR_PDCS_CLK(0, 0));
	}

	/* Use DS1PR and DS2PR to configure planes priorities and connects the
	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
	 */
	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);

	/* Apply planes to CRTCs association. */
	mutex_lock(&rgrp->lock);
	rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
			    rgrp->dptsr_planes);
	mutex_unlock(&rgrp->lock);
}

/*
 * rcar_du_group_get - Acquire a reference to the DU channels group
 *
 * Acquiring the first reference setups core registers. A reference must be held
 * before accessing any hardware registers.
 *
 * This function must be called with the DRM mode_config lock held.
 *
 * Return 0 in case of success or a negative error code otherwise.
 */
int rcar_du_group_get(struct rcar_du_group *rgrp)
{
	if (rgrp->use_count)
		goto done;

	rcar_du_group_setup(rgrp);

done:
	rgrp->use_count++;
	return 0;
}

/*
 * rcar_du_group_put - Release a reference to the DU
 *
 * This function must be called with the DRM mode_config lock held.
 */
void rcar_du_group_put(struct rcar_du_group *rgrp)
{
	--rgrp->use_count;
}

static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
	rcar_du_group_write(rgrp, DSYSR,
		(rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
		(start ? DSYSR_DEN : DSYSR_DRES));
}

void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
	/* Many of the configuration bits are only updated when the display
	 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
	 * of those bits could be pre-configured, but others (especially the
	 * bits related to plane assignment to display timing controllers) need
	 * to be modified at runtime.
	 *
	 * Restart the display controller if a start is requested. Sorry for the
	 * flicker. It should be possible to move most of the "DRES-update" bits
	 * setup to driver initialization time and minimize the number of cases
	 * when the display controller will have to be restarted.
	 */
	if (start) {
		if (rgrp->used_crtcs++ != 0)
			__rcar_du_group_start_stop(rgrp, false);
		__rcar_du_group_start_stop(rgrp, true);
	} else {
		if (--rgrp->used_crtcs == 0)
			__rcar_du_group_start_stop(rgrp, false);
	}
}

void rcar_du_group_restart(struct rcar_du_group *rgrp)
{
	rgrp->need_restart = false;

	__rcar_du_group_start_stop(rgrp, false);
	__rcar_du_group_start_stop(rgrp, true);
}

int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
{
	int ret;

	if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
		return 0;

	/* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
	 * configured in the DEFR8 register of the first group. As this function
	 * can be called with the DU0 and DU1 CRTCs disabled, we need to enable
	 * the first group clock before accessing the register.
	 */
	ret = clk_prepare_enable(rcdu->crtcs[0].clock);
	if (ret < 0)
		return ret;

	rcar_du_group_setup_defr8(&rcdu->groups[0]);

	clk_disable_unprepare(rcdu->crtcs[0].clock);

	return 0;
}

int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
{
	struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
	u32 dorcr = rcar_du_group_read(rgrp, DORCR);

	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);

	/* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
	 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
	 * by default.
	 */
	if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
		dorcr |= DORCR_PG2D_DS1;
	else
		dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;

	rcar_du_group_write(rgrp, DORCR, dorcr);

	return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
}
Commit	Line	Data
cb2025d2 LP	1	/*
	2	* rcar_du_group.c -- R-Car Display Unit Channels Pair
	3	*
36d50464	4	* Copyright (C) 2013-2014 Renesas Electronics Corporation
cb2025d2 LP	5	*
	6	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	/*
	15	* The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
	16	* unit, timings generator, ...) and device-global resources (start/stop
	17	* control, planes, ...) shared between the two CRTCs.
	18	*
	19	* The R8A7790 introduced a third CRTC with its own set of global resources.
	20	* This would be modeled as two separate DU device instances if it wasn't for
	21	* a handful or resources that are shared between the three CRTCs (mostly
	22	* related to input and output routing). For this reason the R8A7790 DU must be
	23	* modeled as a single device with three CRTCs, two sets of "semi-global"
	24	* resources, and a few device-global resources.
	25	*
	26	* The rcar_du_group object is a driver specific object, without any real
	27	* counterpart in the DU documentation, that models those semi-global resources.
	28	*/
	29
7cbc05cb	30	#include <linux/clk.h>
cb2025d2 LP	31	#include <linux/io.h>
	32
	33	#include "rcar_du_drv.h"
	34	#include "rcar_du_group.h"
	35	#include "rcar_du_regs.h"
	36
a5f0ef59	37	u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
cb2025d2 LP	38	{
	39	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
	40	}
	41
a5f0ef59	42	void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
cb2025d2 LP	43	{
	44	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
	45	}
	46
7cbc05cb LP	47	static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
	48	{
	49	u32 defr8 = DEFR8_CODE \| DEFR8_DEFE8;
	50
7cbc05cb	51	/* The DEFR8 register for the first group also controls RGB output
34a04f2b LP	52	* routing to DPAD0 and VSPD1 routing to DU0/1/2 for DU instances that
34a04f2b LP	53	* support it.
7cbc05cb	54	*/
34a04f2b LP	55	if (rgrp->index == 0) {
	56	if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1)
	57	defr8 \|= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
	58	if (rgrp->dev->vspd1_sink == 2)
	59	defr8 \|= DEFR8_VSCS;
	60	}
7cbc05cb LP	61
	62	rcar_du_group_write(rgrp, DEFR8, defr8);
	63	}
	64
cb2025d2 LP	65	static void rcar_du_group_setup(struct rcar_du_group *rgrp)
	66	{
	67	/* Enable extended features */
	68	rcar_du_group_write(rgrp, DEFR, DEFR_CODE \| DEFR_DEFE);
	69	rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE \| DEFR2_DEFE2G);
	70	rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE \| DEFR3_DEFE3);
	71	rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
	72	rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE \| DEFR5_DEFE5);
7cbc05cb	73
1b30dbde	74	if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
0c1c8776	75	rcar_du_group_setup_defr8(rgrp);
cb2025d2	76
1b30dbde LP	77	/* Configure input dot clock routing. We currently hardcode the
	78	* configuration to routing DOTCLKINn to DUn.
	79	*/
	80	rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE \|
	81	DIDSR_LCDS_DCLKIN(2) \|
	82	DIDSR_LCDS_DCLKIN(1) \|
	83	DIDSR_LCDS_DCLKIN(0) \|
	84	DIDSR_PDCS_CLK(2, 0) \|
	85	DIDSR_PDCS_CLK(1, 0) \|
	86	DIDSR_PDCS_CLK(0, 0));
	87	}
	88
cb2025d2 LP	89	/* Use DS1PR and DS2PR to configure planes priorities and connects the
	90	* superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
	91	*/
	92	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 \| DORCR_DPRS);
2a57e9b5 LP	93
	94	/* Apply planes to CRTCs association. */
	95	mutex_lock(&rgrp->lock);
	96	rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) \|
	97	rgrp->dptsr_planes);
	98	mutex_unlock(&rgrp->lock);
cb2025d2 LP	99	}
	100
	101	/*
	102	* rcar_du_group_get - Acquire a reference to the DU channels group
	103	*
	104	* Acquiring the first reference setups core registers. A reference must be held
	105	* before accessing any hardware registers.
	106	*
	107	* This function must be called with the DRM mode_config lock held.
	108	*
	109	* Return 0 in case of success or a negative error code otherwise.
	110	*/
	111	int rcar_du_group_get(struct rcar_du_group *rgrp)
	112	{
	113	if (rgrp->use_count)
	114	goto done;
	115
	116	rcar_du_group_setup(rgrp);
	117
	118	done:
	119	rgrp->use_count++;
	120	return 0;
	121	}
	122
	123	/*
	124	* rcar_du_group_put - Release a reference to the DU
	125	*
	126	* This function must be called with the DRM mode_config lock held.
	127	*/
	128	void rcar_du_group_put(struct rcar_du_group *rgrp)
	129	{
	130	--rgrp->use_count;
	131	}
	132
	133	static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
	134	{
	135	rcar_du_group_write(rgrp, DSYSR,
	136	(rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES \| DSYSR_DEN)) \|
	137	(start ? DSYSR_DEN : DSYSR_DRES));
	138	}
	139
	140	void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
	141	{
	142	/* Many of the configuration bits are only updated when the display
	143	* reset (DRES) bit in DSYSR is set to 1, disabling both CRTCs. Some
	144	* of those bits could be pre-configured, but others (especially the
	145	* bits related to plane assignment to display timing controllers) need
	146	* to be modified at runtime.
	147	*
	148	* Restart the display controller if a start is requested. Sorry for the
	149	* flicker. It should be possible to move most of the "DRES-update" bits
	150	* setup to driver initialization time and minimize the number of cases
	151	* when the display controller will have to be restarted.
	152	*/
	153	if (start) {
	154	if (rgrp->used_crtcs++ != 0)
	155	__rcar_du_group_start_stop(rgrp, false);
	156	__rcar_du_group_start_stop(rgrp, true);
	157	} else {
	158	if (--rgrp->used_crtcs == 0)
	159	__rcar_du_group_start_stop(rgrp, false);
	160	}
	161	}
	162
163	void rcar_du_group_restart(struct rcar_du_group *rgrp)
164	{
2af03944 LP	165	rgrp->need_restart = false;
2af03944 LP	166
cb2025d2 LP	167	__rcar_du_group_start_stop(rgrp, false);
	168	__rcar_du_group_start_stop(rgrp, true);
	169	}
2fd22dba	170
34a04f2b	171	int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
7cbc05cb LP	172	{
	173	int ret;
	174
0c1c8776 LP	175	if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
	176	return 0;
	177
34a04f2b LP	178	/* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
	179	* configured in the DEFR8 register of the first group. As this function
	180	* can be called with the DU0 and DU1 CRTCs disabled, we need to enable
	181	* the first group clock before accessing the register.
7cbc05cb LP	182	*/
	183	ret = clk_prepare_enable(rcdu->crtcs[0].clock);
	184	if (ret < 0)
	185	return ret;
	186
	187	rcar_du_group_setup_defr8(&rcdu->groups[0]);
	188
	189	clk_disable_unprepare(rcdu->crtcs[0].clock);
	190
	191	return 0;
	192	}
	193
	194	int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
2fd22dba LP	195	{
	196	struct rcar_du_crtc crtc0 = &rgrp->dev->crtcs[rgrp->index 2];
	197	u32 dorcr = rcar_du_group_read(rgrp, DORCR);
	198
	199	dorcr &= ~(DORCR_PG2T \| DORCR_DK2S \| DORCR_PG2D_MASK);
	200
ef67a902 LP	201	/* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
	202	* CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
	203	* by default.
2fd22dba	204	*/
ef67a902	205	if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
2fd22dba LP	206	dorcr \|= DORCR_PG2D_DS1;
	207	else
	208	dorcr \|= DORCR_PG2T \| DORCR_DK2S \| DORCR_PG2D_DS2;
	209
	210	rcar_du_group_write(rgrp, DORCR, dorcr);
7cbc05cb	211
34a04f2b	212	return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
2fd22dba	213	}