[deliverable/linux.git] / drivers / gpu / drm / rcar-du / rcar_du_regs.h

/*
 * rcar_du_regs.h  --  R-Car Display Unit Registers Definitions
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 */

#ifndef __RCAR_DU_REGS_H__
#define __RCAR_DU_REGS_H__

#define DU0_REG_OFFSET		0x00000
#define DU1_REG_OFFSET		0x30000
#define DU2_REG_OFFSET		0x40000
#define DU3_REG_OFFSET		0x70000

/* -----------------------------------------------------------------------------
 * Display Control Registers
 */

#define DSYSR			0x00000	/* display 1 */
#define DSYSR_ILTS		(1 << 29)
#define DSYSR_DSEC		(1 << 20)
#define DSYSR_IUPD		(1 << 16)
#define DSYSR_DRES		(1 << 9)
#define DSYSR_DEN		(1 << 8)
#define DSYSR_TVM_MASTER	(0 << 6)
#define DSYSR_TVM_SWITCH	(1 << 6)
#define DSYSR_TVM_TVSYNC	(2 << 6)
#define DSYSR_TVM_MASK		(3 << 6)
#define DSYSR_SCM_INT_NONE	(0 << 4)
#define DSYSR_SCM_INT_SYNC	(2 << 4)
#define DSYSR_SCM_INT_VIDEO	(3 << 4)
#define DSYSR_SCM_MASK		(3 << 4)

#define DSMR			0x00004
#define DSMR_VSPM		(1 << 28)
#define DSMR_ODPM		(1 << 27)
#define DSMR_DIPM_DISP		(0 << 25)
#define DSMR_DIPM_CSYNC		(1 << 25)
#define DSMR_DIPM_DE		(3 << 25)
#define DSMR_DIPM_MASK		(3 << 25)
#define DSMR_CSPM		(1 << 24)
#define DSMR_DIL		(1 << 19)
#define DSMR_VSL		(1 << 18)
#define DSMR_HSL		(1 << 17)
#define DSMR_DDIS		(1 << 16)
#define DSMR_CDEL		(1 << 15)
#define DSMR_CDEM_CDE		(0 << 13)
#define DSMR_CDEM_LOW		(2 << 13)
#define DSMR_CDEM_HIGH		(3 << 13)
#define DSMR_CDEM_MASK		(3 << 13)
#define DSMR_CDED		(1 << 12)
#define DSMR_ODEV		(1 << 8)
#define DSMR_CSY_VH_OR		(0 << 6)
#define DSMR_CSY_333		(2 << 6)
#define DSMR_CSY_222		(3 << 6)
#define DSMR_CSY_MASK		(3 << 6)

#define DSSR			0x00008
#define DSSR_VC1FB_DSA0		(0 << 30)
#define DSSR_VC1FB_DSA1		(1 << 30)
#define DSSR_VC1FB_DSA2		(2 << 30)
#define DSSR_VC1FB_INIT		(3 << 30)
#define DSSR_VC1FB_MASK		(3 << 30)
#define DSSR_VC0FB_DSA0		(0 << 28)
#define DSSR_VC0FB_DSA1		(1 << 28)
#define DSSR_VC0FB_DSA2		(2 << 28)
#define DSSR_VC0FB_INIT		(3 << 28)
#define DSSR_VC0FB_MASK		(3 << 28)
#define DSSR_DFB(n)		(1 << ((n)+15))
#define DSSR_TVR		(1 << 15)
#define DSSR_FRM		(1 << 14)
#define DSSR_VBK		(1 << 11)
#define DSSR_RINT		(1 << 9)
#define DSSR_HBK		(1 << 8)
#define DSSR_ADC(n)		(1 << ((n)-1))

#define DSRCR			0x0000c
#define DSRCR_TVCL		(1 << 15)
#define DSRCR_FRCL		(1 << 14)
#define DSRCR_VBCL		(1 << 11)
#define DSRCR_RICL		(1 << 9)
#define DSRCR_HBCL		(1 << 8)
#define DSRCR_ADCL(n)		(1 << ((n)-1))
#define DSRCR_MASK		0x0000cbff

#define DIER			0x00010
#define DIER_TVE		(1 << 15)
#define DIER_FRE		(1 << 14)
#define DIER_VBE		(1 << 11)
#define DIER_RIE		(1 << 9)
#define DIER_HBE		(1 << 8)
#define DIER_ADCE(n)		(1 << ((n)-1))

#define CPCR			0x00014
#define CPCR_CP4CE		(1 << 19)
#define CPCR_CP3CE		(1 << 18)
#define CPCR_CP2CE		(1 << 17)
#define CPCR_CP1CE		(1 << 16)

#define DPPR			0x00018
#define DPPR_DPE(n)		(1 << ((n)*4-1))
#define DPPR_DPS(n, p)		(((p)-1) << DPPR_DPS_SHIFT(n))
#define DPPR_DPS_SHIFT(n)	(((n)-1)*4)
#define DPPR_BPP16		(DPPR_DPE(8) | DPPR_DPS(8, 1))	/* plane1 */
#define DPPR_BPP32_P1		(DPPR_DPE(7) | DPPR_DPS(7, 1))
#define DPPR_BPP32_P2		(DPPR_DPE(8) | DPPR_DPS(8, 2))
#define DPPR_BPP32		(DPPR_BPP32_P1 | DPPR_BPP32_P2)	/* plane1 & 2 */

#define DEFR			0x00020
#define DEFR_CODE		(0x7773 << 16)
#define DEFR_EXSL		(1 << 12)
#define DEFR_EXVL		(1 << 11)
#define DEFR_EXUP		(1 << 5)
#define DEFR_VCUP		(1 << 4)
#define DEFR_DEFE		(1 << 0)

#define DAPCR			0x00024
#define DAPCR_CODE		(0x7773 << 16)
#define DAPCR_AP2E		(1 << 4)
#define DAPCR_AP1E		(1 << 0)

#define DCPCR			0x00028
#define DCPCR_CODE		(0x7773 << 16)
#define DCPCR_CA2B		(1 << 13)
#define DCPCR_CD2F		(1 << 12)
#define DCPCR_DC2E		(1 << 8)
#define DCPCR_CAB		(1 << 5)
#define DCPCR_CDF		(1 << 4)
#define DCPCR_DCE		(1 << 0)

#define DEFR2			0x00034
#define DEFR2_CODE		(0x7775 << 16)
#define DEFR2_DEFE2G		(1 << 0)

#define DEFR3			0x00038
#define DEFR3_CODE		(0x7776 << 16)
#define DEFR3_EVDA		(1 << 14)
#define DEFR3_EVDM_1		(1 << 12)
#define DEFR3_EVDM_2		(2 << 12)
#define DEFR3_EVDM_3		(3 << 12)
#define DEFR3_VMSM2_EMA		(1 << 6)
#define DEFR3_VMSM1_ENA		(1 << 4)
#define DEFR3_DEFE3		(1 << 0)

#define DEFR4			0x0003c
#define DEFR4_CODE		(0x7777 << 16)
#define DEFR4_LRUO		(1 << 5)
#define DEFR4_SPCE		(1 << 4)

#define DVCSR			0x000d0
#define DVCSR_VCnFB2_DSA0(n)	(0 << ((n)*2+16))
#define DVCSR_VCnFB2_DSA1(n)	(1 << ((n)*2+16))
#define DVCSR_VCnFB2_DSA2(n)	(2 << ((n)*2+16))
#define DVCSR_VCnFB2_INIT(n)	(3 << ((n)*2+16))
#define DVCSR_VCnFB2_MASK(n)	(3 << ((n)*2+16))
#define DVCSR_VCnFB_DSA0(n)	(0 << ((n)*2))
#define DVCSR_VCnFB_DSA1(n)	(1 << ((n)*2))
#define DVCSR_VCnFB_DSA2(n)	(2 << ((n)*2))
#define DVCSR_VCnFB_INIT(n)	(3 << ((n)*2))
#define DVCSR_VCnFB_MASK(n)	(3 << ((n)*2))

#define DEFR5			0x000e0
#define DEFR5_CODE		(0x66 << 24)
#define DEFR5_YCRGB2_DIS	(0 << 14)
#define DEFR5_YCRGB2_PRI1	(1 << 14)
#define DEFR5_YCRGB2_PRI2	(2 << 14)
#define DEFR5_YCRGB2_PRI3	(3 << 14)
#define DEFR5_YCRGB2_MASK	(3 << 14)
#define DEFR5_YCRGB1_DIS	(0 << 12)
#define DEFR5_YCRGB1_PRI1	(1 << 12)
#define DEFR5_YCRGB1_PRI2	(2 << 12)
#define DEFR5_YCRGB1_PRI3	(3 << 12)
#define DEFR5_YCRGB1_MASK	(3 << 12)
#define DEFR5_DEFE5		(1 << 0)

#define DDLTR			0x000e4
#define DDLTR_CODE		(0x7766 << 16)
#define DDLTR_DLAR2		(1 << 6)
#define DDLTR_DLAY2		(1 << 5)
#define DDLTR_DLAY1		(1 << 1)

#define DEFR6			0x000e8
#define DEFR6_CODE		(0x7778 << 16)
#define DEFR6_ODPM22_D2SMR	(0 << 10)
#define DEFR6_ODPM22_DISP	(2 << 10)
#define DEFR6_ODPM22_CDE	(3 << 10)
#define DEFR6_ODPM22_MASK	(3 << 10)
#define DEFR6_ODPM12_DSMR	(0 << 8)
#define DEFR6_ODPM12_DISP	(2 << 8)
#define DEFR6_ODPM12_CDE	(3 << 8)
#define DEFR6_ODPM12_MASK	(3 << 8)
#define DEFR6_TCNE2		(1 << 6)
#define DEFR6_MLOS1		(1 << 2)
#define DEFR6_DEFAULT		(DEFR6_CODE | DEFR6_TCNE2)

/* -----------------------------------------------------------------------------
 * R8A7790-only Control Registers
 */

#define DD1SSR			0x20008
#define DD1SSR_TVR		(1 << 15)
#define DD1SSR_FRM		(1 << 14)
#define DD1SSR_BUF		(1 << 12)
#define DD1SSR_VBK		(1 << 11)
#define DD1SSR_RINT		(1 << 9)
#define DD1SSR_HBK		(1 << 8)
#define DD1SSR_ADC(n)		(1 << ((n)-1))

#define DD1SRCR			0x2000c
#define DD1SRCR_TVR		(1 << 15)
#define DD1SRCR_FRM		(1 << 14)
#define DD1SRCR_BUF		(1 << 12)
#define DD1SRCR_VBK		(1 << 11)
#define DD1SRCR_RINT		(1 << 9)
#define DD1SRCR_HBK		(1 << 8)
#define DD1SRCR_ADC(n)		(1 << ((n)-1))

#define DD1IER			0x20010
#define DD1IER_TVR		(1 << 15)
#define DD1IER_FRM		(1 << 14)
#define DD1IER_BUF		(1 << 12)
#define DD1IER_VBK		(1 << 11)
#define DD1IER_RINT		(1 << 9)
#define DD1IER_HBK		(1 << 8)
#define DD1IER_ADC(n)		(1 << ((n)-1))

#define DEFR8			0x20020
#define DEFR8_CODE		(0x7790 << 16)
#define DEFR8_VSCS		(1 << 6)
#define DEFR8_DRGBS_DU(n)	((n) << 4)
#define DEFR8_DRGBS_MASK	(3 << 4)
#define DEFR8_DEFE8		(1 << 0)

#define DOFLR			0x20024
#define DOFLR_CODE		(0x7790 << 16)
#define DOFLR_HSYCFL1		(1 << 13)
#define DOFLR_VSYCFL1		(1 << 12)
#define DOFLR_ODDFL1		(1 << 11)
#define DOFLR_DISPFL1		(1 << 10)
#define DOFLR_CDEFL1		(1 << 9)
#define DOFLR_RGBFL1		(1 << 8)
#define DOFLR_HSYCFL0		(1 << 5)
#define DOFLR_VSYCFL0		(1 << 4)
#define DOFLR_ODDFL0		(1 << 3)
#define DOFLR_DISPFL0		(1 << 2)
#define DOFLR_CDEFL0		(1 << 1)
#define DOFLR_RGBFL0		(1 << 0)

#define DIDSR			0x20028
#define DIDSR_CODE		(0x7790 << 16)
#define DIDSR_LCDS_DCLKIN(n)	(0 << (8 + (n) * 2))
#define DIDSR_LCDS_LVDS0(n)	(2 << (8 + (n) * 2))
#define DIDSR_LCDS_LVDS1(n)	(3 << (8 + (n) * 2))
#define DIDSR_LCDS_MASK(n)	(3 << (8 + (n) * 2))
#define DIDSR_PDCS_CLK(n, clk)	(clk << ((n) * 2))
#define DIDSR_PDCS_MASK(n)	(3 << ((n) * 2))

/* -----------------------------------------------------------------------------
 * Display Timing Generation Registers
 */

#define HDSR			0x00040
#define HDER			0x00044
#define VDSR			0x00048
#define VDER			0x0004c
#define HCR			0x00050
#define HSWR			0x00054
#define VCR			0x00058
#define VSPR			0x0005c
#define EQWR			0x00060
#define SPWR			0x00064
#define CLAMPSR			0x00070
#define CLAMPWR			0x00074
#define DESR			0x00078
#define DEWR			0x0007c

/* -----------------------------------------------------------------------------
 * Display Attribute Registers
 */

#define CP1TR			0x00080
#define CP2TR			0x00084
#define CP3TR			0x00088
#define CP4TR			0x0008c

#define DOOR			0x00090
#define DOOR_RGB(r, g, b)	(((r) << 18) | ((g) << 10) | ((b) << 2))
#define CDER			0x00094
#define CDER_RGB(r, g, b)	(((r) << 18) | ((g) << 10) | ((b) << 2))
#define BPOR			0x00098
#define BPOR_RGB(r, g, b)	(((r) << 18) | ((g) << 10) | ((b) << 2))

#define RINTOFSR		0x0009c

#define DSHPR			0x000c8
#define DSHPR_CODE		(0x7776 << 16)
#define DSHPR_PRIH		(0xa << 4)
#define DSHPR_PRIL_BPP16	(0x8 << 0)
#define DSHPR_PRIL_BPP32	(0x9 << 0)

/* -----------------------------------------------------------------------------
 * Display Plane Registers
 */

#define PLANE_OFF		0x00100

#define PnMR			0x00100 /* plane 1 */
#define PnMR_VISL_VIN0		(0 << 26)	/* use Video Input 0 */
#define PnMR_VISL_VIN1		(1 << 26)	/* use Video Input 1 */
#define PnMR_VISL_VIN2		(2 << 26)	/* use Video Input 2 */
#define PnMR_VISL_VIN3		(3 << 26)	/* use Video Input 3 */
#define PnMR_YCDF_YUYV		(1 << 20)	/* YUYV format */
#define PnMR_TC_R		(0 << 17)	/* Tranparent color is PnTC1R */
#define PnMR_TC_CP		(1 << 17)	/* Tranparent color is color palette */
#define PnMR_WAE		(1 << 16)	/* Wrap around Enable */
#define PnMR_SPIM_TP		(0 << 12)	/* Transparent Color */
#define PnMR_SPIM_ALP		(1 << 12)	/* Alpha Blending */
#define PnMR_SPIM_EOR		(2 << 12)	/* EOR */
#define PnMR_SPIM_TP_OFF	(1 << 14)	/* No Transparent Color */
#define PnMR_CPSL_CP1		(0 << 8)	/* Color Palette selected 1 */
#define PnMR_CPSL_CP2		(1 << 8)	/* Color Palette selected 2 */
#define PnMR_CPSL_CP3		(2 << 8)	/* Color Palette selected 3 */
#define PnMR_CPSL_CP4		(3 << 8)	/* Color Palette selected 4 */
#define PnMR_DC			(1 << 7)	/* Display Area Change */
#define PnMR_BM_MD		(0 << 4)	/* Manual Display Change Mode */
#define PnMR_BM_AR		(1 << 4)	/* Auto Rendering Mode */
#define PnMR_BM_AD		(2 << 4)	/* Auto Display Change Mode */
#define PnMR_BM_VC		(3 << 4)	/* Video Capture Mode */
#define PnMR_DDDF_8BPP		(0 << 0)	/* 8bit */
#define PnMR_DDDF_16BPP		(1 << 0)	/* 16bit or 32bit */
#define PnMR_DDDF_ARGB		(2 << 0)	/* ARGB */
#define PnMR_DDDF_YC		(3 << 0)	/* YC */
#define PnMR_DDDF_MASK		(3 << 0)

#define PnMWR			0x00104

#define PnALPHAR		0x00108
#define PnALPHAR_ABIT_1		(0 << 12)
#define PnALPHAR_ABIT_0		(1 << 12)
#define PnALPHAR_ABIT_X		(2 << 12)

#define PnDSXR			0x00110
#define PnDSYR			0x00114
#define PnDPXR			0x00118
#define PnDPYR			0x0011c

#define PnDSA0R			0x00120
#define PnDSA1R			0x00124
#define PnDSA2R			0x00128
#define PnDSA_MASK		0xfffffff0

#define PnSPXR			0x00130
#define PnSPYR			0x00134
#define PnWASPR			0x00138
#define PnWAMWR			0x0013c

#define PnBTR			0x00140

#define PnTC1R			0x00144
#define PnTC2R			0x00148
#define PnTC3R			0x0014c
#define PnTC3R_CODE		(0x66 << 24)

#define PnMLR			0x00150

#define PnSWAPR			0x00180
#define PnSWAPR_DIGN		(1 << 4)
#define PnSWAPR_SPQW		(1 << 3)
#define PnSWAPR_SPLW		(1 << 2)
#define PnSWAPR_SPWD		(1 << 1)
#define PnSWAPR_SPBY		(1 << 0)

#define PnDDCR			0x00184
#define PnDDCR_CODE		(0x7775 << 16)
#define PnDDCR_LRGB1		(1 << 11)
#define PnDDCR_LRGB0		(1 << 10)

#define PnDDCR2			0x00188
#define PnDDCR2_CODE		(0x7776 << 16)
#define PnDDCR2_NV21		(1 << 5)
#define PnDDCR2_Y420		(1 << 4)
#define PnDDCR2_DIVU		(1 << 1)
#define PnDDCR2_DIVY		(1 << 0)

#define PnDDCR4			0x00190
#define PnDDCR4_CODE		(0x7766 << 16)
#define PnDDCR4_VSPS		(1 << 13)
#define PnDDCR4_SDFS_RGB	(0 << 4)
#define PnDDCR4_SDFS_YC		(5 << 4)
#define PnDDCR4_SDFS_MASK	(7 << 4)
#define PnDDCR4_EDF_NONE	(0 << 0)
#define PnDDCR4_EDF_ARGB8888	(1 << 0)
#define PnDDCR4_EDF_RGB888	(2 << 0)
#define PnDDCR4_EDF_RGB666	(3 << 0)
#define PnDDCR4_EDF_MASK	(7 << 0)

#define APnMR			0x0a100
#define APnMR_WAE		(1 << 16)	/* Wrap around Enable */
#define APnMR_DC		(1 << 7)	/* Display Area Change */
#define APnMR_BM_MD		(0 << 4)	/* Manual Display Change Mode */
#define APnMR_BM_AD		(2 << 4)	/* Auto Display Change Mode */

#define APnMWR			0x0a104

#define APnDSXR			0x0a110
#define APnDSYR			0x0a114
#define APnDPXR			0x0a118
#define APnDPYR			0x0a11c

#define APnDSA0R		0x0a120
#define APnDSA1R		0x0a124
#define APnDSA2R		0x0a128

#define APnSPXR			0x0a130
#define APnSPYR			0x0a134
#define APnWASPR		0x0a138
#define APnWAMWR		0x0a13c

#define APnBTR			0x0a140

#define APnMLR			0x0a150
#define APnSWAPR		0x0a180

/* -----------------------------------------------------------------------------
 * Display Capture Registers
 */

#define DCMR			0x0c100
#define DCMWR			0x0c104
#define DCSAR			0x0c120
#define DCMLR			0x0c150

/* -----------------------------------------------------------------------------
 * Color Palette Registers
 */

#define CP1_000R		0x01000
#define CP1_255R		0x013fc
#define CP2_000R		0x02000
#define CP2_255R		0x023fc
#define CP3_000R		0x03000
#define CP3_255R		0x033fc
#define CP4_000R		0x04000
#define CP4_255R		0x043fc

/* -----------------------------------------------------------------------------
 * External Synchronization Control Registers
 */

#define ESCR			0x10000
#define ESCR2			0x31000
#define ESCR_DCLKOINV		(1 << 25)
#define ESCR_DCLKSEL_DCLKIN	(0 << 20)
#define ESCR_DCLKSEL_CLKS	(1 << 20)
#define ESCR_DCLKSEL_MASK	(1 << 20)
#define ESCR_DCLKDIS		(1 << 16)
#define ESCR_SYNCSEL_OFF	(0 << 8)
#define ESCR_SYNCSEL_EXVSYNC	(2 << 8)
#define ESCR_SYNCSEL_EXHSYNC	(3 << 8)
#define ESCR_FRQSEL_MASK	(0x3f << 0)

#define OTAR			0x10004
#define OTAR2			0x31004

/* -----------------------------------------------------------------------------
 * Dual Display Output Control Registers
 */

#define DORCR			0x11000
#define DORCR_PG2T		(1 << 30)
#define DORCR_DK2S		(1 << 28)
#define DORCR_PG2D_DS1		(0 << 24)
#define DORCR_PG2D_DS2		(1 << 24)
#define DORCR_PG2D_FIX0		(2 << 24)
#define DORCR_PG2D_DOOR		(3 << 24)
#define DORCR_PG2D_MASK		(3 << 24)
#define DORCR_DR1D		(1 << 21)
#define DORCR_PG1D_DS1		(0 << 16)
#define DORCR_PG1D_DS2		(1 << 16)
#define DORCR_PG1D_FIX0		(2 << 16)
#define DORCR_PG1D_DOOR		(3 << 16)
#define DORCR_PG1D_MASK		(3 << 16)
#define DORCR_RGPV		(1 << 4)
#define DORCR_DPRS		(1 << 0)

#define DPTSR			0x11004
#define DPTSR_PnDK(n)		(1 << ((n) + 16))
#define DPTSR_PnTS(n)		(1 << (n))

#define DAPTSR			0x11008
#define DAPTSR_APnDK(n)		(1 << ((n) + 16))
#define DAPTSR_APnTS(n)		(1 << (n))

#define DS1PR			0x11020
#define DS2PR			0x11024

/* -----------------------------------------------------------------------------
 * YC-RGB Conversion Coefficient Registers
 */

#define YNCR			0x11080
#define YNOR			0x11084
#define CRNOR			0x11088
#define CBNOR			0x1108c
#define RCRCR			0x11090
#define GCRCR			0x11094
#define GCBCR			0x11098
#define BCBCR			0x1109c

#endif /* __RCAR_DU_REGS_H__ */
Commit	Line	Data
4bf8e196 LP	1	/*
	2	* rcar_du_regs.h -- R-Car Display Unit Registers Definitions
	3	*
	4	* Copyright (C) 2013 Renesas Electronics Corporation
	5	*
	6	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2
	10	* as published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __RCAR_DU_REGS_H__
	14	#define __RCAR_DU_REGS_H__
	15
a5f0ef59 LP	16	#define DU0_REG_OFFSET 0x00000
	17	#define DU1_REG_OFFSET 0x30000
	18	#define DU2_REG_OFFSET 0x40000
6a8c49fc	19	#define DU3_REG_OFFSET 0x70000
4bf8e196 LP	20
	21	/* -----------------------------------------------------------------------------
	22	* Display Control Registers
	23	*/
	24
	25	#define DSYSR 0x00000 /* display 1 */
4bf8e196 LP	26	#define DSYSR_ILTS (1 << 29)
	27	#define DSYSR_DSEC (1 << 20)
	28	#define DSYSR_IUPD (1 << 16)
	29	#define DSYSR_DRES (1 << 9)
	30	#define DSYSR_DEN (1 << 8)
	31	#define DSYSR_TVM_MASTER (0 << 6)
	32	#define DSYSR_TVM_SWITCH (1 << 6)
	33	#define DSYSR_TVM_TVSYNC (2 << 6)
	34	#define DSYSR_TVM_MASK (3 << 6)
	35	#define DSYSR_SCM_INT_NONE (0 << 4)
	36	#define DSYSR_SCM_INT_SYNC (2 << 4)
	37	#define DSYSR_SCM_INT_VIDEO (3 << 4)
906eff7f	38	#define DSYSR_SCM_MASK (3 << 4)
4bf8e196 LP	39
4bf8e196 LP	40	#define DSMR 0x00004
4bf8e196 LP	41	#define DSMR_VSPM (1 << 28)
	42	#define DSMR_ODPM (1 << 27)
	43	#define DSMR_DIPM_DISP (0 << 25)
	44	#define DSMR_DIPM_CSYNC (1 << 25)
	45	#define DSMR_DIPM_DE (3 << 25)
	46	#define DSMR_DIPM_MASK (3 << 25)
	47	#define DSMR_CSPM (1 << 24)
	48	#define DSMR_DIL (1 << 19)
	49	#define DSMR_VSL (1 << 18)
	50	#define DSMR_HSL (1 << 17)
	51	#define DSMR_DDIS (1 << 16)
	52	#define DSMR_CDEL (1 << 15)
	53	#define DSMR_CDEM_CDE (0 << 13)
	54	#define DSMR_CDEM_LOW (2 << 13)
	55	#define DSMR_CDEM_HIGH (3 << 13)
	56	#define DSMR_CDEM_MASK (3 << 13)
	57	#define DSMR_CDED (1 << 12)
	58	#define DSMR_ODEV (1 << 8)
	59	#define DSMR_CSY_VH_OR (0 << 6)
	60	#define DSMR_CSY_333 (2 << 6)
	61	#define DSMR_CSY_222 (3 << 6)
	62	#define DSMR_CSY_MASK (3 << 6)
	63
	64	#define DSSR 0x00008
4bf8e196 LP	65	#define DSSR_VC1FB_DSA0 (0 << 30)
	66	#define DSSR_VC1FB_DSA1 (1 << 30)
	67	#define DSSR_VC1FB_DSA2 (2 << 30)
	68	#define DSSR_VC1FB_INIT (3 << 30)
	69	#define DSSR_VC1FB_MASK (3 << 30)
	70	#define DSSR_VC0FB_DSA0 (0 << 28)
	71	#define DSSR_VC0FB_DSA1 (1 << 28)
	72	#define DSSR_VC0FB_DSA2 (2 << 28)
	73	#define DSSR_VC0FB_INIT (3 << 28)
	74	#define DSSR_VC0FB_MASK (3 << 28)
	75	#define DSSR_DFB(n) (1 << ((n)+15))
	76	#define DSSR_TVR (1 << 15)
	77	#define DSSR_FRM (1 << 14)
	78	#define DSSR_VBK (1 << 11)
	79	#define DSSR_RINT (1 << 9)
	80	#define DSSR_HBK (1 << 8)
	81	#define DSSR_ADC(n) (1 << ((n)-1))
	82
	83	#define DSRCR 0x0000c
4bf8e196 LP	84	#define DSRCR_TVCL (1 << 15)
	85	#define DSRCR_FRCL (1 << 14)
	86	#define DSRCR_VBCL (1 << 11)
	87	#define DSRCR_RICL (1 << 9)
	88	#define DSRCR_HBCL (1 << 8)
	89	#define DSRCR_ADCL(n) (1 << ((n)-1))
	90	#define DSRCR_MASK 0x0000cbff
	91
	92	#define DIER 0x00010
4bf8e196 LP	93	#define DIER_TVE (1 << 15)
	94	#define DIER_FRE (1 << 14)
	95	#define DIER_VBE (1 << 11)
	96	#define DIER_RIE (1 << 9)
	97	#define DIER_HBE (1 << 8)
	98	#define DIER_ADCE(n) (1 << ((n)-1))
	99
	100	#define CPCR 0x00014
	101	#define CPCR_CP4CE (1 << 19)
	102	#define CPCR_CP3CE (1 << 18)
	103	#define CPCR_CP2CE (1 << 17)
	104	#define CPCR_CP1CE (1 << 16)
	105
	106	#define DPPR 0x00018
	107	#define DPPR_DPE(n) (1 << ((n)*4-1))
	108	#define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n))
	109	#define DPPR_DPS_SHIFT(n) (((n)-1)*4)
	110	#define DPPR_BPP16 (DPPR_DPE(8) \| DPPR_DPS(8, 1)) /* plane1 */
	111	#define DPPR_BPP32_P1 (DPPR_DPE(7) \| DPPR_DPS(7, 1))
	112	#define DPPR_BPP32_P2 (DPPR_DPE(8) \| DPPR_DPS(8, 2))
	113	#define DPPR_BPP32 (DPPR_BPP32_P1 \| DPPR_BPP32_P2) /* plane1 & 2 */
	114
	115	#define DEFR 0x00020
4bf8e196 LP	116	#define DEFR_CODE (0x7773 << 16)
	117	#define DEFR_EXSL (1 << 12)
	118	#define DEFR_EXVL (1 << 11)
	119	#define DEFR_EXUP (1 << 5)
	120	#define DEFR_VCUP (1 << 4)
	121	#define DEFR_DEFE (1 << 0)
	122
	123	#define DAPCR 0x00024
	124	#define DAPCR_CODE (0x7773 << 16)
	125	#define DAPCR_AP2E (1 << 4)
	126	#define DAPCR_AP1E (1 << 0)
	127
	128	#define DCPCR 0x00028
	129	#define DCPCR_CODE (0x7773 << 16)
	130	#define DCPCR_CA2B (1 << 13)
	131	#define DCPCR_CD2F (1 << 12)
	132	#define DCPCR_DC2E (1 << 8)
	133	#define DCPCR_CAB (1 << 5)
	134	#define DCPCR_CDF (1 << 4)
	135	#define DCPCR_DCE (1 << 0)
	136
	137	#define DEFR2 0x00034
4bf8e196 LP	138	#define DEFR2_CODE (0x7775 << 16)
	139	#define DEFR2_DEFE2G (1 << 0)
	140
	141	#define DEFR3 0x00038
4bf8e196 LP	142	#define DEFR3_CODE (0x7776 << 16)
	143	#define DEFR3_EVDA (1 << 14)
	144	#define DEFR3_EVDM_1 (1 << 12)
	145	#define DEFR3_EVDM_2 (2 << 12)
	146	#define DEFR3_EVDM_3 (3 << 12)
	147	#define DEFR3_VMSM2_EMA (1 << 6)
	148	#define DEFR3_VMSM1_ENA (1 << 4)
	149	#define DEFR3_DEFE3 (1 << 0)
	150
	151	#define DEFR4 0x0003c
4bf8e196 LP	152	#define DEFR4_CODE (0x7777 << 16)
	153	#define DEFR4_LRUO (1 << 5)
	154	#define DEFR4_SPCE (1 << 4)
	155
	156	#define DVCSR 0x000d0
	157	#define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16))
	158	#define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16))
	159	#define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16))
	160	#define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16))
	161	#define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16))
	162	#define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2))
	163	#define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2))
	164	#define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2))
	165	#define DVCSR_VCnFB_INIT(n) (3 << ((n)*2))
	166	#define DVCSR_VCnFB_MASK(n) (3 << ((n)*2))
	167
	168	#define DEFR5 0x000e0
	169	#define DEFR5_CODE (0x66 << 24)
	170	#define DEFR5_YCRGB2_DIS (0 << 14)
	171	#define DEFR5_YCRGB2_PRI1 (1 << 14)
	172	#define DEFR5_YCRGB2_PRI2 (2 << 14)
	173	#define DEFR5_YCRGB2_PRI3 (3 << 14)
	174	#define DEFR5_YCRGB2_MASK (3 << 14)
	175	#define DEFR5_YCRGB1_DIS (0 << 12)
	176	#define DEFR5_YCRGB1_PRI1 (1 << 12)
	177	#define DEFR5_YCRGB1_PRI2 (2 << 12)
	178	#define DEFR5_YCRGB1_PRI3 (3 << 12)
	179	#define DEFR5_YCRGB1_MASK (3 << 12)
	180	#define DEFR5_DEFE5 (1 << 0)
	181
	182	#define DDLTR 0x000e4
	183	#define DDLTR_CODE (0x7766 << 16)
	184	#define DDLTR_DLAR2 (1 << 6)
	185	#define DDLTR_DLAY2 (1 << 5)
	186	#define DDLTR_DLAY1 (1 << 1)
	187
	188	#define DEFR6 0x000e8
	189	#define DEFR6_CODE (0x7778 << 16)
	190	#define DEFR6_ODPM22_D2SMR (0 << 10)
	191	#define DEFR6_ODPM22_DISP (2 << 10)
	192	#define DEFR6_ODPM22_CDE (3 << 10)
	193	#define DEFR6_ODPM22_MASK (3 << 10)
	194	#define DEFR6_ODPM12_DSMR (0 << 8)
	195	#define DEFR6_ODPM12_DISP (2 << 8)
	196	#define DEFR6_ODPM12_CDE (3 << 8)
	197	#define DEFR6_ODPM12_MASK (3 << 8)
	198	#define DEFR6_TCNE2 (1 << 6)
	199	#define DEFR6_MLOS1 (1 << 2)
	200	#define DEFR6_DEFAULT (DEFR6_CODE \| DEFR6_TCNE2)
	201
ef2d84be LP	202	/* -----------------------------------------------------------------------------
	203	* R8A7790-only Control Registers
	204	*/
	205
	206	#define DD1SSR 0x20008
	207	#define DD1SSR_TVR (1 << 15)
	208	#define DD1SSR_FRM (1 << 14)
	209	#define DD1SSR_BUF (1 << 12)
	210	#define DD1SSR_VBK (1 << 11)
	211	#define DD1SSR_RINT (1 << 9)
	212	#define DD1SSR_HBK (1 << 8)
	213	#define DD1SSR_ADC(n) (1 << ((n)-1))
	214
	215	#define DD1SRCR 0x2000c
	216	#define DD1SRCR_TVR (1 << 15)
	217	#define DD1SRCR_FRM (1 << 14)
	218	#define DD1SRCR_BUF (1 << 12)
	219	#define DD1SRCR_VBK (1 << 11)
	220	#define DD1SRCR_RINT (1 << 9)
	221	#define DD1SRCR_HBK (1 << 8)
	222	#define DD1SRCR_ADC(n) (1 << ((n)-1))
	223
	224	#define DD1IER 0x20010
	225	#define DD1IER_TVR (1 << 15)
	226	#define DD1IER_FRM (1 << 14)
	227	#define DD1IER_BUF (1 << 12)
	228	#define DD1IER_VBK (1 << 11)
	229	#define DD1IER_RINT (1 << 9)
	230	#define DD1IER_HBK (1 << 8)
	231	#define DD1IER_ADC(n) (1 << ((n)-1))
	232
	233	#define DEFR8 0x20020
	234	#define DEFR8_CODE (0x7790 << 16)
	235	#define DEFR8_VSCS (1 << 6)
	236	#define DEFR8_DRGBS_DU(n) ((n) << 4)
	237	#define DEFR8_DRGBS_MASK (3 << 4)
	238	#define DEFR8_DEFE8 (1 << 0)
	239
	240	#define DOFLR 0x20024
	241	#define DOFLR_CODE (0x7790 << 16)
	242	#define DOFLR_HSYCFL1 (1 << 13)
	243	#define DOFLR_VSYCFL1 (1 << 12)
	244	#define DOFLR_ODDFL1 (1 << 11)
	245	#define DOFLR_DISPFL1 (1 << 10)
	246	#define DOFLR_CDEFL1 (1 << 9)
	247	#define DOFLR_RGBFL1 (1 << 8)
	248	#define DOFLR_HSYCFL0 (1 << 5)
	249	#define DOFLR_VSYCFL0 (1 << 4)
	250	#define DOFLR_ODDFL0 (1 << 3)
	251	#define DOFLR_DISPFL0 (1 << 2)
	252	#define DOFLR_CDEFL0 (1 << 1)
	253	#define DOFLR_RGBFL0 (1 << 0)
	254
	255	#define DIDSR 0x20028
	256	#define DIDSR_CODE (0x7790 << 16)
	257	#define DIDSR_LCDS_DCLKIN(n) (0 << (8 + (n) * 2))
	258	#define DIDSR_LCDS_LVDS0(n) (2 << (8 + (n) * 2))
	259	#define DIDSR_LCDS_LVDS1(n) (3 << (8 + (n) * 2))
	260	#define DIDSR_LCDS_MASK(n) (3 << (8 + (n) * 2))
1b30dbde LP	261	#define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2))
1b30dbde LP	262	#define DIDSR_PDCS_MASK(n) (3 << ((n) * 2))
ef2d84be	263
4bf8e196 LP	264	/* -----------------------------------------------------------------------------
	265	* Display Timing Generation Registers
	266	*/
	267
	268	#define HDSR 0x00040
	269	#define HDER 0x00044
	270	#define VDSR 0x00048
	271	#define VDER 0x0004c
	272	#define HCR 0x00050
	273	#define HSWR 0x00054
	274	#define VCR 0x00058
	275	#define VSPR 0x0005c
	276	#define EQWR 0x00060
	277	#define SPWR 0x00064
	278	#define CLAMPSR 0x00070
	279	#define CLAMPWR 0x00074
	280	#define DESR 0x00078
	281	#define DEWR 0x0007c
	282
	283	/* -----------------------------------------------------------------------------
	284	* Display Attribute Registers
	285	*/
	286
	287	#define CP1TR 0x00080
	288	#define CP2TR 0x00084
	289	#define CP3TR 0x00088
	290	#define CP4TR 0x0008c
	291
	292	#define DOOR 0x00090
	293	#define DOOR_RGB(r, g, b) (((r) << 18) \| ((g) << 10) \| ((b) << 2))
	294	#define CDER 0x00094
	295	#define CDER_RGB(r, g, b) (((r) << 18) \| ((g) << 10) \| ((b) << 2))
	296	#define BPOR 0x00098
	297	#define BPOR_RGB(r, g, b) (((r) << 18) \| ((g) << 10) \| ((b) << 2))
	298
	299	#define RINTOFSR 0x0009c
	300
	301	#define DSHPR 0x000c8
	302	#define DSHPR_CODE (0x7776 << 16)
	303	#define DSHPR_PRIH (0xa << 4)
	304	#define DSHPR_PRIL_BPP16 (0x8 << 0)
	305	#define DSHPR_PRIL_BPP32 (0x9 << 0)
	306
	307	/* -----------------------------------------------------------------------------
	308	* Display Plane Registers
	309	*/
	310
	311	#define PLANE_OFF 0x00100
	312
	313	#define PnMR 0x00100 /* plane 1 */
	314	#define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */
	315	#define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */
	316	#define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */
	317	#define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */
	318	#define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */
	319	#define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */
	320	#define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */
	321	#define PnMR_WAE (1 << 16) /* Wrap around Enable */
	322	#define PnMR_SPIM_TP (0 << 12) /* Transparent Color */
	323	#define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */
	324	#define PnMR_SPIM_EOR (2 << 12) /* EOR */
	325	#define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */
	326	#define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */
	327	#define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */
328	#define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */
329	#define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */
330	#define PnMR_DC (1 << 7) /* Display Area Change */
331	#define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
332	#define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */
333	#define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */
334	#define PnMR_BM_VC (3 << 4) /* Video Capture Mode */
335	#define PnMR_DDDF_8BPP (0 << 0) /* 8bit */
336	#define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */
337	#define PnMR_DDDF_ARGB (2 << 0) /* ARGB */
338	#define PnMR_DDDF_YC (3 << 0) /* YC */
339	#define PnMR_DDDF_MASK (3 << 0)
340
341	#define PnMWR 0x00104
342
343	#define PnALPHAR 0x00108
344	#define PnALPHAR_ABIT_1 (0 << 12)
345	#define PnALPHAR_ABIT_0 (1 << 12)
346	#define PnALPHAR_ABIT_X (2 << 12)
347
348	#define PnDSXR 0x00110
349	#define PnDSYR 0x00114
350	#define PnDPXR 0x00118
351	#define PnDPYR 0x0011c
352
353	#define PnDSA0R 0x00120
354	#define PnDSA1R 0x00124
355	#define PnDSA2R 0x00128
356	#define PnDSA_MASK 0xfffffff0
357
358	#define PnSPXR 0x00130
359	#define PnSPYR 0x00134
360	#define PnWASPR 0x00138
361	#define PnWAMWR 0x0013c
362
363	#define PnBTR 0x00140
364
365	#define PnTC1R 0x00144
366	#define PnTC2R 0x00148
367	#define PnTC3R 0x0014c
368	#define PnTC3R_CODE (0x66 << 24)
369
370	#define PnMLR 0x00150
371
372	#define PnSWAPR 0x00180
373	#define PnSWAPR_DIGN (1 << 4)
374	#define PnSWAPR_SPQW (1 << 3)
375	#define PnSWAPR_SPLW (1 << 2)
376	#define PnSWAPR_SPWD (1 << 1)
377	#define PnSWAPR_SPBY (1 << 0)
378
379	#define PnDDCR 0x00184
380	#define PnDDCR_CODE (0x7775 << 16)
381	#define PnDDCR_LRGB1 (1 << 11)
382	#define PnDDCR_LRGB0 (1 << 10)
383
384	#define PnDDCR2 0x00188
385	#define PnDDCR2_CODE (0x7776 << 16)
386	#define PnDDCR2_NV21 (1 << 5)
387	#define PnDDCR2_Y420 (1 << 4)
388	#define PnDDCR2_DIVU (1 << 1)
389	#define PnDDCR2_DIVY (1 << 0)
390
391	#define PnDDCR4 0x00190
392	#define PnDDCR4_CODE (0x7766 << 16)
34a04f2b	393	#define PnDDCR4_VSPS (1 << 13)
4bf8e196 LP	394	#define PnDDCR4_SDFS_RGB (0 << 4)
	395	#define PnDDCR4_SDFS_YC (5 << 4)
	396	#define PnDDCR4_SDFS_MASK (7 << 4)
	397	#define PnDDCR4_EDF_NONE (0 << 0)
	398	#define PnDDCR4_EDF_ARGB8888 (1 << 0)
	399	#define PnDDCR4_EDF_RGB888 (2 << 0)
	400	#define PnDDCR4_EDF_RGB666 (3 << 0)
	401	#define PnDDCR4_EDF_MASK (7 << 0)
	402
	403	#define APnMR 0x0a100
	404	#define APnMR_WAE (1 << 16) /* Wrap around Enable */
	405	#define APnMR_DC (1 << 7) /* Display Area Change */
	406	#define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
	407	#define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */
	408
	409	#define APnMWR 0x0a104
6811b1be LP	410
	411	#define APnDSXR 0x0a110
	412	#define APnDSYR 0x0a114
	413	#define APnDPXR 0x0a118
	414	#define APnDPYR 0x0a11c
	415
4bf8e196 LP	416	#define APnDSA0R 0x0a120
	417	#define APnDSA1R 0x0a124
	418	#define APnDSA2R 0x0a128
6811b1be LP	419
	420	#define APnSPXR 0x0a130
	421	#define APnSPYR 0x0a134
	422	#define APnWASPR 0x0a138
	423	#define APnWAMWR 0x0a13c
	424
	425	#define APnBTR 0x0a140
	426
4bf8e196	427	#define APnMLR 0x0a150
6811b1be	428	#define APnSWAPR 0x0a180
4bf8e196 LP	429
	430	/* -----------------------------------------------------------------------------
	431	* Display Capture Registers
	432	*/
	433
ef2d84be	434	#define DCMR 0x0c100
4bf8e196	435	#define DCMWR 0x0c104
4bf8e196	436	#define DCSAR 0x0c120
4bf8e196	437	#define DCMLR 0x0c150
4bf8e196 LP	438
	439	/* -----------------------------------------------------------------------------
	440	* Color Palette Registers
	441	*/
	442
	443	#define CP1_000R 0x01000
	444	#define CP1_255R 0x013fc
	445	#define CP2_000R 0x02000
	446	#define CP2_255R 0x023fc
	447	#define CP3_000R 0x03000
	448	#define CP3_255R 0x033fc
	449	#define CP4_000R 0x04000
	450	#define CP4_255R 0x043fc
	451
	452	/* -----------------------------------------------------------------------------
	453	* External Synchronization Control Registers
	454	*/
	455
	456	#define ESCR 0x10000
	457	#define ESCR2 0x31000
	458	#define ESCR_DCLKOINV (1 << 25)
	459	#define ESCR_DCLKSEL_DCLKIN (0 << 20)
	460	#define ESCR_DCLKSEL_CLKS (1 << 20)
	461	#define ESCR_DCLKSEL_MASK (1 << 20)
	462	#define ESCR_DCLKDIS (1 << 16)
	463	#define ESCR_SYNCSEL_OFF (0 << 8)
	464	#define ESCR_SYNCSEL_EXVSYNC (2 << 8)
	465	#define ESCR_SYNCSEL_EXHSYNC (3 << 8)
	466	#define ESCR_FRQSEL_MASK (0x3f << 0)
	467
	468	#define OTAR 0x10004
	469	#define OTAR2 0x31004
	470
	471	/* -----------------------------------------------------------------------------
	472	* Dual Display Output Control Registers
	473	*/
	474
	475	#define DORCR 0x11000
	476	#define DORCR_PG2T (1 << 30)
	477	#define DORCR_DK2S (1 << 28)
	478	#define DORCR_PG2D_DS1 (0 << 24)
	479	#define DORCR_PG2D_DS2 (1 << 24)
	480	#define DORCR_PG2D_FIX0 (2 << 24)
	481	#define DORCR_PG2D_DOOR (3 << 24)
	482	#define DORCR_PG2D_MASK (3 << 24)
	483	#define DORCR_DR1D (1 << 21)
	484	#define DORCR_PG1D_DS1 (0 << 16)
	485	#define DORCR_PG1D_DS2 (1 << 16)
	486	#define DORCR_PG1D_FIX0 (2 << 16)
	487	#define DORCR_PG1D_DOOR (3 << 16)
	488	#define DORCR_PG1D_MASK (3 << 16)
	489	#define DORCR_RGPV (1 << 4)
	490	#define DORCR_DPRS (1 << 0)
	491
	492	#define DPTSR 0x11004
	493	#define DPTSR_PnDK(n) (1 << ((n) + 16))
	494	#define DPTSR_PnTS(n) (1 << (n))
	495
	496	#define DAPTSR 0x11008
	497	#define DAPTSR_APnDK(n) (1 << ((n) + 16))
	498	#define DAPTSR_APnTS(n) (1 << (n))
	499
	500	#define DS1PR 0x11020
	501	#define DS2PR 0x11024
502
503	/* -----------------------------------------------------------------------------
504	* YC-RGB Conversion Coefficient Registers
505	*/
506
507	#define YNCR 0x11080
508	#define YNOR 0x11084
509	#define CRNOR 0x11088
510	#define CBNOR 0x1108c
511	#define RCRCR 0x11090
512	#define GCRCR 0x11094
513	#define GCBCR 0x11098
514	#define BCBCR 0x1109c
515
516	#endif /* __RCAR_DU_REGS_H__ */