Commit | Line | Data |
---|---|---|
2048e328 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <drm/drm.h> | |
16 | #include <drm/drmP.h> | |
63ebb9fa | 17 | #include <drm/drm_atomic.h> |
2048e328 MY |
18 | #include <drm/drm_crtc.h> |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include <linux/kernel.h> | |
00fe6148 | 23 | #include <linux/module.h> |
2048e328 MY |
24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/component.h> | |
30 | ||
31 | #include <linux/reset.h> | |
32 | #include <linux/delay.h> | |
33 | ||
34 | #include "rockchip_drm_drv.h" | |
35 | #include "rockchip_drm_gem.h" | |
36 | #include "rockchip_drm_fb.h" | |
37 | #include "rockchip_drm_vop.h" | |
38 | ||
2048e328 MY |
39 | #define __REG_SET_RELAXED(x, off, mask, shift, v) \ |
40 | vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) | |
41 | #define __REG_SET_NORMAL(x, off, mask, shift, v) \ | |
42 | vop_mask_write(x, off, (mask) << shift, (v) << shift) | |
43 | ||
44 | #define REG_SET(x, base, reg, v, mode) \ | |
45 | __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) | |
c7647f86 JK |
46 | #define REG_SET_MASK(x, base, reg, mask, v, mode) \ |
47 | __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) | |
2048e328 MY |
48 | |
49 | #define VOP_WIN_SET(x, win, name, v) \ | |
50 | REG_SET(x, win->base, win->phy->name, v, RELAXED) | |
4c156c21 MY |
51 | #define VOP_SCL_SET(x, win, name, v) \ |
52 | REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) | |
1194fffb MY |
53 | #define VOP_SCL_SET_EXT(x, win, name, v) \ |
54 | REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) | |
2048e328 MY |
55 | #define VOP_CTRL_SET(x, name, v) \ |
56 | REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) | |
57 | ||
dbb3d944 MY |
58 | #define VOP_INTR_GET(vop, name) \ |
59 | vop_read_reg(vop, 0, &vop->data->ctrl->name) | |
60 | ||
c7647f86 JK |
61 | #define VOP_INTR_SET(vop, name, mask, v) \ |
62 | REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) | |
dbb3d944 MY |
63 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
64 | do { \ | |
c7647f86 | 65 | int i, reg = 0, mask = 0; \ |
dbb3d944 | 66 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
c7647f86 | 67 | if (vop->data->intr->intrs[i] & type) { \ |
dbb3d944 | 68 | reg |= (v) << i; \ |
c7647f86 JK |
69 | mask |= 1 << i; \ |
70 | } \ | |
dbb3d944 | 71 | } \ |
c7647f86 | 72 | VOP_INTR_SET(vop, name, mask, reg); \ |
dbb3d944 MY |
73 | } while (0) |
74 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
75 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
76 | ||
2048e328 MY |
77 | #define VOP_WIN_GET(x, win, name) \ |
78 | vop_read_reg(x, win->base, &win->phy->name) | |
79 | ||
80 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ | |
81 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
82 | ||
83 | #define to_vop(x) container_of(x, struct vop, crtc) | |
84 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
63ebb9fa | 85 | #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) |
2048e328 | 86 | |
63ebb9fa MY |
87 | struct vop_plane_state { |
88 | struct drm_plane_state base; | |
89 | int format; | |
2048e328 | 90 | dma_addr_t yrgb_mst; |
63ebb9fa | 91 | bool enable; |
2048e328 MY |
92 | }; |
93 | ||
94 | struct vop_win { | |
95 | struct drm_plane base; | |
96 | const struct vop_win_data *data; | |
97 | struct vop *vop; | |
98 | ||
4f9d39a7 DV |
99 | /* protected by dev->event_lock */ |
100 | bool enable; | |
101 | dma_addr_t yrgb_mst; | |
2048e328 MY |
102 | }; |
103 | ||
104 | struct vop { | |
105 | struct drm_crtc crtc; | |
106 | struct device *dev; | |
107 | struct drm_device *drm_dev; | |
31e980c5 | 108 | bool is_enabled; |
2048e328 | 109 | |
2048e328 MY |
110 | /* mutex vsync_ work */ |
111 | struct mutex vsync_mutex; | |
112 | bool vsync_work_pending; | |
1067219b | 113 | struct completion dsp_hold_completion; |
63ebb9fa | 114 | struct completion wait_update_complete; |
4f9d39a7 DV |
115 | |
116 | /* protected by dev->event_lock */ | |
63ebb9fa | 117 | struct drm_pending_vblank_event *event; |
2048e328 MY |
118 | |
119 | const struct vop_data *data; | |
120 | ||
121 | uint32_t *regsbak; | |
122 | void __iomem *regs; | |
123 | ||
124 | /* physical map length of vop register */ | |
125 | uint32_t len; | |
126 | ||
127 | /* one time only one process allowed to config the register */ | |
128 | spinlock_t reg_lock; | |
129 | /* lock vop irq reg */ | |
130 | spinlock_t irq_lock; | |
131 | ||
132 | unsigned int irq; | |
133 | ||
134 | /* vop AHP clk */ | |
135 | struct clk *hclk; | |
136 | /* vop dclk */ | |
137 | struct clk *dclk; | |
138 | /* vop share memory frequency */ | |
139 | struct clk *aclk; | |
140 | ||
141 | /* vop dclk reset */ | |
142 | struct reset_control *dclk_rst; | |
143 | ||
2048e328 MY |
144 | struct vop_win win[]; |
145 | }; | |
146 | ||
2048e328 MY |
147 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
148 | { | |
149 | writel(v, vop->regs + offset); | |
150 | vop->regsbak[offset >> 2] = v; | |
151 | } | |
152 | ||
153 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
154 | { | |
155 | return readl(vop->regs + offset); | |
156 | } | |
157 | ||
158 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
159 | const struct vop_reg *reg) | |
160 | { | |
161 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
162 | } | |
163 | ||
2048e328 MY |
164 | static inline void vop_mask_write(struct vop *vop, uint32_t offset, |
165 | uint32_t mask, uint32_t v) | |
166 | { | |
167 | if (mask) { | |
168 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
169 | ||
170 | cached_val = (cached_val & ~mask) | v; | |
171 | writel(cached_val, vop->regs + offset); | |
172 | vop->regsbak[offset >> 2] = cached_val; | |
173 | } | |
174 | } | |
175 | ||
176 | static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, | |
177 | uint32_t mask, uint32_t v) | |
178 | { | |
179 | if (mask) { | |
180 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
181 | ||
182 | cached_val = (cached_val & ~mask) | v; | |
183 | writel_relaxed(cached_val, vop->regs + offset); | |
184 | vop->regsbak[offset >> 2] = cached_val; | |
185 | } | |
186 | } | |
187 | ||
dbb3d944 MY |
188 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
189 | const struct vop_reg *reg, int type) | |
190 | { | |
191 | uint32_t i, ret = 0; | |
192 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
193 | ||
194 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
195 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
196 | ret |= vop->data->intr->intrs[i]; | |
197 | } | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
0cf33fe3 MY |
202 | static inline void vop_cfg_done(struct vop *vop) |
203 | { | |
204 | VOP_CTRL_SET(vop, cfg_done, 1); | |
205 | } | |
206 | ||
85a359f2 TF |
207 | static bool has_rb_swapped(uint32_t format) |
208 | { | |
209 | switch (format) { | |
210 | case DRM_FORMAT_XBGR8888: | |
211 | case DRM_FORMAT_ABGR8888: | |
212 | case DRM_FORMAT_BGR888: | |
213 | case DRM_FORMAT_BGR565: | |
214 | return true; | |
215 | default: | |
216 | return false; | |
217 | } | |
218 | } | |
219 | ||
2048e328 MY |
220 | static enum vop_data_format vop_convert_format(uint32_t format) |
221 | { | |
222 | switch (format) { | |
223 | case DRM_FORMAT_XRGB8888: | |
224 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
225 | case DRM_FORMAT_XBGR8888: |
226 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
227 | return VOP_FMT_ARGB8888; |
228 | case DRM_FORMAT_RGB888: | |
85a359f2 | 229 | case DRM_FORMAT_BGR888: |
2048e328 MY |
230 | return VOP_FMT_RGB888; |
231 | case DRM_FORMAT_RGB565: | |
85a359f2 | 232 | case DRM_FORMAT_BGR565: |
2048e328 MY |
233 | return VOP_FMT_RGB565; |
234 | case DRM_FORMAT_NV12: | |
235 | return VOP_FMT_YUV420SP; | |
236 | case DRM_FORMAT_NV16: | |
237 | return VOP_FMT_YUV422SP; | |
238 | case DRM_FORMAT_NV24: | |
239 | return VOP_FMT_YUV444SP; | |
240 | default: | |
241 | DRM_ERROR("unsupport format[%08x]\n", format); | |
242 | return -EINVAL; | |
243 | } | |
244 | } | |
245 | ||
84c7f8ca MY |
246 | static bool is_yuv_support(uint32_t format) |
247 | { | |
248 | switch (format) { | |
249 | case DRM_FORMAT_NV12: | |
250 | case DRM_FORMAT_NV16: | |
251 | case DRM_FORMAT_NV24: | |
252 | return true; | |
253 | default: | |
254 | return false; | |
255 | } | |
256 | } | |
257 | ||
2048e328 MY |
258 | static bool is_alpha_support(uint32_t format) |
259 | { | |
260 | switch (format) { | |
261 | case DRM_FORMAT_ARGB8888: | |
85a359f2 | 262 | case DRM_FORMAT_ABGR8888: |
2048e328 MY |
263 | return true; |
264 | default: | |
265 | return false; | |
266 | } | |
267 | } | |
268 | ||
4c156c21 MY |
269 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
270 | uint32_t dst, bool is_horizontal, | |
271 | int vsu_mode, int *vskiplines) | |
272 | { | |
273 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
274 | ||
275 | if (is_horizontal) { | |
276 | if (mode == SCALE_UP) | |
277 | val = GET_SCL_FT_BIC(src, dst); | |
278 | else if (mode == SCALE_DOWN) | |
279 | val = GET_SCL_FT_BILI_DN(src, dst); | |
280 | } else { | |
281 | if (mode == SCALE_UP) { | |
282 | if (vsu_mode == SCALE_UP_BIL) | |
283 | val = GET_SCL_FT_BILI_UP(src, dst); | |
284 | else | |
285 | val = GET_SCL_FT_BIC(src, dst); | |
286 | } else if (mode == SCALE_DOWN) { | |
287 | if (vskiplines) { | |
288 | *vskiplines = scl_get_vskiplines(src, dst); | |
289 | val = scl_get_bili_dn_vskip(src, dst, | |
290 | *vskiplines); | |
291 | } else { | |
292 | val = GET_SCL_FT_BILI_DN(src, dst); | |
293 | } | |
294 | } | |
295 | } | |
296 | ||
297 | return val; | |
298 | } | |
299 | ||
300 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
301 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
302 | uint32_t dst_h, uint32_t pixel_format) | |
303 | { | |
304 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
305 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
306 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
307 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
308 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
309 | bool is_yuv = is_yuv_support(pixel_format); | |
310 | uint16_t cbcr_src_w = src_w / hsub; | |
311 | uint16_t cbcr_src_h = src_h / vsub; | |
312 | uint16_t vsu_mode; | |
313 | uint16_t lb_mode; | |
314 | uint32_t val; | |
2db00cf5 | 315 | int vskiplines = 0; |
4c156c21 MY |
316 | |
317 | if (dst_w > 3840) { | |
318 | DRM_ERROR("Maximum destination width (3840) exceeded\n"); | |
319 | return; | |
320 | } | |
321 | ||
1194fffb MY |
322 | if (!win->phy->scl->ext) { |
323 | VOP_SCL_SET(vop, win, scale_yrgb_x, | |
324 | scl_cal_scale2(src_w, dst_w)); | |
325 | VOP_SCL_SET(vop, win, scale_yrgb_y, | |
326 | scl_cal_scale2(src_h, dst_h)); | |
327 | if (is_yuv) { | |
328 | VOP_SCL_SET(vop, win, scale_cbcr_x, | |
ee8662fc | 329 | scl_cal_scale2(cbcr_src_w, dst_w)); |
1194fffb | 330 | VOP_SCL_SET(vop, win, scale_cbcr_y, |
ee8662fc | 331 | scl_cal_scale2(cbcr_src_h, dst_h)); |
1194fffb MY |
332 | } |
333 | return; | |
334 | } | |
335 | ||
4c156c21 MY |
336 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); |
337 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
338 | ||
339 | if (is_yuv) { | |
340 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
341 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
342 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
343 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
344 | else | |
345 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
346 | } else { | |
347 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
348 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
349 | else | |
350 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
351 | } | |
352 | ||
1194fffb | 353 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
4c156c21 MY |
354 | if (lb_mode == LB_RGB_3840X2) { |
355 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
356 | DRM_ERROR("ERROR : not allow yrgb ver scale\n"); | |
357 | return; | |
358 | } | |
359 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
360 | DRM_ERROR("ERROR : not allow cbcr ver scale\n"); | |
361 | return; | |
362 | } | |
363 | vsu_mode = SCALE_UP_BIL; | |
364 | } else if (lb_mode == LB_RGB_2560X4) { | |
365 | vsu_mode = SCALE_UP_BIL; | |
366 | } else { | |
367 | vsu_mode = SCALE_UP_BIC; | |
368 | } | |
369 | ||
370 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
371 | true, 0, NULL); | |
372 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
373 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
374 | false, vsu_mode, &vskiplines); | |
375 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
376 | ||
1194fffb MY |
377 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
378 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
4c156c21 | 379 | |
1194fffb MY |
380 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
381 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
382 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
383 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
384 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); | |
4c156c21 MY |
385 | if (is_yuv) { |
386 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
387 | dst_w, true, 0, NULL); | |
388 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
389 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
390 | dst_h, false, vsu_mode, &vskiplines); | |
391 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
392 | ||
1194fffb MY |
393 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
394 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
395 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
396 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
397 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
398 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
399 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); | |
4c156c21 MY |
400 | } |
401 | } | |
402 | ||
1067219b MY |
403 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
404 | { | |
405 | unsigned long flags; | |
406 | ||
407 | if (WARN_ON(!vop->is_enabled)) | |
408 | return; | |
409 | ||
410 | spin_lock_irqsave(&vop->irq_lock, flags); | |
411 | ||
dbb3d944 | 412 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
413 | |
414 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
415 | } | |
416 | ||
417 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
418 | { | |
419 | unsigned long flags; | |
420 | ||
421 | if (WARN_ON(!vop->is_enabled)) | |
422 | return; | |
423 | ||
424 | spin_lock_irqsave(&vop->irq_lock, flags); | |
425 | ||
dbb3d944 | 426 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
427 | |
428 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
429 | } | |
430 | ||
63ebb9fa | 431 | static void vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
432 | { |
433 | struct vop *vop = to_vop(crtc); | |
434 | int ret; | |
435 | ||
5d82d1a7 MY |
436 | ret = pm_runtime_get_sync(vop->dev); |
437 | if (ret < 0) { | |
438 | dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); | |
439 | return; | |
440 | } | |
441 | ||
2048e328 MY |
442 | ret = clk_enable(vop->hclk); |
443 | if (ret < 0) { | |
444 | dev_err(vop->dev, "failed to enable hclk - %d\n", ret); | |
445 | return; | |
446 | } | |
447 | ||
448 | ret = clk_enable(vop->dclk); | |
449 | if (ret < 0) { | |
450 | dev_err(vop->dev, "failed to enable dclk - %d\n", ret); | |
451 | goto err_disable_hclk; | |
452 | } | |
453 | ||
454 | ret = clk_enable(vop->aclk); | |
455 | if (ret < 0) { | |
456 | dev_err(vop->dev, "failed to enable aclk - %d\n", ret); | |
457 | goto err_disable_dclk; | |
458 | } | |
459 | ||
460 | /* | |
461 | * Slave iommu shares power, irq and clock with vop. It was associated | |
462 | * automatically with this master device via common driver code. | |
463 | * Now that we have enabled the clock we attach it to the shared drm | |
464 | * mapping. | |
465 | */ | |
466 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
467 | if (ret) { | |
468 | dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); | |
469 | goto err_disable_aclk; | |
470 | } | |
471 | ||
77faa161 | 472 | memcpy(vop->regs, vop->regsbak, vop->len); |
52ab7891 MY |
473 | /* |
474 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
475 | */ | |
476 | vop->is_enabled = true; | |
477 | ||
2048e328 MY |
478 | spin_lock(&vop->reg_lock); |
479 | ||
480 | VOP_CTRL_SET(vop, standby, 0); | |
481 | ||
482 | spin_unlock(&vop->reg_lock); | |
483 | ||
484 | enable_irq(vop->irq); | |
485 | ||
b5f7b755 | 486 | drm_crtc_vblank_on(crtc); |
2048e328 MY |
487 | |
488 | return; | |
489 | ||
490 | err_disable_aclk: | |
491 | clk_disable(vop->aclk); | |
492 | err_disable_dclk: | |
493 | clk_disable(vop->dclk); | |
494 | err_disable_hclk: | |
495 | clk_disable(vop->hclk); | |
496 | } | |
497 | ||
0ad3675d | 498 | static void vop_crtc_disable(struct drm_crtc *crtc) |
2048e328 MY |
499 | { |
500 | struct vop *vop = to_vop(crtc); | |
3ed6c649 | 501 | int i; |
2048e328 | 502 | |
893b6cad DV |
503 | WARN_ON(vop->event); |
504 | ||
3ed6c649 TV |
505 | /* |
506 | * We need to make sure that all windows are disabled before we | |
507 | * disable that crtc. Otherwise we might try to scan from a destroyed | |
508 | * buffer later. | |
509 | */ | |
510 | for (i = 0; i < vop->data->win_size; i++) { | |
511 | struct vop_win *vop_win = &vop->win[i]; | |
512 | const struct vop_win_data *win = vop_win->data; | |
513 | ||
514 | spin_lock(&vop->reg_lock); | |
515 | VOP_WIN_SET(vop, win, enable, 0); | |
516 | spin_unlock(&vop->reg_lock); | |
517 | } | |
518 | ||
b5f7b755 | 519 | drm_crtc_vblank_off(crtc); |
2048e328 | 520 | |
2048e328 | 521 | /* |
1067219b MY |
522 | * Vop standby will take effect at end of current frame, |
523 | * if dsp hold valid irq happen, it means standby complete. | |
524 | * | |
525 | * we must wait standby complete when we want to disable aclk, | |
526 | * if not, memory bus maybe dead. | |
2048e328 | 527 | */ |
1067219b MY |
528 | reinit_completion(&vop->dsp_hold_completion); |
529 | vop_dsp_hold_valid_irq_enable(vop); | |
530 | ||
2048e328 MY |
531 | spin_lock(&vop->reg_lock); |
532 | ||
533 | VOP_CTRL_SET(vop, standby, 1); | |
534 | ||
535 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 536 | |
1067219b MY |
537 | wait_for_completion(&vop->dsp_hold_completion); |
538 | ||
539 | vop_dsp_hold_valid_irq_disable(vop); | |
540 | ||
541 | disable_irq(vop->irq); | |
542 | ||
52ab7891 | 543 | vop->is_enabled = false; |
1067219b | 544 | |
2048e328 | 545 | /* |
1067219b | 546 | * vop standby complete, so iommu detach is safe. |
2048e328 | 547 | */ |
2048e328 MY |
548 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
549 | ||
1067219b | 550 | clk_disable(vop->dclk); |
2048e328 MY |
551 | clk_disable(vop->aclk); |
552 | clk_disable(vop->hclk); | |
5d82d1a7 | 553 | pm_runtime_put(vop->dev); |
893b6cad DV |
554 | |
555 | if (crtc->state->event && !crtc->state->active) { | |
556 | spin_lock_irq(&crtc->dev->event_lock); | |
557 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
558 | spin_unlock_irq(&crtc->dev->event_lock); | |
559 | ||
560 | crtc->state->event = NULL; | |
561 | } | |
2048e328 MY |
562 | } |
563 | ||
63ebb9fa | 564 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 565 | { |
63ebb9fa | 566 | drm_plane_cleanup(plane); |
2048e328 MY |
567 | } |
568 | ||
44d0237a MY |
569 | static int vop_plane_prepare_fb(struct drm_plane *plane, |
570 | const struct drm_plane_state *new_state) | |
571 | { | |
572 | if (plane->state->fb) | |
573 | drm_framebuffer_reference(plane->state->fb); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static void vop_plane_cleanup_fb(struct drm_plane *plane, | |
579 | const struct drm_plane_state *old_state) | |
580 | { | |
581 | if (old_state->fb) | |
582 | drm_framebuffer_unreference(old_state->fb); | |
583 | } | |
584 | ||
63ebb9fa MY |
585 | static int vop_plane_atomic_check(struct drm_plane *plane, |
586 | struct drm_plane_state *state) | |
2048e328 | 587 | { |
63ebb9fa | 588 | struct drm_crtc *crtc = state->crtc; |
92915da6 | 589 | struct drm_crtc_state *crtc_state; |
63ebb9fa | 590 | struct drm_framebuffer *fb = state->fb; |
2048e328 | 591 | struct vop_win *vop_win = to_vop_win(plane); |
63ebb9fa | 592 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); |
2048e328 | 593 | const struct vop_win_data *win = vop_win->data; |
2048e328 | 594 | int ret; |
63ebb9fa | 595 | struct drm_rect clip; |
4c156c21 MY |
596 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
597 | DRM_PLANE_HELPER_NO_SCALING; | |
598 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
599 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 600 | |
63ebb9fa MY |
601 | if (!crtc || !fb) |
602 | goto out_disable; | |
92915da6 JK |
603 | |
604 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); | |
605 | if (WARN_ON(!crtc_state)) | |
606 | return -EINVAL; | |
607 | ||
63ebb9fa MY |
608 | clip.x1 = 0; |
609 | clip.y1 = 0; | |
92915da6 JK |
610 | clip.x2 = crtc_state->adjusted_mode.hdisplay; |
611 | clip.y2 = crtc_state->adjusted_mode.vdisplay; | |
63ebb9fa | 612 | |
f9b96be0 VS |
613 | ret = drm_plane_helper_check_state(state, &clip, |
614 | min_scale, max_scale, | |
615 | true, true); | |
2048e328 MY |
616 | if (ret) |
617 | return ret; | |
618 | ||
f9b96be0 | 619 | if (!state->visible) |
63ebb9fa | 620 | goto out_disable; |
2048e328 | 621 | |
63ebb9fa MY |
622 | vop_plane_state->format = vop_convert_format(fb->pixel_format); |
623 | if (vop_plane_state->format < 0) | |
624 | return vop_plane_state->format; | |
84c7f8ca | 625 | |
63ebb9fa MY |
626 | /* |
627 | * Src.x1 can be odd when do clip, but yuv plane start point | |
628 | * need align with 2 pixel. | |
629 | */ | |
f9b96be0 | 630 | if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2)) |
2048e328 | 631 | return -EINVAL; |
2048e328 | 632 | |
63ebb9fa | 633 | vop_plane_state->enable = true; |
2048e328 | 634 | |
63ebb9fa | 635 | return 0; |
84c7f8ca | 636 | |
63ebb9fa MY |
637 | out_disable: |
638 | vop_plane_state->enable = false; | |
639 | return 0; | |
640 | } | |
2048e328 | 641 | |
63ebb9fa MY |
642 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
643 | struct drm_plane_state *old_state) | |
644 | { | |
645 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); | |
646 | struct vop_win *vop_win = to_vop_win(plane); | |
647 | const struct vop_win_data *win = vop_win->data; | |
648 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 649 | |
63ebb9fa MY |
650 | if (!old_state->crtc) |
651 | return; | |
2048e328 | 652 | |
4f9d39a7 DV |
653 | spin_lock_irq(&plane->dev->event_lock); |
654 | vop_win->enable = false; | |
655 | vop_win->yrgb_mst = 0; | |
656 | spin_unlock_irq(&plane->dev->event_lock); | |
657 | ||
63ebb9fa | 658 | spin_lock(&vop->reg_lock); |
2048e328 | 659 | |
63ebb9fa | 660 | VOP_WIN_SET(vop, win, enable, 0); |
84c7f8ca | 661 | |
63ebb9fa | 662 | spin_unlock(&vop->reg_lock); |
84c7f8ca | 663 | |
63ebb9fa MY |
664 | vop_plane_state->enable = false; |
665 | } | |
84c7f8ca | 666 | |
63ebb9fa MY |
667 | static void vop_plane_atomic_update(struct drm_plane *plane, |
668 | struct drm_plane_state *old_state) | |
669 | { | |
670 | struct drm_plane_state *state = plane->state; | |
671 | struct drm_crtc *crtc = state->crtc; | |
672 | struct vop_win *vop_win = to_vop_win(plane); | |
673 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); | |
674 | const struct vop_win_data *win = vop_win->data; | |
675 | struct vop *vop = to_vop(state->crtc); | |
676 | struct drm_framebuffer *fb = state->fb; | |
677 | unsigned int actual_w, actual_h; | |
678 | unsigned int dsp_stx, dsp_sty; | |
679 | uint32_t act_info, dsp_info, dsp_st; | |
ac92028e VS |
680 | struct drm_rect *src = &state->src; |
681 | struct drm_rect *dest = &state->dst; | |
63ebb9fa MY |
682 | struct drm_gem_object *obj, *uv_obj; |
683 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
684 | unsigned long offset; | |
685 | dma_addr_t dma_addr; | |
686 | uint32_t val; | |
687 | bool rb_swap; | |
84c7f8ca | 688 | |
2048e328 | 689 | /* |
63ebb9fa | 690 | * can't update plane when vop is disabled. |
2048e328 | 691 | */ |
4f9d39a7 | 692 | if (WARN_ON(!crtc)) |
63ebb9fa | 693 | return; |
2048e328 | 694 | |
63ebb9fa MY |
695 | if (WARN_ON(!vop->is_enabled)) |
696 | return; | |
2048e328 | 697 | |
63ebb9fa MY |
698 | if (!vop_plane_state->enable) { |
699 | vop_plane_atomic_disable(plane, old_state); | |
700 | return; | |
2048e328 | 701 | } |
63ebb9fa MY |
702 | |
703 | obj = rockchip_fb_get_gem_obj(fb, 0); | |
704 | rk_obj = to_rockchip_obj(obj); | |
705 | ||
706 | actual_w = drm_rect_width(src) >> 16; | |
707 | actual_h = drm_rect_height(src) >> 16; | |
708 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
709 | ||
710 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
711 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
712 | ||
713 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
714 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
715 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
716 | ||
717 | offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); | |
718 | offset += (src->y1 >> 16) * fb->pitches[0]; | |
719 | vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; | |
2048e328 | 720 | |
4f9d39a7 DV |
721 | spin_lock_irq(&plane->dev->event_lock); |
722 | vop_win->enable = true; | |
723 | vop_win->yrgb_mst = vop_plane_state->yrgb_mst; | |
724 | spin_unlock_irq(&plane->dev->event_lock); | |
725 | ||
2048e328 MY |
726 | spin_lock(&vop->reg_lock); |
727 | ||
63ebb9fa MY |
728 | VOP_WIN_SET(vop, win, format, vop_plane_state->format); |
729 | VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); | |
730 | VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); | |
731 | if (is_yuv_support(fb->pixel_format)) { | |
732 | int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); | |
733 | int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); | |
734 | int bpp = drm_format_plane_cpp(fb->pixel_format, 1); | |
735 | ||
736 | uv_obj = rockchip_fb_get_gem_obj(fb, 1); | |
737 | rk_uv_obj = to_rockchip_obj(uv_obj); | |
738 | ||
739 | offset = (src->x1 >> 16) * bpp / hsub; | |
740 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
741 | ||
742 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
743 | VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); | |
744 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); | |
84c7f8ca | 745 | } |
4c156c21 MY |
746 | |
747 | if (win->phy->scl) | |
748 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 749 | drm_rect_width(dest), drm_rect_height(dest), |
4c156c21 MY |
750 | fb->pixel_format); |
751 | ||
63ebb9fa MY |
752 | VOP_WIN_SET(vop, win, act_info, act_info); |
753 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
754 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 755 | |
63ebb9fa | 756 | rb_swap = has_rb_swapped(fb->pixel_format); |
85a359f2 | 757 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 758 | |
63ebb9fa | 759 | if (is_alpha_support(fb->pixel_format)) { |
2048e328 MY |
760 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
761 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
762 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
763 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
764 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
765 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
766 | SRC_FACTOR_M0(ALPHA_ONE); | |
767 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
768 | } else { | |
769 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
770 | } | |
771 | ||
772 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 773 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
774 | } |
775 | ||
63ebb9fa | 776 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
44d0237a MY |
777 | .prepare_fb = vop_plane_prepare_fb, |
778 | .cleanup_fb = vop_plane_cleanup_fb, | |
63ebb9fa MY |
779 | .atomic_check = vop_plane_atomic_check, |
780 | .atomic_update = vop_plane_atomic_update, | |
781 | .atomic_disable = vop_plane_atomic_disable, | |
782 | }; | |
2048e328 | 783 | |
8ff490ae | 784 | static void vop_atomic_plane_reset(struct drm_plane *plane) |
2048e328 | 785 | { |
63ebb9fa MY |
786 | struct vop_plane_state *vop_plane_state = |
787 | to_vop_plane_state(plane->state); | |
2048e328 | 788 | |
63ebb9fa MY |
789 | if (plane->state && plane->state->fb) |
790 | drm_framebuffer_unreference(plane->state->fb); | |
791 | ||
792 | kfree(vop_plane_state); | |
793 | vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); | |
794 | if (!vop_plane_state) | |
795 | return; | |
2048e328 | 796 | |
63ebb9fa MY |
797 | plane->state = &vop_plane_state->base; |
798 | plane->state->plane = plane; | |
2048e328 MY |
799 | } |
800 | ||
8ff490ae | 801 | static struct drm_plane_state * |
63ebb9fa | 802 | vop_atomic_plane_duplicate_state(struct drm_plane *plane) |
2048e328 | 803 | { |
63ebb9fa MY |
804 | struct vop_plane_state *old_vop_plane_state; |
805 | struct vop_plane_state *vop_plane_state; | |
2048e328 | 806 | |
63ebb9fa MY |
807 | if (WARN_ON(!plane->state)) |
808 | return NULL; | |
2048e328 | 809 | |
63ebb9fa MY |
810 | old_vop_plane_state = to_vop_plane_state(plane->state); |
811 | vop_plane_state = kmemdup(old_vop_plane_state, | |
812 | sizeof(*vop_plane_state), GFP_KERNEL); | |
813 | if (!vop_plane_state) | |
814 | return NULL; | |
2048e328 | 815 | |
63ebb9fa MY |
816 | __drm_atomic_helper_plane_duplicate_state(plane, |
817 | &vop_plane_state->base); | |
2048e328 | 818 | |
63ebb9fa | 819 | return &vop_plane_state->base; |
2048e328 MY |
820 | } |
821 | ||
63ebb9fa MY |
822 | static void vop_atomic_plane_destroy_state(struct drm_plane *plane, |
823 | struct drm_plane_state *state) | |
2048e328 | 824 | { |
63ebb9fa MY |
825 | struct vop_plane_state *vop_state = to_vop_plane_state(state); |
826 | ||
2f701695 | 827 | __drm_atomic_helper_plane_destroy_state(state); |
63ebb9fa MY |
828 | |
829 | kfree(vop_state); | |
2048e328 MY |
830 | } |
831 | ||
832 | static const struct drm_plane_funcs vop_plane_funcs = { | |
63ebb9fa MY |
833 | .update_plane = drm_atomic_helper_update_plane, |
834 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 835 | .destroy = vop_plane_destroy, |
63ebb9fa MY |
836 | .reset = vop_atomic_plane_reset, |
837 | .atomic_duplicate_state = vop_atomic_plane_duplicate_state, | |
838 | .atomic_destroy_state = vop_atomic_plane_destroy_state, | |
2048e328 MY |
839 | }; |
840 | ||
2048e328 MY |
841 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) |
842 | { | |
843 | struct vop *vop = to_vop(crtc); | |
844 | unsigned long flags; | |
845 | ||
63ebb9fa | 846 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
847 | return -EPERM; |
848 | ||
849 | spin_lock_irqsave(&vop->irq_lock, flags); | |
850 | ||
dbb3d944 | 851 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
852 | |
853 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
858 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
859 | { | |
860 | struct vop *vop = to_vop(crtc); | |
861 | unsigned long flags; | |
862 | ||
63ebb9fa | 863 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 864 | return; |
31e980c5 | 865 | |
2048e328 | 866 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
867 | |
868 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
869 | ||
2048e328 MY |
870 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
871 | } | |
872 | ||
63ebb9fa MY |
873 | static void vop_crtc_wait_for_update(struct drm_crtc *crtc) |
874 | { | |
875 | struct vop *vop = to_vop(crtc); | |
876 | ||
877 | reinit_completion(&vop->wait_update_complete); | |
878 | WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); | |
879 | } | |
880 | ||
2048e328 MY |
881 | static const struct rockchip_crtc_funcs private_crtc_funcs = { |
882 | .enable_vblank = vop_crtc_enable_vblank, | |
883 | .disable_vblank = vop_crtc_disable_vblank, | |
63ebb9fa | 884 | .wait_for_update = vop_crtc_wait_for_update, |
2048e328 MY |
885 | }; |
886 | ||
2048e328 MY |
887 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
888 | const struct drm_display_mode *mode, | |
889 | struct drm_display_mode *adjusted_mode) | |
890 | { | |
b59b8de3 CZ |
891 | struct vop *vop = to_vop(crtc); |
892 | ||
b59b8de3 CZ |
893 | adjusted_mode->clock = |
894 | clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; | |
895 | ||
2048e328 MY |
896 | return true; |
897 | } | |
898 | ||
63ebb9fa | 899 | static void vop_crtc_enable(struct drm_crtc *crtc) |
2048e328 MY |
900 | { |
901 | struct vop *vop = to_vop(crtc); | |
4e257d9e | 902 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); |
63ebb9fa | 903 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
904 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
905 | u16 hdisplay = adjusted_mode->hdisplay; | |
906 | u16 htotal = adjusted_mode->htotal; | |
907 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
908 | u16 hact_end = hact_st + hdisplay; | |
909 | u16 vdisplay = adjusted_mode->vdisplay; | |
910 | u16 vtotal = adjusted_mode->vtotal; | |
911 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
912 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
913 | u16 vact_end = vact_st + vdisplay; | |
2048e328 MY |
914 | uint32_t val; |
915 | ||
893b6cad DV |
916 | WARN_ON(vop->event); |
917 | ||
63ebb9fa | 918 | vop_enable(crtc); |
2048e328 | 919 | /* |
ce3887ed MY |
920 | * If dclk rate is zero, mean that scanout is stop, |
921 | * we don't need wait any more. | |
2048e328 | 922 | */ |
ce3887ed MY |
923 | if (clk_get_rate(vop->dclk)) { |
924 | /* | |
925 | * Rk3288 vop timing register is immediately, when configure | |
926 | * display timing on display time, may cause tearing. | |
927 | * | |
928 | * Vop standby will take effect at end of current frame, | |
929 | * if dsp hold valid irq happen, it means standby complete. | |
930 | * | |
931 | * mode set: | |
932 | * standby and wait complete --> |---- | |
933 | * | display time | |
934 | * |---- | |
935 | * |---> dsp hold irq | |
936 | * configure display timing --> | | |
937 | * standby exit | | |
938 | * | new frame start. | |
939 | */ | |
940 | ||
941 | reinit_completion(&vop->dsp_hold_completion); | |
942 | vop_dsp_hold_valid_irq_enable(vop); | |
943 | ||
944 | spin_lock(&vop->reg_lock); | |
945 | ||
946 | VOP_CTRL_SET(vop, standby, 1); | |
947 | ||
948 | spin_unlock(&vop->reg_lock); | |
949 | ||
950 | wait_for_completion(&vop->dsp_hold_completion); | |
951 | ||
952 | vop_dsp_hold_valid_irq_disable(vop); | |
953 | } | |
2048e328 | 954 | |
2048e328 | 955 | val = 0x8; |
44ddb7ef MY |
956 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; |
957 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); | |
2048e328 | 958 | VOP_CTRL_SET(vop, pin_pol, val); |
4e257d9e MY |
959 | switch (s->output_type) { |
960 | case DRM_MODE_CONNECTOR_LVDS: | |
961 | VOP_CTRL_SET(vop, rgb_en, 1); | |
962 | break; | |
963 | case DRM_MODE_CONNECTOR_eDP: | |
964 | VOP_CTRL_SET(vop, edp_en, 1); | |
965 | break; | |
966 | case DRM_MODE_CONNECTOR_HDMIA: | |
967 | VOP_CTRL_SET(vop, hdmi_en, 1); | |
968 | break; | |
969 | case DRM_MODE_CONNECTOR_DSI: | |
970 | VOP_CTRL_SET(vop, mipi_en, 1); | |
971 | break; | |
972 | default: | |
973 | DRM_ERROR("unsupport connector_type[%d]\n", s->output_type); | |
974 | } | |
975 | VOP_CTRL_SET(vop, out_mode, s->output_mode); | |
2048e328 MY |
976 | |
977 | VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); | |
978 | val = hact_st << 16; | |
979 | val |= hact_end; | |
980 | VOP_CTRL_SET(vop, hact_st_end, val); | |
981 | VOP_CTRL_SET(vop, hpost_st_end, val); | |
982 | ||
983 | VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); | |
984 | val = vact_st << 16; | |
985 | val |= vact_end; | |
986 | VOP_CTRL_SET(vop, vact_st_end, val); | |
987 | VOP_CTRL_SET(vop, vpost_st_end, val); | |
988 | ||
2048e328 | 989 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed MY |
990 | |
991 | VOP_CTRL_SET(vop, standby, 0); | |
2048e328 MY |
992 | } |
993 | ||
63ebb9fa MY |
994 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
995 | struct drm_crtc_state *old_crtc_state) | |
2048e328 MY |
996 | { |
997 | struct vop *vop = to_vop(crtc); | |
2048e328 | 998 | |
63ebb9fa MY |
999 | if (WARN_ON(!vop->is_enabled)) |
1000 | return; | |
2048e328 | 1001 | |
63ebb9fa | 1002 | spin_lock(&vop->reg_lock); |
2048e328 | 1003 | |
63ebb9fa | 1004 | vop_cfg_done(vop); |
2048e328 | 1005 | |
63ebb9fa | 1006 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
1007 | } |
1008 | ||
63ebb9fa MY |
1009 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
1010 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 1011 | { |
63ebb9fa | 1012 | struct vop *vop = to_vop(crtc); |
2048e328 | 1013 | |
893b6cad | 1014 | spin_lock_irq(&crtc->dev->event_lock); |
63ebb9fa MY |
1015 | if (crtc->state->event) { |
1016 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
893b6cad | 1017 | WARN_ON(vop->event); |
2048e328 | 1018 | |
63ebb9fa MY |
1019 | vop->event = crtc->state->event; |
1020 | crtc->state->event = NULL; | |
1021 | } | |
893b6cad | 1022 | spin_unlock_irq(&crtc->dev->event_lock); |
2048e328 MY |
1023 | } |
1024 | ||
63ebb9fa MY |
1025 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
1026 | .enable = vop_crtc_enable, | |
1027 | .disable = vop_crtc_disable, | |
1028 | .mode_fixup = vop_crtc_mode_fixup, | |
1029 | .atomic_flush = vop_crtc_atomic_flush, | |
1030 | .atomic_begin = vop_crtc_atomic_begin, | |
1031 | }; | |
1032 | ||
2048e328 MY |
1033 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
1034 | { | |
1035 | drm_crtc_cleanup(crtc); | |
1036 | } | |
1037 | ||
dc0b408f JK |
1038 | static void vop_crtc_reset(struct drm_crtc *crtc) |
1039 | { | |
1040 | if (crtc->state) | |
1041 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
1042 | kfree(crtc->state); | |
1043 | ||
1044 | crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); | |
1045 | if (crtc->state) | |
1046 | crtc->state->crtc = crtc; | |
1047 | } | |
1048 | ||
4e257d9e MY |
1049 | static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) |
1050 | { | |
1051 | struct rockchip_crtc_state *rockchip_state; | |
1052 | ||
1053 | rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); | |
1054 | if (!rockchip_state) | |
1055 | return NULL; | |
1056 | ||
1057 | __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); | |
1058 | return &rockchip_state->base; | |
1059 | } | |
1060 | ||
1061 | static void vop_crtc_destroy_state(struct drm_crtc *crtc, | |
1062 | struct drm_crtc_state *state) | |
1063 | { | |
1064 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); | |
1065 | ||
ec2dc6a0 | 1066 | __drm_atomic_helper_crtc_destroy_state(&s->base); |
4e257d9e MY |
1067 | kfree(s); |
1068 | } | |
1069 | ||
2048e328 | 1070 | static const struct drm_crtc_funcs vop_crtc_funcs = { |
63ebb9fa MY |
1071 | .set_config = drm_atomic_helper_set_config, |
1072 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 1073 | .destroy = vop_crtc_destroy, |
dc0b408f | 1074 | .reset = vop_crtc_reset, |
4e257d9e MY |
1075 | .atomic_duplicate_state = vop_crtc_duplicate_state, |
1076 | .atomic_destroy_state = vop_crtc_destroy_state, | |
2048e328 MY |
1077 | }; |
1078 | ||
63ebb9fa | 1079 | static bool vop_win_pending_is_complete(struct vop_win *vop_win) |
2048e328 | 1080 | { |
63ebb9fa | 1081 | dma_addr_t yrgb_mst; |
2048e328 | 1082 | |
4f9d39a7 | 1083 | if (!vop_win->enable) |
63ebb9fa | 1084 | return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; |
2048e328 | 1085 | |
63ebb9fa | 1086 | yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); |
2048e328 | 1087 | |
4f9d39a7 | 1088 | return yrgb_mst == vop_win->yrgb_mst; |
2048e328 MY |
1089 | } |
1090 | ||
63ebb9fa | 1091 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1092 | { |
63ebb9fa MY |
1093 | struct drm_device *drm = vop->drm_dev; |
1094 | struct drm_crtc *crtc = &vop->crtc; | |
1095 | unsigned long flags; | |
1096 | int i; | |
2048e328 | 1097 | |
63ebb9fa MY |
1098 | for (i = 0; i < vop->data->win_size; i++) { |
1099 | if (!vop_win_pending_is_complete(&vop->win[i])) | |
1100 | return; | |
2048e328 MY |
1101 | } |
1102 | ||
893b6cad | 1103 | spin_lock_irqsave(&drm->event_lock, flags); |
63ebb9fa | 1104 | if (vop->event) { |
2048e328 | 1105 | |
63ebb9fa MY |
1106 | drm_crtc_send_vblank_event(crtc, vop->event); |
1107 | drm_crtc_vblank_put(crtc); | |
1108 | vop->event = NULL; | |
2048e328 | 1109 | |
2048e328 | 1110 | } |
893b6cad DV |
1111 | spin_unlock_irqrestore(&drm->event_lock, flags); |
1112 | ||
63ebb9fa MY |
1113 | if (!completion_done(&vop->wait_update_complete)) |
1114 | complete(&vop->wait_update_complete); | |
2048e328 MY |
1115 | } |
1116 | ||
1117 | static irqreturn_t vop_isr(int irq, void *data) | |
1118 | { | |
1119 | struct vop *vop = data; | |
b5f7b755 | 1120 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1121 | uint32_t active_irqs; |
2048e328 | 1122 | unsigned long flags; |
1067219b | 1123 | int ret = IRQ_NONE; |
2048e328 MY |
1124 | |
1125 | /* | |
dbb3d944 | 1126 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1127 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1128 | */ | |
1129 | spin_lock_irqsave(&vop->irq_lock, flags); | |
dbb3d944 MY |
1130 | |
1131 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1132 | /* Clear all active interrupt sources */ |
1133 | if (active_irqs) | |
dbb3d944 MY |
1134 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1135 | ||
2048e328 MY |
1136 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1137 | ||
1138 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1139 | if (!active_irqs) | |
1140 | return IRQ_NONE; | |
1141 | ||
1067219b MY |
1142 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1143 | complete(&vop->dsp_hold_completion); | |
1144 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1145 | ret = IRQ_HANDLED; | |
2048e328 MY |
1146 | } |
1147 | ||
1067219b | 1148 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1149 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1150 | vop_handle_vblank(vop); |
1067219b | 1151 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1152 | ret = IRQ_HANDLED; |
1067219b | 1153 | } |
2048e328 | 1154 | |
1067219b MY |
1155 | /* Unhandled irqs are spurious. */ |
1156 | if (active_irqs) | |
1157 | DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); | |
1158 | ||
1159 | return ret; | |
2048e328 MY |
1160 | } |
1161 | ||
1162 | static int vop_create_crtc(struct vop *vop) | |
1163 | { | |
1164 | const struct vop_data *vop_data = vop->data; | |
1165 | struct device *dev = vop->dev; | |
1166 | struct drm_device *drm_dev = vop->drm_dev; | |
328b51c0 | 1167 | struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; |
2048e328 MY |
1168 | struct drm_crtc *crtc = &vop->crtc; |
1169 | struct device_node *port; | |
1170 | int ret; | |
1171 | int i; | |
1172 | ||
1173 | /* | |
1174 | * Create drm_plane for primary and cursor planes first, since we need | |
1175 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1176 | * "possible_crtcs" to the newly initialized crtc. | |
1177 | */ | |
1178 | for (i = 0; i < vop_data->win_size; i++) { | |
1179 | struct vop_win *vop_win = &vop->win[i]; | |
1180 | const struct vop_win_data *win_data = vop_win->data; | |
1181 | ||
1182 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1183 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1184 | continue; | |
1185 | ||
1186 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1187 | 0, &vop_plane_funcs, | |
1188 | win_data->phy->data_formats, | |
1189 | win_data->phy->nformats, | |
b0b3b795 | 1190 | win_data->type, NULL); |
2048e328 MY |
1191 | if (ret) { |
1192 | DRM_ERROR("failed to initialize plane\n"); | |
1193 | goto err_cleanup_planes; | |
1194 | } | |
1195 | ||
1196 | plane = &vop_win->base; | |
63ebb9fa | 1197 | drm_plane_helper_add(plane, &plane_helper_funcs); |
2048e328 MY |
1198 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1199 | primary = plane; | |
1200 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1201 | cursor = plane; | |
1202 | } | |
1203 | ||
1204 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1205 | &vop_crtc_funcs, NULL); |
2048e328 | 1206 | if (ret) |
328b51c0 | 1207 | goto err_cleanup_planes; |
2048e328 MY |
1208 | |
1209 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1210 | ||
1211 | /* | |
1212 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1213 | * to the newly created crtc. | |
1214 | */ | |
1215 | for (i = 0; i < vop_data->win_size; i++) { | |
1216 | struct vop_win *vop_win = &vop->win[i]; | |
1217 | const struct vop_win_data *win_data = vop_win->data; | |
1218 | unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); | |
1219 | ||
1220 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1221 | continue; | |
1222 | ||
1223 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1224 | possible_crtcs, | |
1225 | &vop_plane_funcs, | |
1226 | win_data->phy->data_formats, | |
1227 | win_data->phy->nformats, | |
b0b3b795 | 1228 | win_data->type, NULL); |
2048e328 MY |
1229 | if (ret) { |
1230 | DRM_ERROR("failed to initialize overlay plane\n"); | |
1231 | goto err_cleanup_crtc; | |
1232 | } | |
63ebb9fa | 1233 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
2048e328 MY |
1234 | } |
1235 | ||
1236 | port = of_get_child_by_name(dev->of_node, "port"); | |
1237 | if (!port) { | |
1238 | DRM_ERROR("no port node found in %s\n", | |
1239 | dev->of_node->full_name); | |
328b51c0 | 1240 | ret = -ENOENT; |
2048e328 MY |
1241 | goto err_cleanup_crtc; |
1242 | } | |
1243 | ||
1067219b | 1244 | init_completion(&vop->dsp_hold_completion); |
63ebb9fa | 1245 | init_completion(&vop->wait_update_complete); |
2048e328 | 1246 | crtc->port = port; |
b5f7b755 | 1247 | rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); |
2048e328 MY |
1248 | |
1249 | return 0; | |
1250 | ||
1251 | err_cleanup_crtc: | |
1252 | drm_crtc_cleanup(crtc); | |
1253 | err_cleanup_planes: | |
328b51c0 DA |
1254 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, |
1255 | head) | |
2048e328 MY |
1256 | drm_plane_cleanup(plane); |
1257 | return ret; | |
1258 | } | |
1259 | ||
1260 | static void vop_destroy_crtc(struct vop *vop) | |
1261 | { | |
1262 | struct drm_crtc *crtc = &vop->crtc; | |
328b51c0 DA |
1263 | struct drm_device *drm_dev = vop->drm_dev; |
1264 | struct drm_plane *plane, *tmp; | |
2048e328 | 1265 | |
b5f7b755 | 1266 | rockchip_unregister_crtc_funcs(crtc); |
2048e328 | 1267 | of_node_put(crtc->port); |
328b51c0 DA |
1268 | |
1269 | /* | |
1270 | * We need to cleanup the planes now. Why? | |
1271 | * | |
1272 | * The planes are "&vop->win[i].base". That means the memory is | |
1273 | * all part of the big "struct vop" chunk of memory. That memory | |
1274 | * was devm allocated and associated with this component. We need to | |
1275 | * free it ourselves before vop_unbind() finishes. | |
1276 | */ | |
1277 | list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, | |
1278 | head) | |
1279 | vop_plane_destroy(plane); | |
1280 | ||
1281 | /* | |
1282 | * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() | |
1283 | * references the CRTC. | |
1284 | */ | |
2048e328 MY |
1285 | drm_crtc_cleanup(crtc); |
1286 | } | |
1287 | ||
1288 | static int vop_initial(struct vop *vop) | |
1289 | { | |
1290 | const struct vop_data *vop_data = vop->data; | |
1291 | const struct vop_reg_data *init_table = vop_data->init_table; | |
1292 | struct reset_control *ahb_rst; | |
1293 | int i, ret; | |
1294 | ||
1295 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1296 | if (IS_ERR(vop->hclk)) { | |
1297 | dev_err(vop->dev, "failed to get hclk source\n"); | |
1298 | return PTR_ERR(vop->hclk); | |
1299 | } | |
1300 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1301 | if (IS_ERR(vop->aclk)) { | |
1302 | dev_err(vop->dev, "failed to get aclk source\n"); | |
1303 | return PTR_ERR(vop->aclk); | |
1304 | } | |
1305 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1306 | if (IS_ERR(vop->dclk)) { | |
1307 | dev_err(vop->dev, "failed to get dclk source\n"); | |
1308 | return PTR_ERR(vop->dclk); | |
1309 | } | |
1310 | ||
2048e328 MY |
1311 | ret = clk_prepare(vop->dclk); |
1312 | if (ret < 0) { | |
1313 | dev_err(vop->dev, "failed to prepare dclk\n"); | |
d7b53fd9 | 1314 | return ret; |
2048e328 MY |
1315 | } |
1316 | ||
d7b53fd9 SS |
1317 | /* Enable both the hclk and aclk to setup the vop */ |
1318 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1319 | if (ret < 0) { |
d7b53fd9 | 1320 | dev_err(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1321 | goto err_unprepare_dclk; |
1322 | } | |
1323 | ||
d7b53fd9 | 1324 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1325 | if (ret < 0) { |
d7b53fd9 SS |
1326 | dev_err(vop->dev, "failed to prepare/enable aclk\n"); |
1327 | goto err_disable_hclk; | |
2048e328 | 1328 | } |
d7b53fd9 | 1329 | |
2048e328 MY |
1330 | /* |
1331 | * do hclk_reset, reset all vop registers. | |
1332 | */ | |
1333 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1334 | if (IS_ERR(ahb_rst)) { | |
1335 | dev_err(vop->dev, "failed to get ahb reset\n"); | |
1336 | ret = PTR_ERR(ahb_rst); | |
d7b53fd9 | 1337 | goto err_disable_aclk; |
2048e328 MY |
1338 | } |
1339 | reset_control_assert(ahb_rst); | |
1340 | usleep_range(10, 20); | |
1341 | reset_control_deassert(ahb_rst); | |
1342 | ||
1343 | memcpy(vop->regsbak, vop->regs, vop->len); | |
1344 | ||
1345 | for (i = 0; i < vop_data->table_size; i++) | |
1346 | vop_writel(vop, init_table[i].offset, init_table[i].value); | |
1347 | ||
1348 | for (i = 0; i < vop_data->win_size; i++) { | |
1349 | const struct vop_win_data *win = &vop_data->win[i]; | |
1350 | ||
1351 | VOP_WIN_SET(vop, win, enable, 0); | |
1352 | } | |
1353 | ||
1354 | vop_cfg_done(vop); | |
1355 | ||
1356 | /* | |
1357 | * do dclk_reset, let all config take affect. | |
1358 | */ | |
1359 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1360 | if (IS_ERR(vop->dclk_rst)) { | |
1361 | dev_err(vop->dev, "failed to get dclk reset\n"); | |
1362 | ret = PTR_ERR(vop->dclk_rst); | |
d7b53fd9 | 1363 | goto err_disable_aclk; |
2048e328 MY |
1364 | } |
1365 | reset_control_assert(vop->dclk_rst); | |
1366 | usleep_range(10, 20); | |
1367 | reset_control_deassert(vop->dclk_rst); | |
1368 | ||
1369 | clk_disable(vop->hclk); | |
d7b53fd9 | 1370 | clk_disable(vop->aclk); |
2048e328 | 1371 | |
31e980c5 | 1372 | vop->is_enabled = false; |
2048e328 MY |
1373 | |
1374 | return 0; | |
1375 | ||
d7b53fd9 SS |
1376 | err_disable_aclk: |
1377 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1378 | err_disable_hclk: |
d7b53fd9 | 1379 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1380 | err_unprepare_dclk: |
1381 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1382 | return ret; |
1383 | } | |
1384 | ||
1385 | /* | |
1386 | * Initialize the vop->win array elements. | |
1387 | */ | |
1388 | static void vop_win_init(struct vop *vop) | |
1389 | { | |
1390 | const struct vop_data *vop_data = vop->data; | |
1391 | unsigned int i; | |
1392 | ||
1393 | for (i = 0; i < vop_data->win_size; i++) { | |
1394 | struct vop_win *vop_win = &vop->win[i]; | |
1395 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1396 | ||
1397 | vop_win->data = win_data; | |
1398 | vop_win->vop = vop; | |
2048e328 MY |
1399 | } |
1400 | } | |
1401 | ||
1402 | static int vop_bind(struct device *dev, struct device *master, void *data) | |
1403 | { | |
1404 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1405 | const struct vop_data *vop_data; |
1406 | struct drm_device *drm_dev = data; | |
1407 | struct vop *vop; | |
1408 | struct resource *res; | |
1409 | size_t alloc_size; | |
3ea68922 | 1410 | int ret, irq; |
2048e328 | 1411 | |
a67719d1 | 1412 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1413 | if (!vop_data) |
1414 | return -ENODEV; | |
1415 | ||
1416 | /* Allocate vop struct and its vop_win array */ | |
1417 | alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; | |
1418 | vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); | |
1419 | if (!vop) | |
1420 | return -ENOMEM; | |
1421 | ||
1422 | vop->dev = dev; | |
1423 | vop->data = vop_data; | |
1424 | vop->drm_dev = drm_dev; | |
1425 | dev_set_drvdata(dev, vop); | |
1426 | ||
1427 | vop_win_init(vop); | |
1428 | ||
1429 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1430 | vop->len = resource_size(res); | |
1431 | vop->regs = devm_ioremap_resource(dev, res); | |
1432 | if (IS_ERR(vop->regs)) | |
1433 | return PTR_ERR(vop->regs); | |
1434 | ||
1435 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1436 | if (!vop->regsbak) | |
1437 | return -ENOMEM; | |
1438 | ||
1439 | ret = vop_initial(vop); | |
1440 | if (ret < 0) { | |
1441 | dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); | |
1442 | return ret; | |
1443 | } | |
1444 | ||
3ea68922 HS |
1445 | irq = platform_get_irq(pdev, 0); |
1446 | if (irq < 0) { | |
2048e328 | 1447 | dev_err(dev, "cannot find irq for vop\n"); |
3ea68922 | 1448 | return irq; |
2048e328 | 1449 | } |
3ea68922 | 1450 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1451 | |
1452 | spin_lock_init(&vop->reg_lock); | |
1453 | spin_lock_init(&vop->irq_lock); | |
1454 | ||
1455 | mutex_init(&vop->vsync_mutex); | |
1456 | ||
63ebb9fa MY |
1457 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1458 | IRQF_SHARED, dev_name(dev), vop); | |
2048e328 MY |
1459 | if (ret) |
1460 | return ret; | |
1461 | ||
1462 | /* IRQ is initially disabled; it gets enabled in power_on */ | |
1463 | disable_irq(vop->irq); | |
1464 | ||
1465 | ret = vop_create_crtc(vop); | |
1466 | if (ret) | |
1467 | return ret; | |
1468 | ||
1469 | pm_runtime_enable(&pdev->dev); | |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1474 | { | |
1475 | struct vop *vop = dev_get_drvdata(dev); | |
1476 | ||
1477 | pm_runtime_disable(dev); | |
1478 | vop_destroy_crtc(vop); | |
1479 | } | |
1480 | ||
a67719d1 | 1481 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1482 | .bind = vop_bind, |
1483 | .unbind = vop_unbind, | |
1484 | }; | |
54255e81 | 1485 | EXPORT_SYMBOL_GPL(vop_component_ops); |