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51c13278 LP |
1 | /* |
2 | * shmob_drm_regs.h -- SH Mobile DRM registers | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Corporation | |
5 | * | |
6 | * Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #ifndef __SHMOB_DRM_REGS_H__ | |
15 | #define __SHMOB_DRM_REGS_H__ | |
16 | ||
17 | #include <linux/io.h> | |
18 | ||
19 | /* Register definitions */ | |
20 | #define LDDCKPAT1R 0x400 | |
21 | #define LDDCKPAT2R 0x404 | |
22 | #define LDDCKR 0x410 | |
23 | #define LDDCKR_ICKSEL_BUS (0 << 16) | |
24 | #define LDDCKR_ICKSEL_MIPI (1 << 16) | |
25 | #define LDDCKR_ICKSEL_HDMI (2 << 16) | |
26 | #define LDDCKR_ICKSEL_EXT (3 << 16) | |
27 | #define LDDCKR_ICKSEL_MASK (7 << 16) | |
28 | #define LDDCKR_MOSEL (1 << 6) | |
29 | #define LDDCKSTPR 0x414 | |
30 | #define LDDCKSTPR_DCKSTS (1 << 16) | |
31 | #define LDDCKSTPR_DCKSTP (1 << 0) | |
32 | #define LDMT1R 0x418 | |
33 | #define LDMT1R_VPOL (1 << 28) | |
34 | #define LDMT1R_HPOL (1 << 27) | |
35 | #define LDMT1R_DWPOL (1 << 26) | |
36 | #define LDMT1R_DIPOL (1 << 25) | |
37 | #define LDMT1R_DAPOL (1 << 24) | |
38 | #define LDMT1R_HSCNT (1 << 17) | |
39 | #define LDMT1R_DWCNT (1 << 16) | |
40 | #define LDMT1R_IFM (1 << 12) | |
41 | #define LDMT1R_MIFTYP_RGB8 (0x0 << 0) | |
42 | #define LDMT1R_MIFTYP_RGB9 (0x4 << 0) | |
43 | #define LDMT1R_MIFTYP_RGB12A (0x5 << 0) | |
44 | #define LDMT1R_MIFTYP_RGB12B (0x6 << 0) | |
45 | #define LDMT1R_MIFTYP_RGB16 (0x7 << 0) | |
46 | #define LDMT1R_MIFTYP_RGB18 (0xa << 0) | |
47 | #define LDMT1R_MIFTYP_RGB24 (0xb << 0) | |
48 | #define LDMT1R_MIFTYP_YCBCR (0xf << 0) | |
49 | #define LDMT1R_MIFTYP_SYS8A (0x0 << 0) | |
50 | #define LDMT1R_MIFTYP_SYS8B (0x1 << 0) | |
51 | #define LDMT1R_MIFTYP_SYS8C (0x2 << 0) | |
52 | #define LDMT1R_MIFTYP_SYS8D (0x3 << 0) | |
53 | #define LDMT1R_MIFTYP_SYS9 (0x4 << 0) | |
54 | #define LDMT1R_MIFTYP_SYS12 (0x5 << 0) | |
55 | #define LDMT1R_MIFTYP_SYS16A (0x7 << 0) | |
56 | #define LDMT1R_MIFTYP_SYS16B (0x8 << 0) | |
57 | #define LDMT1R_MIFTYP_SYS16C (0x9 << 0) | |
58 | #define LDMT1R_MIFTYP_SYS18 (0xa << 0) | |
59 | #define LDMT1R_MIFTYP_SYS24 (0xb << 0) | |
60 | #define LDMT1R_MIFTYP_MASK (0xf << 0) | |
61 | #define LDMT2R 0x41c | |
62 | #define LDMT2R_CSUP_MASK (7 << 26) | |
63 | #define LDMT2R_CSUP_SHIFT 26 | |
64 | #define LDMT2R_RSV (1 << 25) | |
65 | #define LDMT2R_VSEL (1 << 24) | |
66 | #define LDMT2R_WCSC_MASK (0xff << 16) | |
67 | #define LDMT2R_WCSC_SHIFT 16 | |
68 | #define LDMT2R_WCEC_MASK (0xff << 8) | |
69 | #define LDMT2R_WCEC_SHIFT 8 | |
70 | #define LDMT2R_WCLW_MASK (0xff << 0) | |
71 | #define LDMT2R_WCLW_SHIFT 0 | |
72 | #define LDMT3R 0x420 | |
73 | #define LDMT3R_RDLC_MASK (0x3f << 24) | |
74 | #define LDMT3R_RDLC_SHIFT 24 | |
75 | #define LDMT3R_RCSC_MASK (0xff << 16) | |
76 | #define LDMT3R_RCSC_SHIFT 16 | |
77 | #define LDMT3R_RCEC_MASK (0xff << 8) | |
78 | #define LDMT3R_RCEC_SHIFT 8 | |
79 | #define LDMT3R_RCLW_MASK (0xff << 0) | |
80 | #define LDMT3R_RCLW_SHIFT 0 | |
81 | #define LDDFR 0x424 | |
82 | #define LDDFR_CF1 (1 << 18) | |
83 | #define LDDFR_CF0 (1 << 17) | |
84 | #define LDDFR_CC (1 << 16) | |
85 | #define LDDFR_YF_420 (0 << 8) | |
86 | #define LDDFR_YF_422 (1 << 8) | |
87 | #define LDDFR_YF_444 (2 << 8) | |
88 | #define LDDFR_YF_MASK (3 << 8) | |
89 | #define LDDFR_PKF_ARGB32 (0x00 << 0) | |
90 | #define LDDFR_PKF_RGB16 (0x03 << 0) | |
91 | #define LDDFR_PKF_RGB24 (0x0b << 0) | |
92 | #define LDDFR_PKF_MASK (0x1f << 0) | |
93 | #define LDSM1R 0x428 | |
94 | #define LDSM1R_OS (1 << 0) | |
95 | #define LDSM2R 0x42c | |
96 | #define LDSM2R_OSTRG (1 << 0) | |
97 | #define LDSA1R 0x430 | |
98 | #define LDSA2R 0x434 | |
99 | #define LDMLSR 0x438 | |
100 | #define LDWBFR 0x43c | |
101 | #define LDWBCNTR 0x440 | |
102 | #define LDWBAR 0x444 | |
103 | #define LDHCNR 0x448 | |
104 | #define LDHSYNR 0x44c | |
105 | #define LDVLNR 0x450 | |
106 | #define LDVSYNR 0x454 | |
107 | #define LDHPDR 0x458 | |
108 | #define LDVPDR 0x45c | |
109 | #define LDPMR 0x460 | |
110 | #define LDPMR_LPS (3 << 0) | |
111 | #define LDINTR 0x468 | |
112 | #define LDINTR_FE (1 << 10) | |
113 | #define LDINTR_VSE (1 << 9) | |
114 | #define LDINTR_VEE (1 << 8) | |
115 | #define LDINTR_FS (1 << 2) | |
116 | #define LDINTR_VSS (1 << 1) | |
117 | #define LDINTR_VES (1 << 0) | |
118 | #define LDINTR_STATUS_MASK (0xff << 0) | |
119 | #define LDSR 0x46c | |
120 | #define LDSR_MSS (1 << 10) | |
121 | #define LDSR_MRS (1 << 8) | |
122 | #define LDSR_AS (1 << 1) | |
123 | #define LDCNT1R 0x470 | |
124 | #define LDCNT1R_DE (1 << 0) | |
125 | #define LDCNT2R 0x474 | |
126 | #define LDCNT2R_BR (1 << 8) | |
127 | #define LDCNT2R_MD (1 << 3) | |
128 | #define LDCNT2R_SE (1 << 2) | |
129 | #define LDCNT2R_ME (1 << 1) | |
130 | #define LDCNT2R_DO (1 << 0) | |
131 | #define LDRCNTR 0x478 | |
132 | #define LDRCNTR_SRS (1 << 17) | |
133 | #define LDRCNTR_SRC (1 << 16) | |
134 | #define LDRCNTR_MRS (1 << 1) | |
135 | #define LDRCNTR_MRC (1 << 0) | |
136 | #define LDDDSR 0x47c | |
137 | #define LDDDSR_LS (1 << 2) | |
138 | #define LDDDSR_WS (1 << 1) | |
139 | #define LDDDSR_BS (1 << 0) | |
140 | #define LDHAJR 0x4a0 | |
141 | ||
142 | #define LDDWD0R 0x800 | |
143 | #define LDDWDxR_WDACT (1 << 28) | |
144 | #define LDDWDxR_RSW (1 << 24) | |
145 | #define LDDRDR 0x840 | |
146 | #define LDDRDR_RSR (1 << 24) | |
147 | #define LDDRDR_DRD_MASK (0x3ffff << 0) | |
148 | #define LDDWAR 0x900 | |
149 | #define LDDWAR_WA (1 << 0) | |
150 | #define LDDRAR 0x904 | |
151 | #define LDDRAR_RA (1 << 0) | |
152 | ||
153 | #define LDBCR 0xb00 | |
154 | #define LDBCR_UPC(n) (1 << ((n) + 16)) | |
155 | #define LDBCR_UPF(n) (1 << ((n) + 8)) | |
156 | #define LDBCR_UPD(n) (1 << ((n) + 0)) | |
157 | #define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00) | |
158 | #define LDBBSIFR_EN (1 << 31) | |
159 | #define LDBBSIFR_VS (1 << 29) | |
160 | #define LDBBSIFR_BRSEL (1 << 28) | |
161 | #define LDBBSIFR_MX (1 << 27) | |
162 | #define LDBBSIFR_MY (1 << 26) | |
163 | #define LDBBSIFR_CV3 (3 << 24) | |
164 | #define LDBBSIFR_CV2 (2 << 24) | |
165 | #define LDBBSIFR_CV1 (1 << 24) | |
166 | #define LDBBSIFR_CV0 (0 << 24) | |
167 | #define LDBBSIFR_CV_MASK (3 << 24) | |
168 | #define LDBBSIFR_LAY_MASK (0xff << 16) | |
169 | #define LDBBSIFR_LAY_SHIFT 16 | |
170 | #define LDBBSIFR_ROP3_MASK (0xff << 16) | |
171 | #define LDBBSIFR_ROP3_SHIFT 16 | |
172 | #define LDBBSIFR_AL_PL8 (3 << 14) | |
173 | #define LDBBSIFR_AL_PL1 (2 << 14) | |
174 | #define LDBBSIFR_AL_PK (1 << 14) | |
175 | #define LDBBSIFR_AL_1 (0 << 14) | |
176 | #define LDBBSIFR_AL_MASK (3 << 14) | |
177 | #define LDBBSIFR_SWPL (1 << 10) | |
178 | #define LDBBSIFR_SWPW (1 << 9) | |
179 | #define LDBBSIFR_SWPB (1 << 8) | |
180 | #define LDBBSIFR_RY (1 << 7) | |
181 | #define LDBBSIFR_CHRR_420 (2 << 0) | |
182 | #define LDBBSIFR_CHRR_422 (1 << 0) | |
183 | #define LDBBSIFR_CHRR_444 (0 << 0) | |
184 | #define LDBBSIFR_RPKF_ARGB32 (0x00 << 0) | |
185 | #define LDBBSIFR_RPKF_RGB16 (0x03 << 0) | |
186 | #define LDBBSIFR_RPKF_RGB24 (0x0b << 0) | |
187 | #define LDBBSIFR_RPKF_MASK (0x1f << 0) | |
188 | #define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04) | |
189 | #define LDBBSSZR_BVSS_MASK (0xfff << 16) | |
190 | #define LDBBSSZR_BVSS_SHIFT 16 | |
191 | #define LDBBSSZR_BHSS_MASK (0xfff << 0) | |
192 | #define LDBBSSZR_BHSS_SHIFT 0 | |
193 | #define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08) | |
194 | #define LDBBLOCR_CVLC_MASK (0xfff << 16) | |
195 | #define LDBBLOCR_CVLC_SHIFT 16 | |
196 | #define LDBBLOCR_CHLC_MASK (0xfff << 0) | |
197 | #define LDBBLOCR_CHLC_SHIFT 0 | |
198 | #define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c) | |
199 | #define LDBBSMWR_BSMWA_MASK (0xffff << 16) | |
200 | #define LDBBSMWR_BSMWA_SHIFT 16 | |
201 | #define LDBBSMWR_BSMW_MASK (0xffff << 0) | |
202 | #define LDBBSMWR_BSMW_SHIFT 0 | |
203 | #define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10) | |
204 | #define LDBBSAYR_FG1A_MASK (0xff << 24) | |
205 | #define LDBBSAYR_FG1A_SHIFT 24 | |
206 | #define LDBBSAYR_FG1R_MASK (0xff << 16) | |
207 | #define LDBBSAYR_FG1R_SHIFT 16 | |
208 | #define LDBBSAYR_FG1G_MASK (0xff << 8) | |
209 | #define LDBBSAYR_FG1G_SHIFT 8 | |
210 | #define LDBBSAYR_FG1B_MASK (0xff << 0) | |
211 | #define LDBBSAYR_FG1B_SHIFT 0 | |
212 | #define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14) | |
213 | #define LDBBSACR_FG2A_MASK (0xff << 24) | |
214 | #define LDBBSACR_FG2A_SHIFT 24 | |
215 | #define LDBBSACR_FG2R_MASK (0xff << 16) | |
216 | #define LDBBSACR_FG2R_SHIFT 16 | |
217 | #define LDBBSACR_FG2G_MASK (0xff << 8) | |
218 | #define LDBBSACR_FG2G_SHIFT 8 | |
219 | #define LDBBSACR_FG2B_MASK (0xff << 0) | |
220 | #define LDBBSACR_FG2B_SHIFT 0 | |
221 | #define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18) | |
222 | #define LDBBSAAR_AP_MASK (0xff << 24) | |
223 | #define LDBBSAAR_AP_SHIFT 24 | |
224 | #define LDBBSAAR_R_MASK (0xff << 16) | |
225 | #define LDBBSAAR_R_SHIFT 16 | |
226 | #define LDBBSAAR_GY_MASK (0xff << 8) | |
227 | #define LDBBSAAR_GY_SHIFT 8 | |
228 | #define LDBBSAAR_B_MASK (0xff << 0) | |
229 | #define LDBBSAAR_B_SHIFT 0 | |
230 | #define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c) | |
231 | #define LDBBPPCR_AP_MASK (0xff << 24) | |
232 | #define LDBBPPCR_AP_SHIFT 24 | |
233 | #define LDBBPPCR_R_MASK (0xff << 16) | |
234 | #define LDBBPPCR_R_SHIFT 16 | |
235 | #define LDBBPPCR_GY_MASK (0xff << 8) | |
236 | #define LDBBPPCR_GY_SHIFT 8 | |
237 | #define LDBBPPCR_B_MASK (0xff << 0) | |
238 | #define LDBBPPCR_B_SHIFT 0 | |
239 | #define LDBnBBGCL(n) (0xb10 + (n) * 0x04) | |
240 | #define LDBBBGCL_BGA_MASK (0xff << 24) | |
241 | #define LDBBBGCL_BGA_SHIFT 24 | |
242 | #define LDBBBGCL_BGR_MASK (0xff << 16) | |
243 | #define LDBBBGCL_BGR_SHIFT 16 | |
244 | #define LDBBBGCL_BGG_MASK (0xff << 8) | |
245 | #define LDBBBGCL_BGG_SHIFT 8 | |
246 | #define LDBBBGCL_BGB_MASK (0xff << 0) | |
247 | #define LDBBBGCL_BGB_SHIFT 0 | |
248 | ||
249 | #define LCDC_SIDE_B_OFFSET 0x1000 | |
250 | #define LCDC_MIRROR_OFFSET 0x2000 | |
251 | ||
252 | static inline bool lcdc_is_banked(u32 reg) | |
253 | { | |
254 | switch (reg) { | |
255 | case LDMT1R: | |
256 | case LDMT2R: | |
257 | case LDMT3R: | |
258 | case LDDFR: | |
259 | case LDSM1R: | |
260 | case LDSA1R: | |
261 | case LDSA2R: | |
262 | case LDMLSR: | |
263 | case LDWBFR: | |
264 | case LDWBCNTR: | |
265 | case LDWBAR: | |
266 | case LDHCNR: | |
267 | case LDHSYNR: | |
268 | case LDVLNR: | |
269 | case LDVSYNR: | |
270 | case LDHPDR: | |
271 | case LDVPDR: | |
272 | case LDHAJR: | |
273 | return true; | |
274 | default: | |
275 | return reg >= LDBnBBGCL(0) && reg <= LDBnBPPCR(3); | |
276 | } | |
277 | } | |
278 | ||
279 | static inline void lcdc_write_mirror(struct shmob_drm_device *sdev, u32 reg, | |
280 | u32 data) | |
281 | { | |
282 | iowrite32(data, sdev->mmio + reg + LCDC_MIRROR_OFFSET); | |
283 | } | |
284 | ||
285 | static inline void lcdc_write(struct shmob_drm_device *sdev, u32 reg, u32 data) | |
286 | { | |
287 | iowrite32(data, sdev->mmio + reg); | |
288 | if (lcdc_is_banked(reg)) | |
289 | iowrite32(data, sdev->mmio + reg + LCDC_SIDE_B_OFFSET); | |
290 | } | |
291 | ||
292 | static inline u32 lcdc_read(struct shmob_drm_device *sdev, u32 reg) | |
293 | { | |
294 | return ioread32(sdev->mmio + reg); | |
295 | } | |
296 | ||
297 | static inline int lcdc_wait_bit(struct shmob_drm_device *sdev, u32 reg, | |
298 | u32 mask, u32 until) | |
299 | { | |
300 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
301 | ||
302 | while ((lcdc_read(sdev, reg) & mask) != until) { | |
303 | if (time_after(jiffies, timeout)) | |
304 | return -ETIMEDOUT; | |
305 | cpu_relax(); | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | #endif /* __SHMOB_DRM_REGS_H__ */ |