drm/amdkfd: Clean up inline handling
[deliverable/linux.git] / drivers / gpu / drm / sti / sti_crtc.c
CommitLineData
9bbf86fe
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1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Fabien Dessenne <fabien.dessenne@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
7 */
8
9#include <linux/clk.h>
10
11#include <drm/drmP.h>
de4b00b0
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12#include <drm/drm_atomic.h>
13#include <drm/drm_atomic_helper.h>
9bbf86fe 14#include <drm/drm_crtc_helper.h>
3cb9ae4f 15#include <drm/drm_plane_helper.h>
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16
17#include "sti_compositor.h"
9e1f05b2
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18#include "sti_crtc.h"
19#include "sti_drv.h"
29d1dc62 20#include "sti_vid.h"
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21#include "sti_vtg.h"
22
29d1dc62 23static void sti_crtc_enable(struct drm_crtc *crtc)
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24{
25 struct sti_mixer *mixer = to_sti_mixer(crtc);
26 struct device *dev = mixer->dev;
27 struct sti_compositor *compo = dev_get_drvdata(dev);
28
29d1dc62
VA
29 DRM_DEBUG_DRIVER("\n");
30
31 mixer->status = STI_MIXER_READY;
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32
33 /* Prepare and enable the compo IP clock */
34 if (mixer->id == STI_MIXER_MAIN) {
35 if (clk_prepare_enable(compo->clk_compo_main))
36 DRM_INFO("Failed to prepare/enable compo_main clk\n");
37 } else {
38 if (clk_prepare_enable(compo->clk_compo_aux))
39 DRM_INFO("Failed to prepare/enable compo_aux clk\n");
40 }
2f7d0e82 41
29d1dc62 42 drm_crtc_vblank_on(crtc);
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43}
44
29d1dc62 45static void sti_crtc_disabling(struct drm_crtc *crtc)
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46{
47 struct sti_mixer *mixer = to_sti_mixer(crtc);
9bbf86fe 48
29d1dc62 49 DRM_DEBUG_DRIVER("\n");
ca614aad 50
29d1dc62 51 mixer->status = STI_MIXER_DISABLING;
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52}
53
9bbf86fe 54static int
9e1f05b2 55sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode)
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56{
57 struct sti_mixer *mixer = to_sti_mixer(crtc);
58 struct device *dev = mixer->dev;
59 struct sti_compositor *compo = dev_get_drvdata(dev);
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60 struct clk *clk;
61 int rate = mode->clock * 1000;
62 int res;
9bbf86fe 63
de4b00b0 64 DRM_DEBUG_KMS("CRTC:%d (%s) mode:%d (%s)\n",
9bbf86fe 65 crtc->base.id, sti_mixer_to_str(mixer),
de4b00b0 66 mode->base.id, mode->name);
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67
68 DRM_DEBUG_KMS("%d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n",
69 mode->vrefresh, mode->clock,
70 mode->hdisplay,
71 mode->hsync_start, mode->hsync_end,
72 mode->htotal,
73 mode->vdisplay,
74 mode->vsync_start, mode->vsync_end,
75 mode->vtotal, mode->type, mode->flags);
76
77 /* Set rate and prepare/enable pixel clock */
78 if (mixer->id == STI_MIXER_MAIN)
79 clk = compo->clk_pix_main;
80 else
81 clk = compo->clk_pix_aux;
82
83 res = clk_set_rate(clk, rate);
84 if (res < 0) {
85 DRM_ERROR("Cannot set rate (%dHz) for pix clk\n", rate);
86 return -EINVAL;
87 }
88 if (clk_prepare_enable(clk)) {
89 DRM_ERROR("Failed to prepare/enable pix clk\n");
90 return -EINVAL;
91 }
92
93 sti_vtg_set_config(mixer->id == STI_MIXER_MAIN ?
94 compo->vtg_main : compo->vtg_aux, &crtc->mode);
95
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96 res = sti_mixer_active_video_area(mixer, &crtc->mode);
97 if (res) {
871bcdfe 98 DRM_ERROR("Can't set active video area\n");
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99 return -EINVAL;
100 }
101
de4b00b0 102 return res;
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103}
104
9e1f05b2 105static void sti_crtc_disable(struct drm_crtc *crtc)
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106{
107 struct sti_mixer *mixer = to_sti_mixer(crtc);
108 struct device *dev = mixer->dev;
109 struct sti_compositor *compo = dev_get_drvdata(dev);
9bbf86fe 110
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111 DRM_DEBUG_KMS("CRTC:%d (%s)\n", crtc->base.id, sti_mixer_to_str(mixer));
112
113 /* Disable Background */
114 sti_mixer_set_background_status(mixer, false);
115
ca614aad 116 drm_crtc_vblank_off(crtc);
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117
118 /* Disable pixel clock and compo IP clocks */
119 if (mixer->id == STI_MIXER_MAIN) {
120 clk_disable_unprepare(compo->clk_pix_main);
121 clk_disable_unprepare(compo->clk_compo_main);
122 } else {
123 clk_disable_unprepare(compo->clk_pix_aux);
124 clk_disable_unprepare(compo->clk_compo_aux);
125 }
126
29d1dc62 127 mixer->status = STI_MIXER_DISABLED;
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128}
129
de4b00b0 130static void
9e1f05b2 131sti_crtc_mode_set_nofb(struct drm_crtc *crtc)
de4b00b0 132{
29d1dc62 133 sti_crtc_enable(crtc);
9e1f05b2 134 sti_crtc_mode_set(crtc, &crtc->state->adjusted_mode);
de4b00b0 135}
9bbf86fe 136
e1474e7b
DA
137static void sti_crtc_atomic_begin(struct drm_crtc *crtc,
138 struct drm_crtc_state *old_crtc_state)
9bbf86fe 139{
9bbf86fe 140 struct sti_mixer *mixer = to_sti_mixer(crtc);
9bbf86fe 141
de4b00b0
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142 if (crtc->state->event) {
143 crtc->state->event->pipe = drm_crtc_index(crtc);
9bbf86fe 144
de4b00b0 145 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
9bbf86fe 146
de4b00b0
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147 mixer->pending_event = crtc->state->event;
148 crtc->state->event = NULL;
9bbf86fe 149 }
de4b00b0 150}
9bbf86fe 151
e1474e7b
DA
152static void sti_crtc_atomic_flush(struct drm_crtc *crtc,
153 struct drm_crtc_state *old_crtc_state)
de4b00b0 154{
29d1dc62
VA
155 struct drm_device *drm_dev = crtc->dev;
156 struct sti_mixer *mixer = to_sti_mixer(crtc);
157 struct sti_compositor *compo = dev_get_drvdata(mixer->dev);
158 struct drm_plane *p;
159
160 DRM_DEBUG_DRIVER("\n");
161
162 /* perform plane actions */
163 list_for_each_entry(p, &drm_dev->mode_config.plane_list, head) {
164 struct sti_plane *plane = to_sti_plane(p);
165
166 switch (plane->status) {
167 case STI_PLANE_UPDATED:
168 /* update planes tag as updated */
169 DRM_DEBUG_DRIVER("update plane %s\n",
170 sti_plane_to_str(plane));
171
172 if (sti_mixer_set_plane_depth(mixer, plane)) {
173 DRM_ERROR("Cannot set plane %s depth\n",
174 sti_plane_to_str(plane));
175 break;
176 }
177
178 if (sti_mixer_set_plane_status(mixer, plane, true)) {
179 DRM_ERROR("Cannot enable plane %s at mixer\n",
180 sti_plane_to_str(plane));
181 break;
182 }
183
184 /* if plane is HQVDP_0 then commit the vid[0] */
185 if (plane->desc == STI_HQVDP_0)
186 sti_vid_commit(compo->vid[0], p->state);
187
188 plane->status = STI_PLANE_READY;
189
190 break;
191 case STI_PLANE_DISABLING:
192 /* disabling sequence for planes tag as disabling */
193 DRM_DEBUG_DRIVER("disable plane %s from mixer\n",
194 sti_plane_to_str(plane));
195
196 if (sti_mixer_set_plane_status(mixer, plane, false)) {
197 DRM_ERROR("Cannot disable plane %s at mixer\n",
198 sti_plane_to_str(plane));
199 continue;
200 }
201
202 if (plane->desc == STI_CURSOR)
203 /* tag plane status for disabled */
204 plane->status = STI_PLANE_DISABLED;
205 else
206 /* tag plane status for flushing */
207 plane->status = STI_PLANE_FLUSHING;
208
209 /* if plane is HQVDP_0 then disable the vid[0] */
210 if (plane->desc == STI_HQVDP_0)
211 sti_vid_disable(compo->vid[0]);
212
213 break;
214 default:
215 /* Other status case are not handled */
216 break;
217 }
218 }
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219}
220
c5de4853 221static const struct drm_crtc_helper_funcs sti_crtc_helper_funcs = {
29d1dc62
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222 .enable = sti_crtc_enable,
223 .disable = sti_crtc_disabling,
de4b00b0 224 .mode_set = drm_helper_crtc_mode_set,
9e1f05b2 225 .mode_set_nofb = sti_crtc_mode_set_nofb,
de4b00b0 226 .mode_set_base = drm_helper_crtc_mode_set_base,
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227 .atomic_begin = sti_crtc_atomic_begin,
228 .atomic_flush = sti_crtc_atomic_flush,
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229};
230
9e1f05b2 231static void sti_crtc_destroy(struct drm_crtc *crtc)
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232{
233 DRM_DEBUG_KMS("\n");
234 drm_crtc_cleanup(crtc);
235}
236
9e1f05b2
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237static int sti_crtc_set_property(struct drm_crtc *crtc,
238 struct drm_property *property,
239 uint64_t val)
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240{
241 DRM_DEBUG_KMS("\n");
242 return 0;
243}
244
9e1f05b2
VA
245int sti_crtc_vblank_cb(struct notifier_block *nb,
246 unsigned long event, void *data)
9bbf86fe 247{
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248 struct sti_compositor *compo =
249 container_of(nb, struct sti_compositor, vtg_vblank_nb);
2388693e
TR
250 struct drm_crtc *crtc = data;
251 struct sti_mixer *mixer;
9bbf86fe 252 unsigned long flags;
9e1f05b2 253 struct sti_private *priv;
2388693e 254 unsigned int pipe;
9bbf86fe 255
2388693e
TR
256 priv = crtc->dev->dev_private;
257 pipe = drm_crtc_index(crtc);
258 mixer = compo->mixer[pipe];
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259
260 if ((event != VTG_TOP_FIELD_EVENT) &&
261 (event != VTG_BOTTOM_FIELD_EVENT)) {
262 DRM_ERROR("unknown event: %lu\n", event);
263 return -EINVAL;
264 }
265
2388693e 266 drm_crtc_handle_vblank(crtc);
9bbf86fe 267
2388693e
TR
268 spin_lock_irqsave(&crtc->dev->event_lock, flags);
269 if (mixer->pending_event) {
270 drm_crtc_send_vblank_event(crtc, mixer->pending_event);
271 drm_crtc_vblank_put(crtc);
272 mixer->pending_event = NULL;
9bbf86fe 273 }
2388693e 274 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
9bbf86fe 275
2388693e 276 if (mixer->status == STI_MIXER_DISABLING) {
29d1dc62
VA
277 struct drm_plane *p;
278
279 /* Disable mixer only if all overlay planes (GDP and VDP)
280 * are disabled */
2388693e
TR
281 list_for_each_entry(p, &crtc->dev->mode_config.plane_list,
282 head) {
29d1dc62
VA
283 struct sti_plane *plane = to_sti_plane(p);
284
285 if ((plane->desc & STI_PLANE_TYPE_MASK) <= STI_VDP)
286 if (plane->status != STI_PLANE_DISABLED)
287 return 0;
288 }
2388693e 289 sti_crtc_disable(crtc);
29d1dc62
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290 }
291
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292 return 0;
293}
294
88e72717 295int sti_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe)
9bbf86fe 296{
9e1f05b2 297 struct sti_private *dev_priv = dev->dev_private;
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298 struct sti_compositor *compo = dev_priv->compo;
299 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb;
2388693e 300 struct drm_crtc *crtc = &compo->mixer[pipe]->drm_crtc;
9bbf86fe 301
871bcdfe
VA
302 DRM_DEBUG_DRIVER("\n");
303
88e72717 304 if (sti_vtg_register_client(pipe == STI_MIXER_MAIN ?
9bbf86fe 305 compo->vtg_main : compo->vtg_aux,
2388693e 306 vtg_vblank_nb, crtc)) {
9bbf86fe
BG
307 DRM_ERROR("Cannot register VTG notifier\n");
308 return -EINVAL;
309 }
310
311 return 0;
312}
9bbf86fe 313
88e72717 314void sti_crtc_disable_vblank(struct drm_device *drm_dev, unsigned int pipe)
9bbf86fe 315{
29d1dc62 316 struct sti_private *priv = drm_dev->dev_private;
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BG
317 struct sti_compositor *compo = priv->compo;
318 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb;
2388693e 319 struct drm_crtc *crtc = &compo->mixer[pipe]->drm_crtc;
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320
321 DRM_DEBUG_DRIVER("\n");
322
88e72717 323 if (sti_vtg_unregister_client(pipe == STI_MIXER_MAIN ?
9bbf86fe
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324 compo->vtg_main : compo->vtg_aux, vtg_vblank_nb))
325 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
326
327 /* free the resources of the pending requests */
88e72717 328 if (compo->mixer[pipe]->pending_event) {
2388693e 329 drm_crtc_vblank_put(crtc);
88e72717 330 compo->mixer[pipe]->pending_event = NULL;
9bbf86fe 331 }
9bbf86fe 332}
9bbf86fe 333
c5de4853 334static const struct drm_crtc_funcs sti_crtc_funcs = {
de4b00b0
BG
335 .set_config = drm_atomic_helper_set_config,
336 .page_flip = drm_atomic_helper_page_flip,
9e1f05b2
VA
337 .destroy = sti_crtc_destroy,
338 .set_property = sti_crtc_set_property,
de4b00b0
BG
339 .reset = drm_atomic_helper_crtc_reset,
340 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
341 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
9bbf86fe
BG
342};
343
9e1f05b2 344bool sti_crtc_is_main(struct drm_crtc *crtc)
9bbf86fe
BG
345{
346 struct sti_mixer *mixer = to_sti_mixer(crtc);
347
348 if (mixer->id == STI_MIXER_MAIN)
349 return true;
350
351 return false;
352}
353
9e1f05b2
VA
354int sti_crtc_init(struct drm_device *drm_dev, struct sti_mixer *mixer,
355 struct drm_plane *primary, struct drm_plane *cursor)
9bbf86fe
BG
356{
357 struct drm_crtc *crtc = &mixer->drm_crtc;
358 int res;
359
360 res = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
f9882876 361 &sti_crtc_funcs, NULL);
9bbf86fe 362 if (res) {
871bcdfe 363 DRM_ERROR("Can't initialze CRTC\n");
9bbf86fe
BG
364 return -EINVAL;
365 }
366
367 drm_crtc_helper_add(crtc, &sti_crtc_helper_funcs);
368
369 DRM_DEBUG_DRIVER("drm CRTC:%d mapped to %s\n",
370 crtc->base.id, sti_mixer_to_str(mixer));
371
372 return 0;
373}
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