Commit | Line | Data |
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9bbf86fe BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics. | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | */ | |
6 | ||
7 | #include <drm/drmP.h> | |
8 | ||
9 | #include <linux/component.h> | |
10 | #include <linux/debugfs.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of_platform.h> | |
14 | ||
de4b00b0 BG |
15 | #include <drm/drm_atomic.h> |
16 | #include <drm/drm_atomic_helper.h> | |
9bbf86fe BG |
17 | #include <drm/drm_crtc_helper.h> |
18 | #include <drm/drm_gem_cma_helper.h> | |
19 | #include <drm/drm_fb_cma_helper.h> | |
20 | ||
9e1f05b2 VA |
21 | #include "sti_crtc.h" |
22 | #include "sti_drv.h" | |
9bbf86fe BG |
23 | |
24 | #define DRIVER_NAME "sti" | |
25 | #define DRIVER_DESC "STMicroelectronics SoC DRM" | |
26 | #define DRIVER_DATE "20140601" | |
27 | #define DRIVER_MAJOR 1 | |
28 | #define DRIVER_MINOR 0 | |
29 | ||
30 | #define STI_MAX_FB_HEIGHT 4096 | |
31 | #define STI_MAX_FB_WIDTH 4096 | |
32 | ||
9e1f05b2 VA |
33 | static void sti_atomic_schedule(struct sti_private *private, |
34 | struct drm_atomic_state *state) | |
de4b00b0 BG |
35 | { |
36 | private->commit.state = state; | |
37 | schedule_work(&private->commit.work); | |
38 | } | |
39 | ||
9e1f05b2 VA |
40 | static void sti_atomic_complete(struct sti_private *private, |
41 | struct drm_atomic_state *state) | |
de4b00b0 BG |
42 | { |
43 | struct drm_device *drm = private->drm_dev; | |
44 | ||
45 | /* | |
46 | * Everything below can be run asynchronously without the need to grab | |
47 | * any modeset locks at all under one condition: It must be guaranteed | |
48 | * that the asynchronous work has either been cancelled (if the driver | |
49 | * supports it, which at least requires that the framebuffers get | |
50 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed | |
51 | * before the new state gets committed on the software side with | |
52 | * drm_atomic_helper_swap_state(). | |
53 | * | |
54 | * This scheme allows new atomic state updates to be prepared and | |
55 | * checked in parallel to the asynchronous completion of the previous | |
56 | * update. Which is important since compositors need to figure out the | |
57 | * composition of the next frame right after having submitted the | |
58 | * current layout. | |
59 | */ | |
60 | ||
61 | drm_atomic_helper_commit_modeset_disables(drm, state); | |
aef9dbb8 | 62 | drm_atomic_helper_commit_planes(drm, state, false); |
de4b00b0 BG |
63 | drm_atomic_helper_commit_modeset_enables(drm, state); |
64 | ||
65 | drm_atomic_helper_wait_for_vblanks(drm, state); | |
66 | ||
67 | drm_atomic_helper_cleanup_planes(drm, state); | |
68 | drm_atomic_state_free(state); | |
69 | } | |
70 | ||
9e1f05b2 | 71 | static void sti_atomic_work(struct work_struct *work) |
de4b00b0 | 72 | { |
9e1f05b2 VA |
73 | struct sti_private *private = container_of(work, |
74 | struct sti_private, commit.work); | |
de4b00b0 | 75 | |
9e1f05b2 | 76 | sti_atomic_complete(private, private->commit.state); |
de4b00b0 BG |
77 | } |
78 | ||
9e1f05b2 VA |
79 | static int sti_atomic_commit(struct drm_device *drm, |
80 | struct drm_atomic_state *state, bool async) | |
de4b00b0 | 81 | { |
9e1f05b2 | 82 | struct sti_private *private = drm->dev_private; |
de4b00b0 BG |
83 | int err; |
84 | ||
85 | err = drm_atomic_helper_prepare_planes(drm, state); | |
86 | if (err) | |
87 | return err; | |
88 | ||
89 | /* serialize outstanding asynchronous commits */ | |
90 | mutex_lock(&private->commit.lock); | |
91 | flush_work(&private->commit.work); | |
92 | ||
93 | /* | |
94 | * This is the point of no return - everything below never fails except | |
95 | * when the hw goes bonghits. Which means we can commit the new state on | |
96 | * the software side now. | |
97 | */ | |
98 | ||
99 | drm_atomic_helper_swap_state(drm, state); | |
100 | ||
101 | if (async) | |
9e1f05b2 | 102 | sti_atomic_schedule(private, state); |
de4b00b0 | 103 | else |
9e1f05b2 | 104 | sti_atomic_complete(private, state); |
de4b00b0 BG |
105 | |
106 | mutex_unlock(&private->commit.lock); | |
107 | return 0; | |
108 | } | |
109 | ||
c5de4853 | 110 | static const struct drm_mode_config_funcs sti_mode_config_funcs = { |
9bbf86fe | 111 | .fb_create = drm_fb_cma_create, |
de4b00b0 | 112 | .atomic_check = drm_atomic_helper_check, |
9e1f05b2 | 113 | .atomic_commit = sti_atomic_commit, |
9bbf86fe BG |
114 | }; |
115 | ||
9e1f05b2 | 116 | static void sti_mode_config_init(struct drm_device *dev) |
9bbf86fe BG |
117 | { |
118 | dev->mode_config.min_width = 0; | |
119 | dev->mode_config.min_height = 0; | |
120 | ||
121 | /* | |
122 | * set max width and height as default value. | |
123 | * this value would be used to check framebuffer size limitation | |
124 | * at drm_mode_addfb(). | |
125 | */ | |
126 | dev->mode_config.max_width = STI_MAX_FB_HEIGHT; | |
127 | dev->mode_config.max_height = STI_MAX_FB_WIDTH; | |
128 | ||
9e1f05b2 | 129 | dev->mode_config.funcs = &sti_mode_config_funcs; |
9bbf86fe BG |
130 | } |
131 | ||
9e1f05b2 | 132 | static int sti_load(struct drm_device *dev, unsigned long flags) |
9bbf86fe | 133 | { |
9e1f05b2 | 134 | struct sti_private *private; |
9bbf86fe BG |
135 | int ret; |
136 | ||
9e1f05b2 | 137 | private = kzalloc(sizeof(*private), GFP_KERNEL); |
9bbf86fe BG |
138 | if (!private) { |
139 | DRM_ERROR("Failed to allocate private\n"); | |
140 | return -ENOMEM; | |
141 | } | |
142 | dev->dev_private = (void *)private; | |
143 | private->drm_dev = dev; | |
144 | ||
de4b00b0 | 145 | mutex_init(&private->commit.lock); |
9e1f05b2 | 146 | INIT_WORK(&private->commit.work, sti_atomic_work); |
de4b00b0 | 147 | |
9bbf86fe BG |
148 | drm_mode_config_init(dev); |
149 | drm_kms_helper_poll_init(dev); | |
150 | ||
9e1f05b2 | 151 | sti_mode_config_init(dev); |
9bbf86fe BG |
152 | |
153 | ret = component_bind_all(dev->dev, dev); | |
f78e772a BG |
154 | if (ret) { |
155 | drm_kms_helper_poll_fini(dev); | |
156 | drm_mode_config_cleanup(dev); | |
157 | kfree(private); | |
9bbf86fe | 158 | return ret; |
f78e772a | 159 | } |
9bbf86fe | 160 | |
de4b00b0 | 161 | drm_mode_config_reset(dev); |
9bbf86fe | 162 | |
9bbf86fe | 163 | drm_fbdev_cma_init(dev, 32, |
9e1f05b2 VA |
164 | dev->mode_config.num_crtc, |
165 | dev->mode_config.num_connector); | |
b5d34a27 | 166 | |
9bbf86fe BG |
167 | return 0; |
168 | } | |
169 | ||
9e1f05b2 | 170 | static const struct file_operations sti_driver_fops = { |
9bbf86fe BG |
171 | .owner = THIS_MODULE, |
172 | .open = drm_open, | |
173 | .mmap = drm_gem_cma_mmap, | |
174 | .poll = drm_poll, | |
175 | .read = drm_read, | |
176 | .unlocked_ioctl = drm_ioctl, | |
177 | #ifdef CONFIG_COMPAT | |
178 | .compat_ioctl = drm_compat_ioctl, | |
179 | #endif | |
180 | .release = drm_release, | |
181 | }; | |
182 | ||
9e1f05b2 VA |
183 | static struct dma_buf *sti_gem_prime_export(struct drm_device *dev, |
184 | struct drm_gem_object *obj, | |
185 | int flags) | |
9bbf86fe BG |
186 | { |
187 | /* we want to be able to write in mmapped buffer */ | |
188 | flags |= O_RDWR; | |
189 | return drm_gem_prime_export(dev, obj, flags); | |
190 | } | |
191 | ||
9e1f05b2 | 192 | static struct drm_driver sti_driver = { |
9bbf86fe BG |
193 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET | |
194 | DRIVER_GEM | DRIVER_PRIME, | |
9e1f05b2 | 195 | .load = sti_load, |
9bbf86fe BG |
196 | .gem_free_object = drm_gem_cma_free_object, |
197 | .gem_vm_ops = &drm_gem_cma_vm_ops, | |
198 | .dumb_create = drm_gem_cma_dumb_create, | |
199 | .dumb_map_offset = drm_gem_cma_dumb_map_offset, | |
200 | .dumb_destroy = drm_gem_dumb_destroy, | |
9e1f05b2 | 201 | .fops = &sti_driver_fops, |
9bbf86fe | 202 | |
b44f8408 | 203 | .get_vblank_counter = drm_vblank_no_hw_counter, |
9e1f05b2 VA |
204 | .enable_vblank = sti_crtc_enable_vblank, |
205 | .disable_vblank = sti_crtc_disable_vblank, | |
9bbf86fe BG |
206 | |
207 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
208 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
9e1f05b2 | 209 | .gem_prime_export = sti_gem_prime_export, |
9bbf86fe BG |
210 | .gem_prime_import = drm_gem_prime_import, |
211 | .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, | |
212 | .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, | |
213 | .gem_prime_vmap = drm_gem_cma_prime_vmap, | |
214 | .gem_prime_vunmap = drm_gem_cma_prime_vunmap, | |
215 | .gem_prime_mmap = drm_gem_cma_prime_mmap, | |
216 | ||
217 | .name = DRIVER_NAME, | |
218 | .desc = DRIVER_DESC, | |
219 | .date = DRIVER_DATE, | |
220 | .major = DRIVER_MAJOR, | |
221 | .minor = DRIVER_MINOR, | |
222 | }; | |
223 | ||
224 | static int compare_of(struct device *dev, void *data) | |
225 | { | |
226 | return dev->of_node == data; | |
227 | } | |
228 | ||
9e1f05b2 | 229 | static int sti_bind(struct device *dev) |
9bbf86fe | 230 | { |
9e1f05b2 | 231 | return drm_platform_init(&sti_driver, to_platform_device(dev)); |
9bbf86fe BG |
232 | } |
233 | ||
9e1f05b2 | 234 | static void sti_unbind(struct device *dev) |
9bbf86fe BG |
235 | { |
236 | drm_put_dev(dev_get_drvdata(dev)); | |
237 | } | |
238 | ||
9e1f05b2 VA |
239 | static const struct component_master_ops sti_ops = { |
240 | .bind = sti_bind, | |
241 | .unbind = sti_unbind, | |
9bbf86fe BG |
242 | }; |
243 | ||
9e1f05b2 | 244 | static int sti_platform_probe(struct platform_device *pdev) |
9bbf86fe BG |
245 | { |
246 | struct device *dev = &pdev->dev; | |
53bdcf5f | 247 | struct device_node *node = dev->of_node; |
9bbf86fe BG |
248 | struct device_node *child_np; |
249 | struct component_match *match = NULL; | |
250 | ||
251 | dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); | |
252 | ||
53bdcf5f BG |
253 | of_platform_populate(node, NULL, NULL, dev); |
254 | ||
9bbf86fe BG |
255 | child_np = of_get_next_available_child(node, NULL); |
256 | ||
257 | while (child_np) { | |
258 | component_match_add(dev, &match, compare_of, child_np); | |
259 | of_node_put(child_np); | |
260 | child_np = of_get_next_available_child(node, child_np); | |
261 | } | |
262 | ||
9e1f05b2 | 263 | return component_master_add_with_match(dev, &sti_ops, match); |
9bbf86fe BG |
264 | } |
265 | ||
9e1f05b2 | 266 | static int sti_platform_remove(struct platform_device *pdev) |
9bbf86fe | 267 | { |
9e1f05b2 | 268 | component_master_del(&pdev->dev, &sti_ops); |
9bbf86fe | 269 | of_platform_depopulate(&pdev->dev); |
53bdcf5f | 270 | |
9bbf86fe BG |
271 | return 0; |
272 | } | |
273 | ||
9e1f05b2 | 274 | static const struct of_device_id sti_dt_ids[] = { |
9bbf86fe BG |
275 | { .compatible = "st,sti-display-subsystem", }, |
276 | { /* end node */ }, | |
277 | }; | |
9e1f05b2 | 278 | MODULE_DEVICE_TABLE(of, sti_dt_ids); |
9bbf86fe | 279 | |
9e1f05b2 VA |
280 | static struct platform_driver sti_platform_driver = { |
281 | .probe = sti_platform_probe, | |
282 | .remove = sti_platform_remove, | |
9bbf86fe | 283 | .driver = { |
9bbf86fe | 284 | .name = DRIVER_NAME, |
9e1f05b2 | 285 | .of_match_table = sti_dt_ids, |
9bbf86fe BG |
286 | }, |
287 | }; | |
288 | ||
dcec16ef TR |
289 | static struct platform_driver * const drivers[] = { |
290 | &sti_tvout_driver, | |
291 | &sti_vtac_driver, | |
292 | &sti_hqvdp_driver, | |
293 | &sti_hdmi_driver, | |
294 | &sti_hda_driver, | |
295 | &sti_dvo_driver, | |
296 | &sti_vtg_driver, | |
297 | &sti_compositor_driver, | |
298 | &sti_platform_driver, | |
299 | }; | |
300 | ||
301 | static int sti_drm_init(void) | |
302 | { | |
303 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); | |
304 | } | |
305 | module_init(sti_drm_init); | |
306 | ||
307 | static void sti_drm_exit(void) | |
308 | { | |
309 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); | |
310 | } | |
311 | module_exit(sti_drm_exit); | |
9bbf86fe BG |
312 | |
313 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); | |
314 | MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); | |
315 | MODULE_LICENSE("GPL"); |