[deliverable/linux.git] / drivers / gpu / drm / sti / sti_gdp.c

/*
 * Copyright (C) STMicroelectronics SA 2014
 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
 *          Fabien Dessenne <fabien.dessenne@st.com>
 *          for STMicroelectronics.
 * License terms:  GNU General Public License (GPL), version 2
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>

#include "sti_compositor.h"
#include "sti_gdp.h"
#include "sti_plane.h"
#include "sti_vtg.h"

#define ALPHASWITCH     BIT(6)
#define ENA_COLOR_FILL  BIT(8)
#define BIGNOTLITTLE    BIT(23)
#define WAIT_NEXT_VSYNC BIT(31)

/* GDP color formats */
#define GDP_RGB565      0x00
#define GDP_RGB888      0x01
#define GDP_RGB888_32   0x02
#define GDP_XBGR8888    (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
#define GDP_ARGB8565    0x04
#define GDP_ARGB8888    0x05
#define GDP_ABGR8888	(GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
#define GDP_ARGB1555    0x06
#define GDP_ARGB4444    0x07
#define GDP_CLUT8       0x0B
#define GDP_YCBR888     0x10
#define GDP_YCBR422R    0x12
#define GDP_AYCBR8888   0x15

#define GAM_GDP_CTL_OFFSET      0x00
#define GAM_GDP_AGC_OFFSET      0x04
#define GAM_GDP_VPO_OFFSET      0x0C
#define GAM_GDP_VPS_OFFSET      0x10
#define GAM_GDP_PML_OFFSET      0x14
#define GAM_GDP_PMP_OFFSET      0x18
#define GAM_GDP_SIZE_OFFSET     0x1C
#define GAM_GDP_NVN_OFFSET      0x24
#define GAM_GDP_KEY1_OFFSET     0x28
#define GAM_GDP_KEY2_OFFSET     0x2C
#define GAM_GDP_PPT_OFFSET      0x34
#define GAM_GDP_CML_OFFSET      0x3C
#define GAM_GDP_MST_OFFSET      0x68

#define GAM_GDP_ALPHARANGE_255  BIT(5)
#define GAM_GDP_AGC_FULL_RANGE  0x00808080
#define GAM_GDP_PPT_IGNORE      (BIT(1) | BIT(0))
#define GAM_GDP_SIZE_MAX        0x7FF

#define GDP_NODE_NB_BANK	2
#define GDP_NODE_PER_FIELD	2

struct sti_gdp_node {
	u32 gam_gdp_ctl;
	u32 gam_gdp_agc;
	u32 reserved1;
	u32 gam_gdp_vpo;
	u32 gam_gdp_vps;
	u32 gam_gdp_pml;
	u32 gam_gdp_pmp;
	u32 gam_gdp_size;
	u32 reserved2;
	u32 gam_gdp_nvn;
	u32 gam_gdp_key1;
	u32 gam_gdp_key2;
	u32 reserved3;
	u32 gam_gdp_ppt;
	u32 reserved4;
	u32 gam_gdp_cml;
};

struct sti_gdp_node_list {
	struct sti_gdp_node *top_field;
	dma_addr_t top_field_paddr;
	struct sti_gdp_node *btm_field;
	dma_addr_t btm_field_paddr;
};

/**
 * STI GDP structure
 *
 * @sti_plane:          sti_plane structure
 * @dev:                driver device
 * @regs:               gdp registers
 * @clk_pix:            pixel clock for the current gdp
 * @clk_main_parent:    gdp parent clock if main path used
 * @clk_aux_parent:     gdp parent clock if aux path used
 * @vtg_field_nb:       callback for VTG FIELD (top or bottom) notification
 * @is_curr_top:        true if the current node processed is the top field
 * @node_list:          array of node list
 */
struct sti_gdp {
	struct sti_plane plane;
	struct device *dev;
	void __iomem *regs;
	struct clk *clk_pix;
	struct clk *clk_main_parent;
	struct clk *clk_aux_parent;
	struct notifier_block vtg_field_nb;
	bool is_curr_top;
	struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
};

#define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)

static const uint32_t gdp_supported_formats[] = {
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_ARGB4444,
	DRM_FORMAT_ARGB1555,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_RGB888,
	DRM_FORMAT_AYUV,
	DRM_FORMAT_YUV444,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_C8,
};

static const uint32_t *sti_gdp_get_formats(struct sti_plane *plane)
{
	return gdp_supported_formats;
}

static unsigned int sti_gdp_get_nb_formats(struct sti_plane *plane)
{
	return ARRAY_SIZE(gdp_supported_formats);
}

static int sti_gdp_fourcc2format(int fourcc)
{
	switch (fourcc) {
	case DRM_FORMAT_XRGB8888:
		return GDP_RGB888_32;
	case DRM_FORMAT_XBGR8888:
		return GDP_XBGR8888;
	case DRM_FORMAT_ARGB8888:
		return GDP_ARGB8888;
	case DRM_FORMAT_ABGR8888:
		return GDP_ABGR8888;
	case DRM_FORMAT_ARGB4444:
		return GDP_ARGB4444;
	case DRM_FORMAT_ARGB1555:
		return GDP_ARGB1555;
	case DRM_FORMAT_RGB565:
		return GDP_RGB565;
	case DRM_FORMAT_RGB888:
		return GDP_RGB888;
	case DRM_FORMAT_AYUV:
		return GDP_AYCBR8888;
	case DRM_FORMAT_YUV444:
		return GDP_YCBR888;
	case DRM_FORMAT_VYUY:
		return GDP_YCBR422R;
	case DRM_FORMAT_C8:
		return GDP_CLUT8;
	}
	return -1;
}

static int sti_gdp_get_alpharange(int format)
{
	switch (format) {
	case GDP_ARGB8565:
	case GDP_ARGB8888:
	case GDP_AYCBR8888:
	case GDP_ABGR8888:
		return GAM_GDP_ALPHARANGE_255;
	}
	return 0;
}

/**
 * sti_gdp_get_free_nodes
 * @plane: gdp plane
 *
 * Look for a GDP node list that is not currently read by the HW.
 *
 * RETURNS:
 * Pointer to the free GDP node list
 */
static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_plane *plane)
{
	int hw_nvn;
	struct sti_gdp *gdp = to_sti_gdp(plane);
	unsigned int i;

	hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
	if (!hw_nvn)
		goto end;

	for (i = 0; i < GDP_NODE_NB_BANK; i++)
		if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
		    (hw_nvn != gdp->node_list[i].top_field_paddr))
			return &gdp->node_list[i];

	/* in hazardious cases restart with the first node */
	DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
			sti_plane_to_str(plane), hw_nvn);

end:
	return &gdp->node_list[0];
}

/**
 * sti_gdp_get_current_nodes
 * @plane: GDP plane
 *
 * Look for GDP nodes that are currently read by the HW.
 *
 * RETURNS:
 * Pointer to the current GDP node list
 */
static
struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_plane *plane)
{
	int hw_nvn;
	struct sti_gdp *gdp = to_sti_gdp(plane);
	unsigned int i;

	hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
	if (!hw_nvn)
		goto end;

	for (i = 0; i < GDP_NODE_NB_BANK; i++)
		if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
				(hw_nvn == gdp->node_list[i].top_field_paddr))
			return &gdp->node_list[i];

end:
	DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
				hw_nvn, sti_plane_to_str(plane));

	return NULL;
}

/**
 * sti_gdp_prepare
 * @plane: gdp plane
 * @first_prepare: true if it is the first time this function is called
 *
 * Update the free GDP node list according to the plane properties.
 *
 * RETURNS:
 * 0 on success.
 */
static int sti_gdp_prepare(struct sti_plane *plane, bool first_prepare)
{
	struct sti_gdp_node_list *list;
	struct sti_gdp_node *top_field, *btm_field;
	struct drm_display_mode *mode = plane->mode;
	struct sti_gdp *gdp = to_sti_gdp(plane);
	struct device *dev = gdp->dev;
	struct sti_compositor *compo = dev_get_drvdata(dev);
	int format;
	unsigned int depth, bpp;
	int rate = mode->clock * 1000;
	int res;
	u32 ydo, xdo, yds, xds;

	list = sti_gdp_get_free_nodes(plane);
	top_field = list->top_field;
	btm_field = list->btm_field;

	dev_dbg(dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
			sti_plane_to_str(plane), top_field, btm_field);

	/* Build the top field from plane params */
	top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
	top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
	format = sti_gdp_fourcc2format(plane->format);
	if (format == -1) {
		DRM_ERROR("Format not supported by GDP %.4s\n",
			  (char *)&plane->format);
		return 1;
	}
	top_field->gam_gdp_ctl |= format;
	top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
	top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;

	/* pixel memory location */
	drm_fb_get_bpp_depth(plane->format, &depth, &bpp);
	top_field->gam_gdp_pml = (u32)plane->paddr + plane->offsets[0];
	top_field->gam_gdp_pml += plane->src_x * (bpp >> 3);
	top_field->gam_gdp_pml += plane->src_y * plane->pitches[0];

	/* input parameters */
	top_field->gam_gdp_pmp = plane->pitches[0];
	top_field->gam_gdp_size =
	    clamp_val(plane->src_h, 0, GAM_GDP_SIZE_MAX) << 16 |
	    clamp_val(plane->src_w, 0, GAM_GDP_SIZE_MAX);

	/* output parameters */
	ydo = sti_vtg_get_line_number(*mode, plane->dst_y);
	yds = sti_vtg_get_line_number(*mode, plane->dst_y + plane->dst_h - 1);
	xdo = sti_vtg_get_pixel_number(*mode, plane->dst_x);
	xds = sti_vtg_get_pixel_number(*mode, plane->dst_x + plane->dst_w - 1);
	top_field->gam_gdp_vpo = (ydo << 16) | xdo;
	top_field->gam_gdp_vps = (yds << 16) | xds;

	/* Same content and chained together */
	memcpy(btm_field, top_field, sizeof(*btm_field));
	top_field->gam_gdp_nvn = list->btm_field_paddr;
	btm_field->gam_gdp_nvn = list->top_field_paddr;

	/* Interlaced mode */
	if (plane->mode->flags & DRM_MODE_FLAG_INTERLACE)
		btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
		    plane->pitches[0];

	if (first_prepare) {
		/* Register gdp callback */
		if (sti_vtg_register_client(plane->mixer_id == STI_MIXER_MAIN ?
				compo->vtg_main : compo->vtg_aux,
				&gdp->vtg_field_nb, plane->mixer_id)) {
			DRM_ERROR("Cannot register VTG notifier\n");
			return 1;
		}

		/* Set and enable gdp clock */
		if (gdp->clk_pix) {
			struct clk *clkp;
			/* According to the mixer used, the gdp pixel clock
			 * should have a different parent clock. */
			if (plane->mixer_id == STI_MIXER_MAIN)
				clkp = gdp->clk_main_parent;
			else
				clkp = gdp->clk_aux_parent;

			if (clkp)
				clk_set_parent(gdp->clk_pix, clkp);

			res = clk_set_rate(gdp->clk_pix, rate);
			if (res < 0) {
				DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
						rate);
				return 1;
			}

			if (clk_prepare_enable(gdp->clk_pix)) {
				DRM_ERROR("Failed to prepare/enable gdp\n");
				return 1;
			}
		}
	}

	return 0;
}

/**
 * sti_gdp_commit
 * @plane: gdp plane
 *
 * Update the NVN field of the 'right' field of the current GDP node (being
 * used by the HW) with the address of the updated ('free') top field GDP node.
 * - In interlaced mode the 'right' field is the bottom field as we update
 *   frames starting from their top field
 * - In progressive mode, we update both bottom and top fields which are
 *   equal nodes.
 * At the next VSYNC, the updated node list will be used by the HW.
 *
 * RETURNS:
 * 0 on success.
 */
static int sti_gdp_commit(struct sti_plane *plane)
{
	struct sti_gdp_node_list *updated_list = sti_gdp_get_free_nodes(plane);
	struct sti_gdp_node *updated_top_node = updated_list->top_field;
	struct sti_gdp_node *updated_btm_node = updated_list->btm_field;
	struct sti_gdp *gdp = to_sti_gdp(plane);
	u32 dma_updated_top = updated_list->top_field_paddr;
	u32 dma_updated_btm = updated_list->btm_field_paddr;
	struct sti_gdp_node_list *curr_list = sti_gdp_get_current_nodes(plane);

	dev_dbg(gdp->dev, "%s %s top/btm_node:0x%p/0x%p\n", __func__,
		sti_plane_to_str(plane),
		updated_top_node, updated_btm_node);
	dev_dbg(gdp->dev, "Current NVN:0x%X\n",
		readl(gdp->regs + GAM_GDP_NVN_OFFSET));
	dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
		(unsigned long)plane->paddr,
		readl(gdp->regs + GAM_GDP_PML_OFFSET));

	if (curr_list == NULL) {
		/* First update or invalid node should directly write in the
		 * hw register */
		DRM_DEBUG_DRIVER("%s first update (or invalid node)",
				sti_plane_to_str(plane));

		writel(gdp->is_curr_top == true ?
				dma_updated_btm : dma_updated_top,
				gdp->regs + GAM_GDP_NVN_OFFSET);
		return 0;
	}

	if (plane->mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (gdp->is_curr_top == true) {
			/* Do not update in the middle of the frame, but
			 * postpone the update after the bottom field has
			 * been displayed */
			curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
		} else {
			/* Direct update to avoid one frame delay */
			writel(dma_updated_top,
				gdp->regs + GAM_GDP_NVN_OFFSET);
		}
	} else {
		/* Direct update for progressive to avoid one frame delay */
		writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
	}

	return 0;
}

/**
 * sti_gdp_disable
 * @plane: gdp plane
 *
 * Disable a GDP.
 *
 * RETURNS:
 * 0 on success.
 */
static int sti_gdp_disable(struct sti_plane *plane)
{
	unsigned int i;
	struct sti_gdp *gdp = to_sti_gdp(plane);
	struct sti_compositor *compo = dev_get_drvdata(gdp->dev);

	DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(plane));

	/* Set the nodes as 'to be ignored on mixer' */
	for (i = 0; i < GDP_NODE_NB_BANK; i++) {
		gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
		gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
	}

	if (sti_vtg_unregister_client(plane->mixer_id == STI_MIXER_MAIN ?
			compo->vtg_main : compo->vtg_aux, &gdp->vtg_field_nb))
		DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");

	if (gdp->clk_pix)
		clk_disable_unprepare(gdp->clk_pix);

	return 0;
}

/**
 * sti_gdp_field_cb
 * @nb: notifier block
 * @event: event message
 * @data: private data
 *
 * Handle VTG top field and bottom field event.
 *
 * RETURNS:
 * 0 on success.
 */
int sti_gdp_field_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);

	switch (event) {
	case VTG_TOP_FIELD_EVENT:
		gdp->is_curr_top = true;
		break;
	case VTG_BOTTOM_FIELD_EVENT:
		gdp->is_curr_top = false;
		break;
	default:
		DRM_ERROR("unsupported event: %lu\n", event);
		break;
	}

	return 0;
}

static void sti_gdp_init(struct sti_gdp *gdp)
{
	struct device_node *np = gdp->dev->of_node;
	dma_addr_t dma_addr;
	void *base;
	unsigned int i, size;

	/* Allocate all the nodes within a single memory page */
	size = sizeof(struct sti_gdp_node) *
	    GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
	base = dma_alloc_writecombine(gdp->dev,
				      size, &dma_addr, GFP_KERNEL | GFP_DMA);

	if (!base) {
		DRM_ERROR("Failed to allocate memory for GDP node\n");
		return;
	}
	memset(base, 0, size);

	for (i = 0; i < GDP_NODE_NB_BANK; i++) {
		if (dma_addr & 0xF) {
			DRM_ERROR("Mem alignment failed\n");
			return;
		}
		gdp->node_list[i].top_field = base;
		gdp->node_list[i].top_field_paddr = dma_addr;

		DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
		base += sizeof(struct sti_gdp_node);
		dma_addr += sizeof(struct sti_gdp_node);

		if (dma_addr & 0xF) {
			DRM_ERROR("Mem alignment failed\n");
			return;
		}
		gdp->node_list[i].btm_field = base;
		gdp->node_list[i].btm_field_paddr = dma_addr;
		DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
		base += sizeof(struct sti_gdp_node);
		dma_addr += sizeof(struct sti_gdp_node);
	}

	if (of_device_is_compatible(np, "st,stih407-compositor")) {
		/* GDP of STiH407 chip have its own pixel clock */
		char *clk_name;

		switch (gdp->plane.desc) {
		case STI_GDP_0:
			clk_name = "pix_gdp1";
			break;
		case STI_GDP_1:
			clk_name = "pix_gdp2";
			break;
		case STI_GDP_2:
			clk_name = "pix_gdp3";
			break;
		case STI_GDP_3:
			clk_name = "pix_gdp4";
			break;
		default:
			DRM_ERROR("GDP id not recognized\n");
			return;
		}

		gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
		if (IS_ERR(gdp->clk_pix))
			DRM_ERROR("Cannot get %s clock\n", clk_name);

		gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
		if (IS_ERR(gdp->clk_main_parent))
			DRM_ERROR("Cannot get main_parent clock\n");

		gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
		if (IS_ERR(gdp->clk_aux_parent))
			DRM_ERROR("Cannot get aux_parent clock\n");
	}
}

static const struct sti_plane_funcs gdp_plane_ops = {
	.get_formats = sti_gdp_get_formats,
	.get_nb_formats = sti_gdp_get_nb_formats,
	.prepare = sti_gdp_prepare,
	.commit = sti_gdp_commit,
	.disable = sti_gdp_disable,
};

struct sti_plane *sti_gdp_create(struct device *dev, int desc,
				 void __iomem *baseaddr)
{
	struct sti_gdp *gdp;

	gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
	if (!gdp) {
		DRM_ERROR("Failed to allocate memory for GDP\n");
		return NULL;
	}

	gdp->dev = dev;
	gdp->regs = baseaddr;
	gdp->plane.desc = desc;
	gdp->plane.ops = &gdp_plane_ops;

	gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;

	sti_gdp_init(gdp);

	return &gdp->plane;
}
Commit	Line	Data
ba2d53fb BG	1	/*
	2	* Copyright (C) STMicroelectronics SA 2014
	3	* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
	4	* Fabien Dessenne <fabien.dessenne@st.com>
	5	* for STMicroelectronics.
	6	* License terms: GNU General Public License (GPL), version 2
	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/dma-mapping.h>
	11
d219673d	12	#include "sti_compositor.h"
ba2d53fb	13	#include "sti_gdp.h"
9e1f05b2	14	#include "sti_plane.h"
ba2d53fb BG	15	#include "sti_vtg.h"
ba2d53fb BG	16
4af6b12a	17	#define ALPHASWITCH BIT(6)
ba2d53fb	18	#define ENA_COLOR_FILL BIT(8)
4af6b12a	19	#define BIGNOTLITTLE BIT(23)
ba2d53fb BG	20	#define WAIT_NEXT_VSYNC BIT(31)
	21
	22	/* GDP color formats */
	23	#define GDP_RGB565 0x00
	24	#define GDP_RGB888 0x01
	25	#define GDP_RGB888_32 0x02
8adb5776	26	#define GDP_XBGR8888 (GDP_RGB888_32 \| BIGNOTLITTLE \| ALPHASWITCH)
ba2d53fb BG	27	#define GDP_ARGB8565 0x04
ba2d53fb BG	28	#define GDP_ARGB8888 0x05
4af6b12a	29	#define GDP_ABGR8888 (GDP_ARGB8888 \| BIGNOTLITTLE \| ALPHASWITCH)
ba2d53fb BG	30	#define GDP_ARGB1555 0x06
	31	#define GDP_ARGB4444 0x07
	32	#define GDP_CLUT8 0x0B
	33	#define GDP_YCBR888 0x10
	34	#define GDP_YCBR422R 0x12
	35	#define GDP_AYCBR8888 0x15
	36
	37	#define GAM_GDP_CTL_OFFSET 0x00
	38	#define GAM_GDP_AGC_OFFSET 0x04
	39	#define GAM_GDP_VPO_OFFSET 0x0C
	40	#define GAM_GDP_VPS_OFFSET 0x10
	41	#define GAM_GDP_PML_OFFSET 0x14
	42	#define GAM_GDP_PMP_OFFSET 0x18
	43	#define GAM_GDP_SIZE_OFFSET 0x1C
	44	#define GAM_GDP_NVN_OFFSET 0x24
	45	#define GAM_GDP_KEY1_OFFSET 0x28
	46	#define GAM_GDP_KEY2_OFFSET 0x2C
	47	#define GAM_GDP_PPT_OFFSET 0x34
	48	#define GAM_GDP_CML_OFFSET 0x3C
	49	#define GAM_GDP_MST_OFFSET 0x68
	50
	51	#define GAM_GDP_ALPHARANGE_255 BIT(5)
	52	#define GAM_GDP_AGC_FULL_RANGE 0x00808080
	53	#define GAM_GDP_PPT_IGNORE (BIT(1) \| BIT(0))
	54	#define GAM_GDP_SIZE_MAX 0x7FF
	55
	56	#define GDP_NODE_NB_BANK 2
	57	#define GDP_NODE_PER_FIELD 2
	58
	59	struct sti_gdp_node {
	60	u32 gam_gdp_ctl;
	61	u32 gam_gdp_agc;
	62	u32 reserved1;
	63	u32 gam_gdp_vpo;
	64	u32 gam_gdp_vps;
	65	u32 gam_gdp_pml;
	66	u32 gam_gdp_pmp;
	67	u32 gam_gdp_size;
	68	u32 reserved2;
	69	u32 gam_gdp_nvn;
	70	u32 gam_gdp_key1;
	71	u32 gam_gdp_key2;
	72	u32 reserved3;
	73	u32 gam_gdp_ppt;
	74	u32 reserved4;
	75	u32 gam_gdp_cml;
	76	};
	77
	78	struct sti_gdp_node_list {
	79	struct sti_gdp_node *top_field;
a51fe84d	80	dma_addr_t top_field_paddr;
ba2d53fb	81	struct sti_gdp_node *btm_field;
a51fe84d	82	dma_addr_t btm_field_paddr;
ba2d53fb BG	83	};
	84
	85	/**
	86	* STI GDP structure
	87	*
871bcdfe VA	88	* @sti_plane: sti_plane structure
	89	* @dev: driver device
	90	* @regs: gdp registers
ba2d53fb	91	* @clk_pix: pixel clock for the current gdp
5e03abc5 BG	92	* @clk_main_parent: gdp parent clock if main path used
5e03abc5 BG	93	* @clk_aux_parent: gdp parent clock if aux path used
ba2d53fb BG	94	* @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
ba2d53fb BG	95	* @is_curr_top: true if the current node processed is the top field
871bcdfe	96	* @node_list: array of node list
ba2d53fb BG	97	*/
ba2d53fb BG	98	struct sti_gdp {
871bcdfe VA	99	struct sti_plane plane;
	100	struct device *dev;
	101	void __iomem *regs;
ba2d53fb	102	struct clk *clk_pix;
5e03abc5 BG	103	struct clk *clk_main_parent;
5e03abc5 BG	104	struct clk *clk_aux_parent;
ba2d53fb BG	105	struct notifier_block vtg_field_nb;
	106	bool is_curr_top;
	107	struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
	108	};
	109
871bcdfe	110	#define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
ba2d53fb BG	111
	112	static const uint32_t gdp_supported_formats[] = {
	113	DRM_FORMAT_XRGB8888,
8adb5776	114	DRM_FORMAT_XBGR8888,
ba2d53fb	115	DRM_FORMAT_ARGB8888,
4af6b12a	116	DRM_FORMAT_ABGR8888,
ba2d53fb BG	117	DRM_FORMAT_ARGB4444,
	118	DRM_FORMAT_ARGB1555,
	119	DRM_FORMAT_RGB565,
	120	DRM_FORMAT_RGB888,
	121	DRM_FORMAT_AYUV,
	122	DRM_FORMAT_YUV444,
	123	DRM_FORMAT_VYUY,
	124	DRM_FORMAT_C8,
	125	};
	126
871bcdfe	127	static const uint32_t sti_gdp_get_formats(struct sti_plane plane)
ba2d53fb BG	128	{
	129	return gdp_supported_formats;
	130	}
	131
871bcdfe	132	static unsigned int sti_gdp_get_nb_formats(struct sti_plane *plane)
ba2d53fb BG	133	{
	134	return ARRAY_SIZE(gdp_supported_formats);
	135	}
	136
	137	static int sti_gdp_fourcc2format(int fourcc)
	138	{
	139	switch (fourcc) {
	140	case DRM_FORMAT_XRGB8888:
	141	return GDP_RGB888_32;
8adb5776 FD	142	case DRM_FORMAT_XBGR8888:
8adb5776 FD	143	return GDP_XBGR8888;
ba2d53fb BG	144	case DRM_FORMAT_ARGB8888:
ba2d53fb BG	145	return GDP_ARGB8888;
4af6b12a BG	146	case DRM_FORMAT_ABGR8888:
4af6b12a BG	147	return GDP_ABGR8888;
ba2d53fb BG	148	case DRM_FORMAT_ARGB4444:
	149	return GDP_ARGB4444;
	150	case DRM_FORMAT_ARGB1555:
	151	return GDP_ARGB1555;
	152	case DRM_FORMAT_RGB565:
	153	return GDP_RGB565;
	154	case DRM_FORMAT_RGB888:
	155	return GDP_RGB888;
	156	case DRM_FORMAT_AYUV:
	157	return GDP_AYCBR8888;
	158	case DRM_FORMAT_YUV444:
	159	return GDP_YCBR888;
	160	case DRM_FORMAT_VYUY:
	161	return GDP_YCBR422R;
	162	case DRM_FORMAT_C8:
	163	return GDP_CLUT8;
	164	}
	165	return -1;
	166	}
	167
	168	static int sti_gdp_get_alpharange(int format)
	169	{
	170	switch (format) {
	171	case GDP_ARGB8565:
	172	case GDP_ARGB8888:
	173	case GDP_AYCBR8888:
4af6b12a	174	case GDP_ABGR8888:
ba2d53fb BG	175	return GAM_GDP_ALPHARANGE_255;
	176	}
	177	return 0;
	178	}
	179
	180	/**
	181	* sti_gdp_get_free_nodes
871bcdfe	182	* @plane: gdp plane
ba2d53fb BG	183	*
	184	* Look for a GDP node list that is not currently read by the HW.
	185	*
	186	* RETURNS:
	187	* Pointer to the free GDP node list
	188	*/
871bcdfe	189	static struct sti_gdp_node_list sti_gdp_get_free_nodes(struct sti_plane plane)
ba2d53fb BG	190	{
ba2d53fb BG	191	int hw_nvn;
871bcdfe	192	struct sti_gdp *gdp = to_sti_gdp(plane);
ba2d53fb BG	193	unsigned int i;
ba2d53fb BG	194
871bcdfe	195	hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
ba2d53fb BG	196	if (!hw_nvn)
	197	goto end;
	198
ba2d53fb	199	for (i = 0; i < GDP_NODE_NB_BANK; i++)
a51fe84d BG	200	if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
a51fe84d BG	201	(hw_nvn != gdp->node_list[i].top_field_paddr))
ba2d53fb BG	202	return &gdp->node_list[i];
ba2d53fb BG	203
d219673d BG	204	/* in hazardious cases restart with the first node */
d219673d BG	205	DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
871bcdfe	206	sti_plane_to_str(plane), hw_nvn);
d219673d	207
ba2d53fb BG	208	end:
	209	return &gdp->node_list[0];
	210	}
	211
	212	/**
	213	* sti_gdp_get_current_nodes
871bcdfe	214	* @plane: GDP plane
ba2d53fb BG	215	*
	216	* Look for GDP nodes that are currently read by the HW.
	217	*
	218	* RETURNS:
	219	* Pointer to the current GDP node list
	220	*/
	221	static
871bcdfe	222	struct sti_gdp_node_list sti_gdp_get_current_nodes(struct sti_plane plane)
ba2d53fb BG	223	{
ba2d53fb BG	224	int hw_nvn;
871bcdfe	225	struct sti_gdp *gdp = to_sti_gdp(plane);
ba2d53fb BG	226	unsigned int i;
ba2d53fb BG	227
871bcdfe	228	hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
ba2d53fb BG	229	if (!hw_nvn)
	230	goto end;
	231
ba2d53fb	232	for (i = 0; i < GDP_NODE_NB_BANK; i++)
a51fe84d BG	233	if ((hw_nvn == gdp->node_list[i].btm_field_paddr) \|\|
a51fe84d BG	234	(hw_nvn == gdp->node_list[i].top_field_paddr))
ba2d53fb BG	235	return &gdp->node_list[i];
	236
	237	end:
d219673d	238	DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
871bcdfe	239	hw_nvn, sti_plane_to_str(plane));
d219673d	240
ba2d53fb BG	241	return NULL;
	242	}
	243
	244	/**
871bcdfe VA	245	* sti_gdp_prepare
871bcdfe VA	246	* @plane: gdp plane
ba2d53fb BG	247	* @first_prepare: true if it is the first time this function is called
ba2d53fb BG	248	*
871bcdfe	249	* Update the free GDP node list according to the plane properties.
ba2d53fb BG	250	*
	251	* RETURNS:
	252	* 0 on success.
	253	*/
871bcdfe	254	static int sti_gdp_prepare(struct sti_plane *plane, bool first_prepare)
ba2d53fb BG	255	{
	256	struct sti_gdp_node_list *list;
	257	struct sti_gdp_node top_field, btm_field;
871bcdfe VA	258	struct drm_display_mode *mode = plane->mode;
	259	struct sti_gdp *gdp = to_sti_gdp(plane);
	260	struct device *dev = gdp->dev;
d219673d	261	struct sti_compositor *compo = dev_get_drvdata(dev);
ba2d53fb BG	262	int format;
	263	unsigned int depth, bpp;
	264	int rate = mode->clock * 1000;
	265	int res;
	266	u32 ydo, xdo, yds, xds;
	267
871bcdfe	268	list = sti_gdp_get_free_nodes(plane);
ba2d53fb BG	269	top_field = list->top_field;
	270	btm_field = list->btm_field;
	271
d219673d	272	dev_dbg(dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
871bcdfe	273	sti_plane_to_str(plane), top_field, btm_field);
d219673d	274
871bcdfe	275	/* Build the top field from plane params */
ba2d53fb BG	276	top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
ba2d53fb BG	277	top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
871bcdfe	278	format = sti_gdp_fourcc2format(plane->format);
ba2d53fb BG	279	if (format == -1) {
ba2d53fb BG	280	DRM_ERROR("Format not supported by GDP %.4s\n",
871bcdfe	281	(char *)&plane->format);
ba2d53fb BG	282	return 1;
	283	}
	284	top_field->gam_gdp_ctl \|= format;
	285	top_field->gam_gdp_ctl \|= sti_gdp_get_alpharange(format);
	286	top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
	287
	288	/* pixel memory location */
871bcdfe VA	289	drm_fb_get_bpp_depth(plane->format, &depth, &bpp);
	290	top_field->gam_gdp_pml = (u32)plane->paddr + plane->offsets[0];
	291	top_field->gam_gdp_pml += plane->src_x * (bpp >> 3);
	292	top_field->gam_gdp_pml += plane->src_y * plane->pitches[0];
ba2d53fb BG	293
ba2d53fb BG	294	/* input parameters */
871bcdfe	295	top_field->gam_gdp_pmp = plane->pitches[0];
ba2d53fb	296	top_field->gam_gdp_size =
871bcdfe VA	297	clamp_val(plane->src_h, 0, GAM_GDP_SIZE_MAX) << 16 \|
871bcdfe VA	298	clamp_val(plane->src_w, 0, GAM_GDP_SIZE_MAX);
ba2d53fb BG	299
ba2d53fb BG	300	/* output parameters */
871bcdfe VA	301	ydo = sti_vtg_get_line_number(*mode, plane->dst_y);
	302	yds = sti_vtg_get_line_number(*mode, plane->dst_y + plane->dst_h - 1);
	303	xdo = sti_vtg_get_pixel_number(*mode, plane->dst_x);
	304	xds = sti_vtg_get_pixel_number(*mode, plane->dst_x + plane->dst_w - 1);
ba2d53fb BG	305	top_field->gam_gdp_vpo = (ydo << 16) \| xdo;
	306	top_field->gam_gdp_vps = (yds << 16) \| xds;
	307
	308	/* Same content and chained together */
	309	memcpy(btm_field, top_field, sizeof(*btm_field));
a51fe84d BG	310	top_field->gam_gdp_nvn = list->btm_field_paddr;
a51fe84d BG	311	btm_field->gam_gdp_nvn = list->top_field_paddr;
ba2d53fb BG	312
ba2d53fb BG	313	/* Interlaced mode */
871bcdfe	314	if (plane->mode->flags & DRM_MODE_FLAG_INTERLACE)
ba2d53fb	315	btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
871bcdfe	316	plane->pitches[0];
ba2d53fb BG	317
ba2d53fb BG	318	if (first_prepare) {
d219673d	319	/* Register gdp callback */
871bcdfe	320	if (sti_vtg_register_client(plane->mixer_id == STI_MIXER_MAIN ?
d219673d	321	compo->vtg_main : compo->vtg_aux,
871bcdfe	322	&gdp->vtg_field_nb, plane->mixer_id)) {
d219673d BG	323	DRM_ERROR("Cannot register VTG notifier\n");
	324	return 1;
	325	}
	326
ba2d53fb BG	327	/* Set and enable gdp clock */
ba2d53fb BG	328	if (gdp->clk_pix) {
5e03abc5 BG	329	struct clk *clkp;
	330	/* According to the mixer used, the gdp pixel clock
	331	* should have a different parent clock. */
871bcdfe	332	if (plane->mixer_id == STI_MIXER_MAIN)
5e03abc5 BG	333	clkp = gdp->clk_main_parent;
	334	else
	335	clkp = gdp->clk_aux_parent;
	336
	337	if (clkp)
	338	clk_set_parent(gdp->clk_pix, clkp);
	339
ba2d53fb BG	340	res = clk_set_rate(gdp->clk_pix, rate);
	341	if (res < 0) {
	342	DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
	343	rate);
	344	return 1;
	345	}
	346
	347	if (clk_prepare_enable(gdp->clk_pix)) {
	348	DRM_ERROR("Failed to prepare/enable gdp\n");
	349	return 1;
	350	}
	351	}
	352	}
	353
	354	return 0;
	355	}
	356
	357	/**
871bcdfe VA	358	* sti_gdp_commit
871bcdfe VA	359	* @plane: gdp plane
ba2d53fb BG	360	*
	361	* Update the NVN field of the 'right' field of the current GDP node (being
	362	* used by the HW) with the address of the updated ('free') top field GDP node.
	363	* - In interlaced mode the 'right' field is the bottom field as we update
	364	* frames starting from their top field
	365	* - In progressive mode, we update both bottom and top fields which are
	366	* equal nodes.
	367	* At the next VSYNC, the updated node list will be used by the HW.
	368	*
	369	* RETURNS:
	370	* 0 on success.
	371	*/
871bcdfe	372	static int sti_gdp_commit(struct sti_plane *plane)
ba2d53fb	373	{
871bcdfe	374	struct sti_gdp_node_list *updated_list = sti_gdp_get_free_nodes(plane);
ba2d53fb BG	375	struct sti_gdp_node *updated_top_node = updated_list->top_field;
ba2d53fb BG	376	struct sti_gdp_node *updated_btm_node = updated_list->btm_field;
871bcdfe	377	struct sti_gdp *gdp = to_sti_gdp(plane);
a51fe84d BG	378	u32 dma_updated_top = updated_list->top_field_paddr;
a51fe84d BG	379	u32 dma_updated_btm = updated_list->btm_field_paddr;
871bcdfe	380	struct sti_gdp_node_list *curr_list = sti_gdp_get_current_nodes(plane);
ba2d53fb	381
871bcdfe VA	382	dev_dbg(gdp->dev, "%s %s top/btm_node:0x%p/0x%p\n", __func__,
	383	sti_plane_to_str(plane),
	384	updated_top_node, updated_btm_node);
	385	dev_dbg(gdp->dev, "Current NVN:0x%X\n",
	386	readl(gdp->regs + GAM_GDP_NVN_OFFSET));
	387	dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
	388	(unsigned long)plane->paddr,
	389	readl(gdp->regs + GAM_GDP_PML_OFFSET));
ba2d53fb BG	390
	391	if (curr_list == NULL) {
	392	/* First update or invalid node should directly write in the
	393	* hw register */
d219673d	394	DRM_DEBUG_DRIVER("%s first update (or invalid node)",
871bcdfe	395	sti_plane_to_str(plane));
d219673d	396
ba2d53fb BG	397	writel(gdp->is_curr_top == true ?
ba2d53fb BG	398	dma_updated_btm : dma_updated_top,
871bcdfe	399	gdp->regs + GAM_GDP_NVN_OFFSET);
ba2d53fb BG	400	return 0;
	401	}
	402
871bcdfe	403	if (plane->mode->flags & DRM_MODE_FLAG_INTERLACE) {
ba2d53fb BG	404	if (gdp->is_curr_top == true) {
	405	/* Do not update in the middle of the frame, but
	406	* postpone the update after the bottom field has
	407	* been displayed */
	408	curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
	409	} else {
	410	/* Direct update to avoid one frame delay */
	411	writel(dma_updated_top,
871bcdfe	412	gdp->regs + GAM_GDP_NVN_OFFSET);
ba2d53fb BG	413	}
	414	} else {
	415	/* Direct update for progressive to avoid one frame delay */
871bcdfe	416	writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
ba2d53fb BG	417	}
	418
	419	return 0;
	420	}
	421
	422	/**
871bcdfe VA	423	* sti_gdp_disable
871bcdfe VA	424	* @plane: gdp plane
ba2d53fb BG	425	*
	426	* Disable a GDP.
	427	*
	428	* RETURNS:
	429	* 0 on success.
	430	*/
871bcdfe	431	static int sti_gdp_disable(struct sti_plane *plane)
ba2d53fb BG	432	{
ba2d53fb BG	433	unsigned int i;
871bcdfe VA	434	struct sti_gdp *gdp = to_sti_gdp(plane);
871bcdfe VA	435	struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
d219673d	436
871bcdfe	437	DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(plane));
ba2d53fb BG	438
	439	/* Set the nodes as 'to be ignored on mixer' */
	440	for (i = 0; i < GDP_NODE_NB_BANK; i++) {
	441	gdp->node_list[i].top_field->gam_gdp_ppt \|= GAM_GDP_PPT_IGNORE;
	442	gdp->node_list[i].btm_field->gam_gdp_ppt \|= GAM_GDP_PPT_IGNORE;
	443	}
	444
871bcdfe	445	if (sti_vtg_unregister_client(plane->mixer_id == STI_MIXER_MAIN ?
d219673d BG	446	compo->vtg_main : compo->vtg_aux, &gdp->vtg_field_nb))
	447	DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
	448
ba2d53fb BG	449	if (gdp->clk_pix)
	450	clk_disable_unprepare(gdp->clk_pix);
	451
	452	return 0;
	453	}
	454
	455	/**
	456	* sti_gdp_field_cb
	457	* @nb: notifier block
	458	* @event: event message
	459	* @data: private data
	460	*
	461	* Handle VTG top field and bottom field event.
	462	*
	463	* RETURNS:
	464	* 0 on success.
	465	*/
	466	int sti_gdp_field_cb(struct notifier_block *nb,
	467	unsigned long event, void *data)
	468	{
	469	struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
	470
	471	switch (event) {
	472	case VTG_TOP_FIELD_EVENT:
	473	gdp->is_curr_top = true;
	474	break;
	475	case VTG_BOTTOM_FIELD_EVENT:
	476	gdp->is_curr_top = false;
	477	break;
	478	default:
	479	DRM_ERROR("unsupported event: %lu\n", event);
	480	break;
	481	}
	482
	483	return 0;
	484	}
	485
871bcdfe	486	static void sti_gdp_init(struct sti_gdp *gdp)
ba2d53fb	487	{
871bcdfe	488	struct device_node *np = gdp->dev->of_node;
a51fe84d	489	dma_addr_t dma_addr;
ba2d53fb BG	490	void *base;
	491	unsigned int i, size;
	492
	493	/* Allocate all the nodes within a single memory page */
	494	size = sizeof(struct sti_gdp_node) *
	495	GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
871bcdfe VA	496	base = dma_alloc_writecombine(gdp->dev,
871bcdfe VA	497	size, &dma_addr, GFP_KERNEL \| GFP_DMA);
a51fe84d	498
ba2d53fb BG	499	if (!base) {
	500	DRM_ERROR("Failed to allocate memory for GDP node\n");
	501	return;
	502	}
	503	memset(base, 0, size);
	504
	505	for (i = 0; i < GDP_NODE_NB_BANK; i++) {
a51fe84d	506	if (dma_addr & 0xF) {
ba2d53fb BG	507	DRM_ERROR("Mem alignment failed\n");
	508	return;
	509	}
	510	gdp->node_list[i].top_field = base;
a51fe84d BG	511	gdp->node_list[i].top_field_paddr = dma_addr;
a51fe84d BG	512
ba2d53fb BG	513	DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
ba2d53fb BG	514	base += sizeof(struct sti_gdp_node);
a51fe84d	515	dma_addr += sizeof(struct sti_gdp_node);
ba2d53fb	516
a51fe84d	517	if (dma_addr & 0xF) {
ba2d53fb BG	518	DRM_ERROR("Mem alignment failed\n");
	519	return;
	520	}
	521	gdp->node_list[i].btm_field = base;
a51fe84d	522	gdp->node_list[i].btm_field_paddr = dma_addr;
ba2d53fb BG	523	DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
ba2d53fb BG	524	base += sizeof(struct sti_gdp_node);
a51fe84d	525	dma_addr += sizeof(struct sti_gdp_node);
ba2d53fb BG	526	}
	527
	528	if (of_device_is_compatible(np, "st,stih407-compositor")) {
	529	/* GDP of STiH407 chip have its own pixel clock */
	530	char *clk_name;
	531
871bcdfe	532	switch (gdp->plane.desc) {
ba2d53fb BG	533	case STI_GDP_0:
	534	clk_name = "pix_gdp1";
	535	break;
	536	case STI_GDP_1:
	537	clk_name = "pix_gdp2";
	538	break;
	539	case STI_GDP_2:
	540	clk_name = "pix_gdp3";
	541	break;
	542	case STI_GDP_3:
	543	clk_name = "pix_gdp4";
	544	break;
	545	default:
	546	DRM_ERROR("GDP id not recognized\n");
	547	return;
	548	}
	549
871bcdfe	550	gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
ba2d53fb BG	551	if (IS_ERR(gdp->clk_pix))
ba2d53fb BG	552	DRM_ERROR("Cannot get %s clock\n", clk_name);
5e03abc5	553
871bcdfe	554	gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
5e03abc5 BG	555	if (IS_ERR(gdp->clk_main_parent))
	556	DRM_ERROR("Cannot get main_parent clock\n");
	557
871bcdfe	558	gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
5e03abc5 BG	559	if (IS_ERR(gdp->clk_aux_parent))
5e03abc5 BG	560	DRM_ERROR("Cannot get aux_parent clock\n");
ba2d53fb BG	561	}
	562	}
	563
871bcdfe	564	static const struct sti_plane_funcs gdp_plane_ops = {
ba2d53fb BG	565	.get_formats = sti_gdp_get_formats,
ba2d53fb BG	566	.get_nb_formats = sti_gdp_get_nb_formats,
871bcdfe VA	567	.prepare = sti_gdp_prepare,
	568	.commit = sti_gdp_commit,
	569	.disable = sti_gdp_disable,
ba2d53fb BG	570	};
ba2d53fb BG	571
871bcdfe VA	572	struct sti_plane sti_gdp_create(struct device dev, int desc,
871bcdfe VA	573	void __iomem *baseaddr)
ba2d53fb BG	574	{
	575	struct sti_gdp *gdp;
	576
	577	gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
	578	if (!gdp) {
	579	DRM_ERROR("Failed to allocate memory for GDP\n");
	580	return NULL;
	581	}
	582
871bcdfe VA	583	gdp->dev = dev;
	584	gdp->regs = baseaddr;
	585	gdp->plane.desc = desc;
	586	gdp->plane.ops = &gdp_plane_ops;
	587
ba2d53fb BG	588	gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
ba2d53fb BG	589
871bcdfe VA	590	sti_gdp_init(gdp);
	591
	592	return &gdp->plane;
ba2d53fb	593	}