Commit | Line | Data |
---|---|---|
ba2d53fb BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> | |
4 | * Fabien Dessenne <fabien.dessenne@st.com> | |
5 | * for STMicroelectronics. | |
6 | * License terms: GNU General Public License (GPL), version 2 | |
7 | */ | |
8 | ||
dd86dc2f | 9 | #include <drm/drm_atomic.h> |
29d1dc62 VA |
10 | #include <drm/drm_fb_cma_helper.h> |
11 | #include <drm/drm_gem_cma_helper.h> | |
12 | ||
d219673d | 13 | #include "sti_compositor.h" |
ba2d53fb | 14 | #include "sti_gdp.h" |
9e1f05b2 | 15 | #include "sti_plane.h" |
ba2d53fb BG |
16 | #include "sti_vtg.h" |
17 | ||
4af6b12a | 18 | #define ALPHASWITCH BIT(6) |
ba2d53fb | 19 | #define ENA_COLOR_FILL BIT(8) |
4af6b12a | 20 | #define BIGNOTLITTLE BIT(23) |
ba2d53fb BG |
21 | #define WAIT_NEXT_VSYNC BIT(31) |
22 | ||
23 | /* GDP color formats */ | |
24 | #define GDP_RGB565 0x00 | |
25 | #define GDP_RGB888 0x01 | |
26 | #define GDP_RGB888_32 0x02 | |
8adb5776 | 27 | #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) |
ba2d53fb BG |
28 | #define GDP_ARGB8565 0x04 |
29 | #define GDP_ARGB8888 0x05 | |
29d1dc62 | 30 | #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) |
ba2d53fb BG |
31 | #define GDP_ARGB1555 0x06 |
32 | #define GDP_ARGB4444 0x07 | |
ba2d53fb BG |
33 | |
34 | #define GAM_GDP_CTL_OFFSET 0x00 | |
35 | #define GAM_GDP_AGC_OFFSET 0x04 | |
36 | #define GAM_GDP_VPO_OFFSET 0x0C | |
37 | #define GAM_GDP_VPS_OFFSET 0x10 | |
38 | #define GAM_GDP_PML_OFFSET 0x14 | |
39 | #define GAM_GDP_PMP_OFFSET 0x18 | |
40 | #define GAM_GDP_SIZE_OFFSET 0x1C | |
41 | #define GAM_GDP_NVN_OFFSET 0x24 | |
42 | #define GAM_GDP_KEY1_OFFSET 0x28 | |
43 | #define GAM_GDP_KEY2_OFFSET 0x2C | |
44 | #define GAM_GDP_PPT_OFFSET 0x34 | |
45 | #define GAM_GDP_CML_OFFSET 0x3C | |
46 | #define GAM_GDP_MST_OFFSET 0x68 | |
47 | ||
48 | #define GAM_GDP_ALPHARANGE_255 BIT(5) | |
49 | #define GAM_GDP_AGC_FULL_RANGE 0x00808080 | |
50 | #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) | |
51 | #define GAM_GDP_SIZE_MAX 0x7FF | |
52 | ||
29d1dc62 VA |
53 | #define GDP_NODE_NB_BANK 2 |
54 | #define GDP_NODE_PER_FIELD 2 | |
ba2d53fb BG |
55 | |
56 | struct sti_gdp_node { | |
57 | u32 gam_gdp_ctl; | |
58 | u32 gam_gdp_agc; | |
59 | u32 reserved1; | |
60 | u32 gam_gdp_vpo; | |
61 | u32 gam_gdp_vps; | |
62 | u32 gam_gdp_pml; | |
63 | u32 gam_gdp_pmp; | |
64 | u32 gam_gdp_size; | |
65 | u32 reserved2; | |
66 | u32 gam_gdp_nvn; | |
67 | u32 gam_gdp_key1; | |
68 | u32 gam_gdp_key2; | |
69 | u32 reserved3; | |
70 | u32 gam_gdp_ppt; | |
71 | u32 reserved4; | |
72 | u32 gam_gdp_cml; | |
73 | }; | |
74 | ||
75 | struct sti_gdp_node_list { | |
76 | struct sti_gdp_node *top_field; | |
a51fe84d | 77 | dma_addr_t top_field_paddr; |
ba2d53fb | 78 | struct sti_gdp_node *btm_field; |
a51fe84d | 79 | dma_addr_t btm_field_paddr; |
ba2d53fb BG |
80 | }; |
81 | ||
82 | /** | |
83 | * STI GDP structure | |
84 | * | |
871bcdfe VA |
85 | * @sti_plane: sti_plane structure |
86 | * @dev: driver device | |
87 | * @regs: gdp registers | |
ba2d53fb | 88 | * @clk_pix: pixel clock for the current gdp |
5e03abc5 BG |
89 | * @clk_main_parent: gdp parent clock if main path used |
90 | * @clk_aux_parent: gdp parent clock if aux path used | |
ba2d53fb BG |
91 | * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification |
92 | * @is_curr_top: true if the current node processed is the top field | |
871bcdfe | 93 | * @node_list: array of node list |
20c47601 | 94 | * @vtg: registered vtg |
ba2d53fb BG |
95 | */ |
96 | struct sti_gdp { | |
871bcdfe VA |
97 | struct sti_plane plane; |
98 | struct device *dev; | |
99 | void __iomem *regs; | |
ba2d53fb | 100 | struct clk *clk_pix; |
5e03abc5 BG |
101 | struct clk *clk_main_parent; |
102 | struct clk *clk_aux_parent; | |
ba2d53fb BG |
103 | struct notifier_block vtg_field_nb; |
104 | bool is_curr_top; | |
105 | struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; | |
20c47601 | 106 | struct sti_vtg *vtg; |
ba2d53fb BG |
107 | }; |
108 | ||
871bcdfe | 109 | #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) |
ba2d53fb BG |
110 | |
111 | static const uint32_t gdp_supported_formats[] = { | |
112 | DRM_FORMAT_XRGB8888, | |
8adb5776 | 113 | DRM_FORMAT_XBGR8888, |
ba2d53fb | 114 | DRM_FORMAT_ARGB8888, |
4af6b12a | 115 | DRM_FORMAT_ABGR8888, |
ba2d53fb BG |
116 | DRM_FORMAT_ARGB4444, |
117 | DRM_FORMAT_ARGB1555, | |
118 | DRM_FORMAT_RGB565, | |
119 | DRM_FORMAT_RGB888, | |
ba2d53fb BG |
120 | }; |
121 | ||
ba2d53fb BG |
122 | static int sti_gdp_fourcc2format(int fourcc) |
123 | { | |
124 | switch (fourcc) { | |
125 | case DRM_FORMAT_XRGB8888: | |
126 | return GDP_RGB888_32; | |
8adb5776 FD |
127 | case DRM_FORMAT_XBGR8888: |
128 | return GDP_XBGR8888; | |
ba2d53fb BG |
129 | case DRM_FORMAT_ARGB8888: |
130 | return GDP_ARGB8888; | |
4af6b12a BG |
131 | case DRM_FORMAT_ABGR8888: |
132 | return GDP_ABGR8888; | |
ba2d53fb BG |
133 | case DRM_FORMAT_ARGB4444: |
134 | return GDP_ARGB4444; | |
135 | case DRM_FORMAT_ARGB1555: | |
136 | return GDP_ARGB1555; | |
137 | case DRM_FORMAT_RGB565: | |
138 | return GDP_RGB565; | |
139 | case DRM_FORMAT_RGB888: | |
140 | return GDP_RGB888; | |
ba2d53fb BG |
141 | } |
142 | return -1; | |
143 | } | |
144 | ||
145 | static int sti_gdp_get_alpharange(int format) | |
146 | { | |
147 | switch (format) { | |
148 | case GDP_ARGB8565: | |
149 | case GDP_ARGB8888: | |
4af6b12a | 150 | case GDP_ABGR8888: |
ba2d53fb BG |
151 | return GAM_GDP_ALPHARANGE_255; |
152 | } | |
153 | return 0; | |
154 | } | |
155 | ||
156 | /** | |
157 | * sti_gdp_get_free_nodes | |
29d1dc62 | 158 | * @gdp: gdp pointer |
ba2d53fb BG |
159 | * |
160 | * Look for a GDP node list that is not currently read by the HW. | |
161 | * | |
162 | * RETURNS: | |
163 | * Pointer to the free GDP node list | |
164 | */ | |
29d1dc62 | 165 | static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) |
ba2d53fb BG |
166 | { |
167 | int hw_nvn; | |
ba2d53fb BG |
168 | unsigned int i; |
169 | ||
871bcdfe | 170 | hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); |
ba2d53fb BG |
171 | if (!hw_nvn) |
172 | goto end; | |
173 | ||
ba2d53fb | 174 | for (i = 0; i < GDP_NODE_NB_BANK; i++) |
a51fe84d BG |
175 | if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && |
176 | (hw_nvn != gdp->node_list[i].top_field_paddr)) | |
ba2d53fb BG |
177 | return &gdp->node_list[i]; |
178 | ||
d219673d BG |
179 | /* in hazardious cases restart with the first node */ |
180 | DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", | |
29d1dc62 | 181 | sti_plane_to_str(&gdp->plane), hw_nvn); |
d219673d | 182 | |
ba2d53fb BG |
183 | end: |
184 | return &gdp->node_list[0]; | |
185 | } | |
186 | ||
187 | /** | |
188 | * sti_gdp_get_current_nodes | |
29d1dc62 | 189 | * @gdp: gdp pointer |
ba2d53fb BG |
190 | * |
191 | * Look for GDP nodes that are currently read by the HW. | |
192 | * | |
193 | * RETURNS: | |
194 | * Pointer to the current GDP node list | |
195 | */ | |
196 | static | |
29d1dc62 | 197 | struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) |
ba2d53fb BG |
198 | { |
199 | int hw_nvn; | |
ba2d53fb BG |
200 | unsigned int i; |
201 | ||
871bcdfe | 202 | hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); |
ba2d53fb BG |
203 | if (!hw_nvn) |
204 | goto end; | |
205 | ||
ba2d53fb | 206 | for (i = 0; i < GDP_NODE_NB_BANK; i++) |
a51fe84d BG |
207 | if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || |
208 | (hw_nvn == gdp->node_list[i].top_field_paddr)) | |
ba2d53fb BG |
209 | return &gdp->node_list[i]; |
210 | ||
211 | end: | |
d219673d | 212 | DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", |
29d1dc62 | 213 | hw_nvn, sti_plane_to_str(&gdp->plane)); |
d219673d | 214 | |
ba2d53fb BG |
215 | return NULL; |
216 | } | |
217 | ||
ba2d53fb | 218 | /** |
871bcdfe | 219 | * sti_gdp_disable |
29d1dc62 | 220 | * @gdp: gdp pointer |
ba2d53fb BG |
221 | * |
222 | * Disable a GDP. | |
ba2d53fb | 223 | */ |
29d1dc62 | 224 | static void sti_gdp_disable(struct sti_gdp *gdp) |
ba2d53fb | 225 | { |
29d1dc62 | 226 | unsigned int i; |
d219673d | 227 | |
29d1dc62 | 228 | DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); |
ba2d53fb BG |
229 | |
230 | /* Set the nodes as 'to be ignored on mixer' */ | |
231 | for (i = 0; i < GDP_NODE_NB_BANK; i++) { | |
232 | gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; | |
233 | gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; | |
234 | } | |
235 | ||
20c47601 | 236 | if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) |
d219673d BG |
237 | DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); |
238 | ||
ba2d53fb BG |
239 | if (gdp->clk_pix) |
240 | clk_disable_unprepare(gdp->clk_pix); | |
241 | ||
29d1dc62 | 242 | gdp->plane.status = STI_PLANE_DISABLED; |
ba2d53fb BG |
243 | } |
244 | ||
245 | /** | |
246 | * sti_gdp_field_cb | |
247 | * @nb: notifier block | |
248 | * @event: event message | |
249 | * @data: private data | |
250 | * | |
251 | * Handle VTG top field and bottom field event. | |
252 | * | |
253 | * RETURNS: | |
254 | * 0 on success. | |
255 | */ | |
256 | int sti_gdp_field_cb(struct notifier_block *nb, | |
257 | unsigned long event, void *data) | |
258 | { | |
259 | struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); | |
260 | ||
29d1dc62 VA |
261 | if (gdp->plane.status == STI_PLANE_FLUSHING) { |
262 | /* disable need to be synchronize on vsync event */ | |
263 | DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", | |
264 | sti_plane_to_str(&gdp->plane)); | |
265 | ||
266 | sti_gdp_disable(gdp); | |
267 | } | |
268 | ||
ba2d53fb BG |
269 | switch (event) { |
270 | case VTG_TOP_FIELD_EVENT: | |
271 | gdp->is_curr_top = true; | |
272 | break; | |
273 | case VTG_BOTTOM_FIELD_EVENT: | |
274 | gdp->is_curr_top = false; | |
275 | break; | |
276 | default: | |
277 | DRM_ERROR("unsupported event: %lu\n", event); | |
278 | break; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
871bcdfe | 284 | static void sti_gdp_init(struct sti_gdp *gdp) |
ba2d53fb | 285 | { |
871bcdfe | 286 | struct device_node *np = gdp->dev->of_node; |
a51fe84d | 287 | dma_addr_t dma_addr; |
ba2d53fb BG |
288 | void *base; |
289 | unsigned int i, size; | |
290 | ||
291 | /* Allocate all the nodes within a single memory page */ | |
292 | size = sizeof(struct sti_gdp_node) * | |
293 | GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; | |
871bcdfe VA |
294 | base = dma_alloc_writecombine(gdp->dev, |
295 | size, &dma_addr, GFP_KERNEL | GFP_DMA); | |
a51fe84d | 296 | |
ba2d53fb BG |
297 | if (!base) { |
298 | DRM_ERROR("Failed to allocate memory for GDP node\n"); | |
299 | return; | |
300 | } | |
301 | memset(base, 0, size); | |
302 | ||
303 | for (i = 0; i < GDP_NODE_NB_BANK; i++) { | |
a51fe84d | 304 | if (dma_addr & 0xF) { |
ba2d53fb BG |
305 | DRM_ERROR("Mem alignment failed\n"); |
306 | return; | |
307 | } | |
308 | gdp->node_list[i].top_field = base; | |
a51fe84d BG |
309 | gdp->node_list[i].top_field_paddr = dma_addr; |
310 | ||
ba2d53fb BG |
311 | DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); |
312 | base += sizeof(struct sti_gdp_node); | |
a51fe84d | 313 | dma_addr += sizeof(struct sti_gdp_node); |
ba2d53fb | 314 | |
a51fe84d | 315 | if (dma_addr & 0xF) { |
ba2d53fb BG |
316 | DRM_ERROR("Mem alignment failed\n"); |
317 | return; | |
318 | } | |
319 | gdp->node_list[i].btm_field = base; | |
a51fe84d | 320 | gdp->node_list[i].btm_field_paddr = dma_addr; |
ba2d53fb BG |
321 | DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); |
322 | base += sizeof(struct sti_gdp_node); | |
a51fe84d | 323 | dma_addr += sizeof(struct sti_gdp_node); |
ba2d53fb BG |
324 | } |
325 | ||
326 | if (of_device_is_compatible(np, "st,stih407-compositor")) { | |
327 | /* GDP of STiH407 chip have its own pixel clock */ | |
328 | char *clk_name; | |
329 | ||
871bcdfe | 330 | switch (gdp->plane.desc) { |
ba2d53fb BG |
331 | case STI_GDP_0: |
332 | clk_name = "pix_gdp1"; | |
333 | break; | |
334 | case STI_GDP_1: | |
335 | clk_name = "pix_gdp2"; | |
336 | break; | |
337 | case STI_GDP_2: | |
338 | clk_name = "pix_gdp3"; | |
339 | break; | |
340 | case STI_GDP_3: | |
341 | clk_name = "pix_gdp4"; | |
342 | break; | |
343 | default: | |
344 | DRM_ERROR("GDP id not recognized\n"); | |
345 | return; | |
346 | } | |
347 | ||
871bcdfe | 348 | gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); |
ba2d53fb BG |
349 | if (IS_ERR(gdp->clk_pix)) |
350 | DRM_ERROR("Cannot get %s clock\n", clk_name); | |
5e03abc5 | 351 | |
871bcdfe | 352 | gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); |
5e03abc5 BG |
353 | if (IS_ERR(gdp->clk_main_parent)) |
354 | DRM_ERROR("Cannot get main_parent clock\n"); | |
355 | ||
871bcdfe | 356 | gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); |
5e03abc5 BG |
357 | if (IS_ERR(gdp->clk_aux_parent)) |
358 | DRM_ERROR("Cannot get aux_parent clock\n"); | |
ba2d53fb BG |
359 | } |
360 | } | |
361 | ||
a5b9a713 BH |
362 | /** |
363 | * sti_gdp_get_dst | |
364 | * @dev: device | |
365 | * @dst: requested destination size | |
366 | * @src: source size | |
367 | * | |
368 | * Return the cropped / clamped destination size | |
369 | * | |
370 | * RETURNS: | |
371 | * cropped / clamped destination size | |
372 | */ | |
373 | static int sti_gdp_get_dst(struct device *dev, int dst, int src) | |
374 | { | |
375 | if (dst == src) | |
376 | return dst; | |
377 | ||
378 | if (dst < src) { | |
379 | dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); | |
380 | return dst; | |
381 | } | |
382 | ||
383 | dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); | |
384 | return src; | |
385 | } | |
386 | ||
dd86dc2f VA |
387 | static int sti_gdp_atomic_check(struct drm_plane *drm_plane, |
388 | struct drm_plane_state *state) | |
29d1dc62 | 389 | { |
29d1dc62 VA |
390 | struct sti_plane *plane = to_sti_plane(drm_plane); |
391 | struct sti_gdp *gdp = to_sti_gdp(plane); | |
392 | struct drm_crtc *crtc = state->crtc; | |
393 | struct sti_compositor *compo = dev_get_drvdata(gdp->dev); | |
394 | struct drm_framebuffer *fb = state->fb; | |
395 | bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false; | |
dd86dc2f | 396 | struct drm_crtc_state *crtc_state; |
29d1dc62 VA |
397 | struct sti_mixer *mixer; |
398 | struct drm_display_mode *mode; | |
399 | int dst_x, dst_y, dst_w, dst_h; | |
400 | int src_x, src_y, src_w, src_h; | |
dd86dc2f VA |
401 | int format; |
402 | ||
403 | /* no need for further checks if the plane is being disabled */ | |
404 | if (!crtc || !fb) | |
405 | return 0; | |
406 | ||
407 | mixer = to_sti_mixer(crtc); | |
408 | crtc_state = drm_atomic_get_crtc_state(state->state, crtc); | |
409 | mode = &crtc_state->mode; | |
410 | dst_x = state->crtc_x; | |
411 | dst_y = state->crtc_y; | |
412 | dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); | |
413 | dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); | |
414 | /* src_x are in 16.16 format */ | |
415 | src_x = state->src_x >> 16; | |
416 | src_y = state->src_y >> 16; | |
417 | src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); | |
418 | src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); | |
419 | ||
420 | format = sti_gdp_fourcc2format(fb->pixel_format); | |
421 | if (format == -1) { | |
422 | DRM_ERROR("Format not supported by GDP %.4s\n", | |
423 | (char *)&fb->pixel_format); | |
424 | return -EINVAL; | |
425 | } | |
426 | ||
427 | if (!drm_fb_cma_get_gem_obj(fb, 0)) { | |
428 | DRM_ERROR("Can't get CMA GEM object for fb\n"); | |
429 | return -EINVAL; | |
430 | } | |
431 | ||
432 | if (first_prepare) { | |
433 | /* Register gdp callback */ | |
434 | gdp->vtg = mixer->id == STI_MIXER_MAIN ? | |
435 | compo->vtg_main : compo->vtg_aux; | |
436 | if (sti_vtg_register_client(gdp->vtg, | |
437 | &gdp->vtg_field_nb, crtc)) { | |
438 | DRM_ERROR("Cannot register VTG notifier\n"); | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | /* Set and enable gdp clock */ | |
443 | if (gdp->clk_pix) { | |
444 | struct clk *clkp; | |
445 | int rate = mode->clock * 1000; | |
446 | int res; | |
447 | ||
448 | /* | |
449 | * According to the mixer used, the gdp pixel clock | |
450 | * should have a different parent clock. | |
451 | */ | |
452 | if (mixer->id == STI_MIXER_MAIN) | |
453 | clkp = gdp->clk_main_parent; | |
454 | else | |
455 | clkp = gdp->clk_aux_parent; | |
456 | ||
457 | if (clkp) | |
458 | clk_set_parent(gdp->clk_pix, clkp); | |
459 | ||
460 | res = clk_set_rate(gdp->clk_pix, rate); | |
461 | if (res < 0) { | |
462 | DRM_ERROR("Cannot set rate (%dHz) for gdp\n", | |
463 | rate); | |
464 | return -EINVAL; | |
465 | } | |
466 | ||
467 | if (clk_prepare_enable(gdp->clk_pix)) { | |
468 | DRM_ERROR("Failed to prepare/enable gdp\n"); | |
469 | return -EINVAL; | |
470 | } | |
471 | } | |
472 | } | |
473 | ||
474 | DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", | |
475 | crtc->base.id, sti_mixer_to_str(mixer), | |
476 | drm_plane->base.id, sti_plane_to_str(plane)); | |
477 | DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", | |
478 | sti_plane_to_str(plane), | |
479 | dst_w, dst_h, dst_x, dst_y, | |
480 | src_w, src_h, src_x, src_y); | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static void sti_gdp_atomic_update(struct drm_plane *drm_plane, | |
486 | struct drm_plane_state *oldstate) | |
487 | { | |
488 | struct drm_plane_state *state = drm_plane->state; | |
489 | struct sti_plane *plane = to_sti_plane(drm_plane); | |
490 | struct sti_gdp *gdp = to_sti_gdp(plane); | |
491 | struct drm_crtc *crtc = state->crtc; | |
492 | struct drm_framebuffer *fb = state->fb; | |
493 | struct drm_display_mode *mode; | |
494 | int dst_x, dst_y, dst_w, dst_h; | |
495 | int src_x, src_y, src_w, src_h; | |
29d1dc62 VA |
496 | struct drm_gem_cma_object *cma_obj; |
497 | struct sti_gdp_node_list *list; | |
498 | struct sti_gdp_node_list *curr_list; | |
499 | struct sti_gdp_node *top_field, *btm_field; | |
500 | u32 dma_updated_top; | |
501 | u32 dma_updated_btm; | |
502 | int format; | |
503 | unsigned int depth, bpp; | |
504 | u32 ydo, xdo, yds, xds; | |
29d1dc62 | 505 | |
dd86dc2f | 506 | if (!crtc || !fb) |
29d1dc62 VA |
507 | return; |
508 | ||
29d1dc62 VA |
509 | mode = &crtc->mode; |
510 | dst_x = state->crtc_x; | |
511 | dst_y = state->crtc_y; | |
512 | dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); | |
513 | dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); | |
514 | /* src_x are in 16.16 format */ | |
515 | src_x = state->src_x >> 16; | |
516 | src_y = state->src_y >> 16; | |
a5b9a713 BH |
517 | src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); |
518 | src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); | |
29d1dc62 | 519 | |
29d1dc62 VA |
520 | list = sti_gdp_get_free_nodes(gdp); |
521 | top_field = list->top_field; | |
522 | btm_field = list->btm_field; | |
523 | ||
524 | dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, | |
525 | sti_plane_to_str(plane), top_field, btm_field); | |
526 | ||
527 | /* build the top field */ | |
528 | top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; | |
529 | top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; | |
530 | format = sti_gdp_fourcc2format(fb->pixel_format); | |
29d1dc62 VA |
531 | top_field->gam_gdp_ctl |= format; |
532 | top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); | |
533 | top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; | |
534 | ||
535 | cma_obj = drm_fb_cma_get_gem_obj(fb, 0); | |
29d1dc62 VA |
536 | |
537 | DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, | |
538 | (char *)&fb->pixel_format, | |
539 | (unsigned long)cma_obj->paddr); | |
540 | ||
541 | /* pixel memory location */ | |
542 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); | |
543 | top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; | |
544 | top_field->gam_gdp_pml += src_x * (bpp >> 3); | |
545 | top_field->gam_gdp_pml += src_y * fb->pitches[0]; | |
546 | ||
a5b9a713 BH |
547 | /* output parameters (clamped / cropped) */ |
548 | dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); | |
549 | dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); | |
29d1dc62 VA |
550 | ydo = sti_vtg_get_line_number(*mode, dst_y); |
551 | yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); | |
552 | xdo = sti_vtg_get_pixel_number(*mode, dst_x); | |
553 | xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); | |
554 | top_field->gam_gdp_vpo = (ydo << 16) | xdo; | |
555 | top_field->gam_gdp_vps = (yds << 16) | xds; | |
556 | ||
704cb30c VA |
557 | /* input parameters */ |
558 | src_w = dst_w; | |
559 | top_field->gam_gdp_pmp = fb->pitches[0]; | |
560 | top_field->gam_gdp_size = src_h << 16 | src_w; | |
561 | ||
29d1dc62 VA |
562 | /* Same content and chained together */ |
563 | memcpy(btm_field, top_field, sizeof(*btm_field)); | |
564 | top_field->gam_gdp_nvn = list->btm_field_paddr; | |
565 | btm_field->gam_gdp_nvn = list->top_field_paddr; | |
566 | ||
567 | /* Interlaced mode */ | |
568 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
569 | btm_field->gam_gdp_pml = top_field->gam_gdp_pml + | |
570 | fb->pitches[0]; | |
571 | ||
29d1dc62 VA |
572 | /* Update the NVN field of the 'right' field of the current GDP node |
573 | * (being used by the HW) with the address of the updated ('free') top | |
574 | * field GDP node. | |
575 | * - In interlaced mode the 'right' field is the bottom field as we | |
576 | * update frames starting from their top field | |
577 | * - In progressive mode, we update both bottom and top fields which | |
578 | * are equal nodes. | |
579 | * At the next VSYNC, the updated node list will be used by the HW. | |
580 | */ | |
581 | curr_list = sti_gdp_get_current_nodes(gdp); | |
582 | dma_updated_top = list->top_field_paddr; | |
583 | dma_updated_btm = list->btm_field_paddr; | |
584 | ||
585 | dev_dbg(gdp->dev, "Current NVN:0x%X\n", | |
586 | readl(gdp->regs + GAM_GDP_NVN_OFFSET)); | |
587 | dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", | |
588 | (unsigned long)cma_obj->paddr, | |
589 | readl(gdp->regs + GAM_GDP_PML_OFFSET)); | |
590 | ||
591 | if (!curr_list) { | |
592 | /* First update or invalid node should directly write in the | |
593 | * hw register */ | |
594 | DRM_DEBUG_DRIVER("%s first update (or invalid node)", | |
595 | sti_plane_to_str(plane)); | |
596 | ||
597 | writel(gdp->is_curr_top ? | |
598 | dma_updated_btm : dma_updated_top, | |
599 | gdp->regs + GAM_GDP_NVN_OFFSET); | |
600 | goto end; | |
601 | } | |
602 | ||
603 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
604 | if (gdp->is_curr_top) { | |
605 | /* Do not update in the middle of the frame, but | |
606 | * postpone the update after the bottom field has | |
607 | * been displayed */ | |
608 | curr_list->btm_field->gam_gdp_nvn = dma_updated_top; | |
609 | } else { | |
610 | /* Direct update to avoid one frame delay */ | |
611 | writel(dma_updated_top, | |
612 | gdp->regs + GAM_GDP_NVN_OFFSET); | |
613 | } | |
614 | } else { | |
615 | /* Direct update for progressive to avoid one frame delay */ | |
616 | writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); | |
617 | } | |
618 | ||
619 | end: | |
620 | plane->status = STI_PLANE_UPDATED; | |
621 | } | |
622 | ||
623 | static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, | |
624 | struct drm_plane_state *oldstate) | |
625 | { | |
626 | struct sti_plane *plane = to_sti_plane(drm_plane); | |
29d1dc62 VA |
627 | |
628 | if (!drm_plane->crtc) { | |
629 | DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", | |
630 | drm_plane->base.id); | |
631 | return; | |
632 | } | |
633 | ||
634 | DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", | |
dd86dc2f VA |
635 | drm_plane->crtc->base.id, |
636 | sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)), | |
29d1dc62 VA |
637 | drm_plane->base.id, sti_plane_to_str(plane)); |
638 | ||
639 | plane->status = STI_PLANE_DISABLING; | |
640 | } | |
641 | ||
642 | static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { | |
dd86dc2f | 643 | .atomic_check = sti_gdp_atomic_check, |
29d1dc62 VA |
644 | .atomic_update = sti_gdp_atomic_update, |
645 | .atomic_disable = sti_gdp_atomic_disable, | |
ba2d53fb BG |
646 | }; |
647 | ||
29d1dc62 VA |
648 | struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, |
649 | struct device *dev, int desc, | |
650 | void __iomem *baseaddr, | |
651 | unsigned int possible_crtcs, | |
652 | enum drm_plane_type type) | |
ba2d53fb BG |
653 | { |
654 | struct sti_gdp *gdp; | |
29d1dc62 | 655 | int res; |
ba2d53fb BG |
656 | |
657 | gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); | |
658 | if (!gdp) { | |
659 | DRM_ERROR("Failed to allocate memory for GDP\n"); | |
660 | return NULL; | |
661 | } | |
662 | ||
871bcdfe VA |
663 | gdp->dev = dev; |
664 | gdp->regs = baseaddr; | |
665 | gdp->plane.desc = desc; | |
29d1dc62 | 666 | gdp->plane.status = STI_PLANE_DISABLED; |
871bcdfe | 667 | |
ba2d53fb BG |
668 | gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; |
669 | ||
871bcdfe VA |
670 | sti_gdp_init(gdp); |
671 | ||
29d1dc62 VA |
672 | res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, |
673 | possible_crtcs, | |
674 | &sti_plane_helpers_funcs, | |
675 | gdp_supported_formats, | |
676 | ARRAY_SIZE(gdp_supported_formats), | |
b0b3b795 | 677 | type, NULL); |
29d1dc62 VA |
678 | if (res) { |
679 | DRM_ERROR("Failed to initialize universal plane\n"); | |
680 | goto err; | |
681 | } | |
682 | ||
683 | drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); | |
684 | ||
685 | sti_plane_init_property(&gdp->plane, type); | |
686 | ||
687 | return &gdp->plane.drm_plane; | |
688 | ||
689 | err: | |
690 | devm_kfree(dev, gdp); | |
691 | return NULL; | |
ba2d53fb | 692 | } |