Commit | Line | Data |
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5402626c BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | */ | |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/component.h> | |
7ea6e6e4 | 9 | #include <linux/debugfs.h> |
5402626c BG |
10 | #include <linux/hdmi.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/of_gpio.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/reset.h> | |
15 | ||
16 | #include <drm/drmP.h> | |
de4b00b0 | 17 | #include <drm/drm_atomic_helper.h> |
5402626c BG |
18 | #include <drm/drm_crtc_helper.h> |
19 | #include <drm/drm_edid.h> | |
20 | ||
2c348e50 AP |
21 | #include <sound/hdmi-codec.h> |
22 | ||
5402626c BG |
23 | #include "sti_hdmi.h" |
24 | #include "sti_hdmi_tx3g4c28phy.h" | |
25 | #include "sti_hdmi_tx3g0c55phy.h" | |
26 | #include "sti_vtg.h" | |
27 | ||
28 | #define HDMI_CFG 0x0000 | |
29 | #define HDMI_INT_EN 0x0004 | |
30 | #define HDMI_INT_STA 0x0008 | |
31 | #define HDMI_INT_CLR 0x000C | |
32 | #define HDMI_STA 0x0010 | |
33 | #define HDMI_ACTIVE_VID_XMIN 0x0100 | |
34 | #define HDMI_ACTIVE_VID_XMAX 0x0104 | |
35 | #define HDMI_ACTIVE_VID_YMIN 0x0108 | |
36 | #define HDMI_ACTIVE_VID_YMAX 0x010C | |
37 | #define HDMI_DFLT_CHL0_DAT 0x0110 | |
38 | #define HDMI_DFLT_CHL1_DAT 0x0114 | |
39 | #define HDMI_DFLT_CHL2_DAT 0x0118 | |
2c348e50 AP |
40 | #define HDMI_AUDIO_CFG 0x0200 |
41 | #define HDMI_SPDIF_FIFO_STATUS 0x0204 | |
5402626c BG |
42 | #define HDMI_SW_DI_1_HEAD_WORD 0x0210 |
43 | #define HDMI_SW_DI_1_PKT_WORD0 0x0214 | |
44 | #define HDMI_SW_DI_1_PKT_WORD1 0x0218 | |
45 | #define HDMI_SW_DI_1_PKT_WORD2 0x021C | |
46 | #define HDMI_SW_DI_1_PKT_WORD3 0x0220 | |
47 | #define HDMI_SW_DI_1_PKT_WORD4 0x0224 | |
48 | #define HDMI_SW_DI_1_PKT_WORD5 0x0228 | |
49 | #define HDMI_SW_DI_1_PKT_WORD6 0x022C | |
50 | #define HDMI_SW_DI_CFG 0x0230 | |
2c348e50 AP |
51 | #define HDMI_SAMPLE_FLAT_MASK 0x0244 |
52 | #define HDMI_AUDN 0x0400 | |
53 | #define HDMI_AUD_CTS 0x0404 | |
cffe1e89 AP |
54 | #define HDMI_SW_DI_2_HEAD_WORD 0x0600 |
55 | #define HDMI_SW_DI_2_PKT_WORD0 0x0604 | |
56 | #define HDMI_SW_DI_2_PKT_WORD1 0x0608 | |
57 | #define HDMI_SW_DI_2_PKT_WORD2 0x060C | |
58 | #define HDMI_SW_DI_2_PKT_WORD3 0x0610 | |
59 | #define HDMI_SW_DI_2_PKT_WORD4 0x0614 | |
60 | #define HDMI_SW_DI_2_PKT_WORD5 0x0618 | |
61 | #define HDMI_SW_DI_2_PKT_WORD6 0x061C | |
e42e7bd7 VA |
62 | #define HDMI_SW_DI_3_HEAD_WORD 0x0620 |
63 | #define HDMI_SW_DI_3_PKT_WORD0 0x0624 | |
64 | #define HDMI_SW_DI_3_PKT_WORD1 0x0628 | |
65 | #define HDMI_SW_DI_3_PKT_WORD2 0x062C | |
66 | #define HDMI_SW_DI_3_PKT_WORD3 0x0630 | |
67 | #define HDMI_SW_DI_3_PKT_WORD4 0x0634 | |
68 | #define HDMI_SW_DI_3_PKT_WORD5 0x0638 | |
69 | #define HDMI_SW_DI_3_PKT_WORD6 0x063C | |
5402626c BG |
70 | |
71 | #define HDMI_IFRAME_SLOT_AVI 1 | |
cffe1e89 | 72 | #define HDMI_IFRAME_SLOT_AUDIO 2 |
e42e7bd7 | 73 | #define HDMI_IFRAME_SLOT_VENDOR 3 |
5402626c BG |
74 | |
75 | #define XCAT(prefix, x, suffix) prefix ## x ## suffix | |
76 | #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD) | |
77 | #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0) | |
78 | #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1) | |
79 | #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2) | |
80 | #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3) | |
81 | #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4) | |
82 | #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5) | |
83 | #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6) | |
84 | ||
181975a2 VA |
85 | #define HDMI_SW_DI_MAX_WORD 7 |
86 | ||
5402626c BG |
87 | #define HDMI_IFRAME_DISABLED 0x0 |
88 | #define HDMI_IFRAME_SINGLE_SHOT 0x1 | |
89 | #define HDMI_IFRAME_FIELD 0x2 | |
90 | #define HDMI_IFRAME_FRAME 0x3 | |
91 | #define HDMI_IFRAME_MASK 0x3 | |
92 | #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */ | |
93 | ||
94 | #define HDMI_CFG_DEVICE_EN BIT(0) | |
95 | #define HDMI_CFG_HDMI_NOT_DVI BIT(1) | |
96 | #define HDMI_CFG_HDCP_EN BIT(2) | |
97 | #define HDMI_CFG_ESS_NOT_OESS BIT(3) | |
98 | #define HDMI_CFG_H_SYNC_POL_NEG BIT(4) | |
99 | #define HDMI_CFG_SINK_TERM_DET_EN BIT(5) | |
100 | #define HDMI_CFG_V_SYNC_POL_NEG BIT(6) | |
101 | #define HDMI_CFG_422_EN BIT(8) | |
102 | #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12) | |
103 | #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13) | |
104 | #define HDMI_CFG_SW_RST_EN BIT(31) | |
105 | ||
106 | #define HDMI_INT_GLOBAL BIT(0) | |
107 | #define HDMI_INT_SW_RST BIT(1) | |
108 | #define HDMI_INT_PIX_CAP BIT(3) | |
109 | #define HDMI_INT_HOT_PLUG BIT(4) | |
110 | #define HDMI_INT_DLL_LCK BIT(5) | |
111 | #define HDMI_INT_NEW_FRAME BIT(6) | |
112 | #define HDMI_INT_GENCTRL_PKT BIT(7) | |
2c348e50 | 113 | #define HDMI_INT_AUDIO_FIFO_XRUN BIT(8) |
5402626c BG |
114 | #define HDMI_INT_SINK_TERM_PRESENT BIT(11) |
115 | ||
116 | #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \ | |
117 | | HDMI_INT_DLL_LCK \ | |
118 | | HDMI_INT_HOT_PLUG \ | |
119 | | HDMI_INT_GLOBAL) | |
120 | ||
121 | #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \ | |
2c348e50 | 122 | | HDMI_INT_AUDIO_FIFO_XRUN \ |
5402626c BG |
123 | | HDMI_INT_GENCTRL_PKT \ |
124 | | HDMI_INT_NEW_FRAME \ | |
125 | | HDMI_INT_DLL_LCK \ | |
126 | | HDMI_INT_HOT_PLUG \ | |
127 | | HDMI_INT_PIX_CAP \ | |
128 | | HDMI_INT_SW_RST \ | |
129 | | HDMI_INT_GLOBAL) | |
130 | ||
131 | #define HDMI_STA_SW_RST BIT(1) | |
132 | ||
2c348e50 AP |
133 | #define HDMI_AUD_CFG_8CH BIT(0) |
134 | #define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1) | |
135 | #define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2) | |
136 | #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2)) | |
137 | #define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12) | |
138 | #define HDMI_AUD_CFG_DTS_INVALID BIT(16) | |
139 | #define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21)) | |
140 | #define HDMI_AUD_CFG_CH12_VALID BIT(28) | |
141 | #define HDMI_AUD_CFG_CH34_VALID BIT(29) | |
142 | #define HDMI_AUD_CFG_CH56_VALID BIT(30) | |
143 | #define HDMI_AUD_CFG_CH78_VALID BIT(31) | |
144 | ||
145 | /* sample flat mask */ | |
146 | #define HDMI_SAMPLE_FLAT_NO 0 | |
147 | #define HDMI_SAMPLE_FLAT_SP0 BIT(0) | |
148 | #define HDMI_SAMPLE_FLAT_SP1 BIT(1) | |
149 | #define HDMI_SAMPLE_FLAT_SP2 BIT(2) | |
150 | #define HDMI_SAMPLE_FLAT_SP3 BIT(3) | |
151 | #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\ | |
152 | HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3) | |
153 | ||
cffe1e89 AP |
154 | #define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) |
155 | #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) | |
156 | #define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) | |
157 | ||
5402626c BG |
158 | struct sti_hdmi_connector { |
159 | struct drm_connector drm_connector; | |
160 | struct drm_encoder *encoder; | |
161 | struct sti_hdmi *hdmi; | |
5671cefb | 162 | struct drm_property *colorspace_property; |
ffc4a6a1 | 163 | struct drm_property *hdmi_mode_property; |
5402626c BG |
164 | }; |
165 | ||
166 | #define to_sti_hdmi_connector(x) \ | |
167 | container_of(x, struct sti_hdmi_connector, drm_connector) | |
168 | ||
169 | u32 hdmi_read(struct sti_hdmi *hdmi, int offset) | |
170 | { | |
171 | return readl(hdmi->regs + offset); | |
172 | } | |
173 | ||
174 | void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset) | |
175 | { | |
176 | writel(val, hdmi->regs + offset); | |
177 | } | |
178 | ||
179 | /** | |
180 | * HDMI interrupt handler threaded | |
181 | * | |
182 | * @irq: irq number | |
183 | * @arg: connector structure | |
184 | */ | |
185 | static irqreturn_t hdmi_irq_thread(int irq, void *arg) | |
186 | { | |
187 | struct sti_hdmi *hdmi = arg; | |
188 | ||
189 | /* Hot plug/unplug IRQ */ | |
190 | if (hdmi->irq_status & HDMI_INT_HOT_PLUG) { | |
76569207 | 191 | hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; |
5402626c BG |
192 | if (hdmi->drm_dev) |
193 | drm_helper_hpd_irq_event(hdmi->drm_dev); | |
194 | } | |
195 | ||
196 | /* Sw reset and PLL lock are exclusive so we can use the same | |
197 | * event to signal them | |
198 | */ | |
199 | if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) { | |
200 | hdmi->event_received = true; | |
201 | wake_up_interruptible(&hdmi->wait_event); | |
202 | } | |
203 | ||
2c348e50 AP |
204 | /* Audio FIFO underrun IRQ */ |
205 | if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN) | |
206 | DRM_INFO("Warning: audio FIFO underrun occurs!"); | |
207 | ||
5402626c BG |
208 | return IRQ_HANDLED; |
209 | } | |
210 | ||
211 | /** | |
212 | * HDMI interrupt handler | |
213 | * | |
214 | * @irq: irq number | |
215 | * @arg: connector structure | |
216 | */ | |
217 | static irqreturn_t hdmi_irq(int irq, void *arg) | |
218 | { | |
219 | struct sti_hdmi *hdmi = arg; | |
220 | ||
221 | /* read interrupt status */ | |
222 | hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA); | |
223 | ||
224 | /* clear interrupt status */ | |
225 | hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR); | |
226 | ||
227 | /* force sync bus write */ | |
228 | hdmi_read(hdmi, HDMI_INT_STA); | |
229 | ||
230 | return IRQ_WAKE_THREAD; | |
231 | } | |
232 | ||
233 | /** | |
234 | * Set hdmi active area depending on the drm display mode selected | |
235 | * | |
236 | * @hdmi: pointer on the hdmi internal structure | |
237 | */ | |
238 | static void hdmi_active_area(struct sti_hdmi *hdmi) | |
239 | { | |
240 | u32 xmin, xmax; | |
241 | u32 ymin, ymax; | |
242 | ||
8661532a VA |
243 | xmin = sti_vtg_get_pixel_number(hdmi->mode, 1); |
244 | xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay); | |
5402626c BG |
245 | ymin = sti_vtg_get_line_number(hdmi->mode, 0); |
246 | ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1); | |
247 | ||
248 | hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN); | |
249 | hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX); | |
250 | hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN); | |
251 | hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX); | |
252 | } | |
253 | ||
254 | /** | |
255 | * Overall hdmi configuration | |
256 | * | |
257 | * @hdmi: pointer on the hdmi internal structure | |
258 | */ | |
259 | static void hdmi_config(struct sti_hdmi *hdmi) | |
260 | { | |
261 | u32 conf; | |
262 | ||
263 | DRM_DEBUG_DRIVER("\n"); | |
264 | ||
265 | /* Clear overrun and underrun fifo */ | |
266 | conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR; | |
267 | ||
ffc4a6a1 VA |
268 | /* Select encryption type and the framing mode */ |
269 | conf |= HDMI_CFG_ESS_NOT_OESS; | |
270 | if (hdmi->hdmi_mode == HDMI_MODE_HDMI) | |
271 | conf |= HDMI_CFG_HDMI_NOT_DVI; | |
5402626c BG |
272 | |
273 | /* Enable sink term detection */ | |
274 | conf |= HDMI_CFG_SINK_TERM_DET_EN; | |
275 | ||
276 | /* Set Hsync polarity */ | |
277 | if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) { | |
278 | DRM_DEBUG_DRIVER("H Sync Negative\n"); | |
279 | conf |= HDMI_CFG_H_SYNC_POL_NEG; | |
280 | } | |
281 | ||
282 | /* Set Vsync polarity */ | |
283 | if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) { | |
284 | DRM_DEBUG_DRIVER("V Sync Negative\n"); | |
285 | conf |= HDMI_CFG_V_SYNC_POL_NEG; | |
286 | } | |
287 | ||
288 | /* Enable HDMI */ | |
289 | conf |= HDMI_CFG_DEVICE_EN; | |
290 | ||
291 | hdmi_write(hdmi, conf, HDMI_CFG); | |
292 | } | |
293 | ||
181975a2 VA |
294 | /* |
295 | * Helper to reset info frame | |
296 | * | |
297 | * @hdmi: pointer on the hdmi internal structure | |
298 | * @slot: infoframe to reset | |
299 | */ | |
300 | static void hdmi_infoframe_reset(struct sti_hdmi *hdmi, | |
301 | u32 slot) | |
302 | { | |
303 | u32 val, i; | |
304 | u32 head_offset, pack_offset; | |
305 | ||
306 | switch (slot) { | |
307 | case HDMI_IFRAME_SLOT_AVI: | |
308 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); | |
309 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); | |
310 | break; | |
311 | case HDMI_IFRAME_SLOT_AUDIO: | |
312 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); | |
313 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); | |
314 | break; | |
e42e7bd7 VA |
315 | case HDMI_IFRAME_SLOT_VENDOR: |
316 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); | |
317 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); | |
318 | break; | |
181975a2 VA |
319 | default: |
320 | DRM_ERROR("unsupported infoframe slot: %#x\n", slot); | |
321 | return; | |
322 | } | |
323 | ||
324 | /* Disable transmission for the selected slot */ | |
325 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
326 | val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); | |
327 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); | |
328 | ||
329 | /* Reset info frame registers */ | |
330 | hdmi_write(hdmi, 0x0, head_offset); | |
331 | for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32)) | |
332 | hdmi_write(hdmi, 0x0, pack_offset + i); | |
333 | } | |
334 | ||
cffe1e89 AP |
335 | /** |
336 | * Helper to concatenate infoframe in 32 bits word | |
337 | * | |
338 | * @ptr: pointer on the hdmi internal structure | |
339 | * @data: infoframe to write | |
340 | * @size: size to write | |
341 | */ | |
342 | static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size) | |
343 | { | |
344 | unsigned long value = 0; | |
345 | size_t i; | |
346 | ||
347 | for (i = size; i > 0; i--) | |
348 | value = (value << 8) | ptr[i - 1]; | |
349 | ||
350 | return value; | |
351 | } | |
352 | ||
353 | /** | |
354 | * Helper to write info frame | |
355 | * | |
356 | * @hdmi: pointer on the hdmi internal structure | |
357 | * @data: infoframe to write | |
358 | * @size: size to write | |
359 | */ | |
e42e7bd7 VA |
360 | static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi, |
361 | const u8 *data, | |
362 | size_t size) | |
cffe1e89 AP |
363 | { |
364 | const u8 *ptr = data; | |
365 | u32 val, slot, mode, i; | |
366 | u32 head_offset, pack_offset; | |
cffe1e89 AP |
367 | |
368 | switch (*ptr) { | |
369 | case HDMI_INFOFRAME_TYPE_AVI: | |
370 | slot = HDMI_IFRAME_SLOT_AVI; | |
371 | mode = HDMI_IFRAME_FIELD; | |
372 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); | |
373 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); | |
cffe1e89 | 374 | break; |
cffe1e89 AP |
375 | case HDMI_INFOFRAME_TYPE_AUDIO: |
376 | slot = HDMI_IFRAME_SLOT_AUDIO; | |
377 | mode = HDMI_IFRAME_FRAME; | |
378 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); | |
379 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); | |
cffe1e89 | 380 | break; |
e42e7bd7 VA |
381 | case HDMI_INFOFRAME_TYPE_VENDOR: |
382 | slot = HDMI_IFRAME_SLOT_VENDOR; | |
383 | mode = HDMI_IFRAME_FRAME; | |
384 | head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); | |
385 | pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); | |
386 | break; | |
cffe1e89 AP |
387 | default: |
388 | DRM_ERROR("unsupported infoframe type: %#x\n", *ptr); | |
389 | return; | |
390 | } | |
391 | ||
392 | /* Disable transmission slot for updated infoframe */ | |
393 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
394 | val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); | |
395 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); | |
396 | ||
397 | val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++); | |
398 | val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++); | |
399 | val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++); | |
400 | writel(val, hdmi->regs + head_offset); | |
401 | ||
402 | /* | |
403 | * Each subpack contains 4 bytes | |
404 | * The First Bytes of the first subpacket must contain the checksum | |
e42e7bd7 | 405 | * Packet size is increase by one. |
cffe1e89 | 406 | */ |
e42e7bd7 | 407 | size = size - HDMI_INFOFRAME_HEADER_SIZE + 1; |
cffe1e89 AP |
408 | for (i = 0; i < size; i += sizeof(u32)) { |
409 | size_t num; | |
410 | ||
411 | num = min_t(size_t, size - i, sizeof(u32)); | |
412 | val = hdmi_infoframe_subpack(ptr, num); | |
413 | ptr += sizeof(u32); | |
414 | writel(val, hdmi->regs + pack_offset + i); | |
415 | } | |
416 | ||
417 | /* Enable transmission slot for updated infoframe */ | |
418 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
50f2138a | 419 | val |= HDMI_IFRAME_CFG_DI_N(mode, slot); |
cffe1e89 AP |
420 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); |
421 | } | |
422 | ||
5402626c BG |
423 | /** |
424 | * Prepare and configure the AVI infoframe | |
425 | * | |
426 | * AVI infoframe are transmitted at least once per two video field and | |
427 | * contains information about HDMI transmission mode such as color space, | |
428 | * colorimetry, ... | |
429 | * | |
430 | * @hdmi: pointer on the hdmi internal structure | |
431 | * | |
432 | * Return negative value if error occurs | |
433 | */ | |
434 | static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi) | |
435 | { | |
436 | struct drm_display_mode *mode = &hdmi->mode; | |
437 | struct hdmi_avi_infoframe infoframe; | |
438 | u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; | |
5402626c BG |
439 | int ret; |
440 | ||
441 | DRM_DEBUG_DRIVER("\n"); | |
442 | ||
443 | ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode); | |
444 | if (ret < 0) { | |
445 | DRM_ERROR("failed to setup AVI infoframe: %d\n", ret); | |
446 | return ret; | |
447 | } | |
448 | ||
449 | /* fixed infoframe configuration not linked to the mode */ | |
5671cefb | 450 | infoframe.colorspace = hdmi->colorspace; |
5402626c BG |
451 | infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; |
452 | infoframe.colorimetry = HDMI_COLORIMETRY_NONE; | |
453 | ||
454 | ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer)); | |
455 | if (ret < 0) { | |
456 | DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); | |
457 | return ret; | |
458 | } | |
459 | ||
e42e7bd7 | 460 | hdmi_infoframe_write_infopack(hdmi, buffer, ret); |
5402626c | 461 | |
cffe1e89 AP |
462 | return 0; |
463 | } | |
464 | ||
465 | /** | |
466 | * Prepare and configure the AUDIO infoframe | |
467 | * | |
468 | * AUDIO infoframe are transmitted once per frame and | |
469 | * contains information about HDMI transmission mode such as audio codec, | |
470 | * sample size, ... | |
471 | * | |
472 | * @hdmi: pointer on the hdmi internal structure | |
473 | * | |
474 | * Return negative value if error occurs | |
475 | */ | |
476 | static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi) | |
477 | { | |
2c348e50 | 478 | struct hdmi_audio_params *audio = &hdmi->audio; |
cffe1e89 | 479 | u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; |
2c348e50 AP |
480 | int ret, val; |
481 | ||
482 | DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__, | |
483 | audio->enabled ? "enable" : "disable"); | |
484 | if (audio->enabled) { | |
485 | /* set audio parameters stored*/ | |
486 | ret = hdmi_audio_infoframe_pack(&audio->cea, buffer, | |
487 | sizeof(buffer)); | |
488 | if (ret < 0) { | |
489 | DRM_ERROR("failed to pack audio infoframe: %d\n", ret); | |
490 | return ret; | |
491 | } | |
492 | hdmi_infoframe_write_infopack(hdmi, buffer, ret); | |
493 | } else { | |
494 | /*disable audio info frame transmission */ | |
495 | val = hdmi_read(hdmi, HDMI_SW_DI_CFG); | |
496 | val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, | |
497 | HDMI_IFRAME_SLOT_AUDIO); | |
498 | hdmi_write(hdmi, val, HDMI_SW_DI_CFG); | |
cffe1e89 AP |
499 | } |
500 | ||
e42e7bd7 VA |
501 | return 0; |
502 | } | |
503 | ||
504 | /* | |
505 | * Prepare and configure the VS infoframe | |
506 | * | |
507 | * Vendor Specific infoframe are transmitted once per frame and | |
508 | * contains vendor specific information. | |
509 | * | |
510 | * @hdmi: pointer on the hdmi internal structure | |
511 | * | |
512 | * Return negative value if error occurs | |
513 | */ | |
514 | #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6 | |
515 | static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi) | |
516 | { | |
517 | struct drm_display_mode *mode = &hdmi->mode; | |
518 | struct hdmi_vendor_infoframe infoframe; | |
519 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE]; | |
520 | int ret; | |
521 | ||
522 | DRM_DEBUG_DRIVER("\n"); | |
523 | ||
524 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe, mode); | |
525 | if (ret < 0) { | |
526 | /* | |
527 | * Going into that statement does not means vendor infoframe | |
528 | * fails. It just informed us that vendor infoframe is not | |
529 | * needed for the selected mode. Only 4k or stereoscopic 3D | |
530 | * mode requires vendor infoframe. So just simply return 0. | |
531 | */ | |
532 | return 0; | |
533 | } | |
534 | ||
535 | ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer)); | |
536 | if (ret < 0) { | |
537 | DRM_ERROR("failed to pack VS infoframe: %d\n", ret); | |
538 | return ret; | |
539 | } | |
540 | ||
541 | hdmi_infoframe_write_infopack(hdmi, buffer, ret); | |
5402626c BG |
542 | |
543 | return 0; | |
544 | } | |
545 | ||
546 | /** | |
547 | * Software reset of the hdmi subsystem | |
548 | * | |
549 | * @hdmi: pointer on the hdmi internal structure | |
550 | * | |
551 | */ | |
552 | #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */ | |
553 | static void hdmi_swreset(struct sti_hdmi *hdmi) | |
554 | { | |
555 | u32 val; | |
556 | ||
557 | DRM_DEBUG_DRIVER("\n"); | |
558 | ||
559 | /* Enable hdmi_audio clock only during hdmi reset */ | |
560 | if (clk_prepare_enable(hdmi->clk_audio)) | |
561 | DRM_INFO("Failed to prepare/enable hdmi_audio clk\n"); | |
562 | ||
563 | /* Sw reset */ | |
564 | hdmi->event_received = false; | |
565 | ||
566 | val = hdmi_read(hdmi, HDMI_CFG); | |
567 | val |= HDMI_CFG_SW_RST_EN; | |
568 | hdmi_write(hdmi, val, HDMI_CFG); | |
569 | ||
570 | /* Wait reset completed */ | |
571 | wait_event_interruptible_timeout(hdmi->wait_event, | |
572 | hdmi->event_received == true, | |
573 | msecs_to_jiffies | |
574 | (HDMI_TIMEOUT_SWRESET)); | |
575 | ||
576 | /* | |
577 | * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is | |
578 | * set to '1' and clk_audio is running. | |
579 | */ | |
580 | if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0) | |
581 | DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n"); | |
582 | ||
583 | val = hdmi_read(hdmi, HDMI_CFG); | |
584 | val &= ~HDMI_CFG_SW_RST_EN; | |
585 | hdmi_write(hdmi, val, HDMI_CFG); | |
586 | ||
587 | /* Disable hdmi_audio clock. Not used anymore for drm purpose */ | |
588 | clk_disable_unprepare(hdmi->clk_audio); | |
589 | } | |
590 | ||
7ea6e6e4 VA |
591 | #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2) |
592 | #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2) | |
593 | #define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \ | |
594 | hdmi_read(hdmi, reg)) | |
595 | #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot)) | |
596 | ||
597 | static void hdmi_dbg_cfg(struct seq_file *s, int val) | |
598 | { | |
599 | int tmp; | |
600 | ||
601 | seq_puts(s, "\t"); | |
602 | tmp = val & HDMI_CFG_HDMI_NOT_DVI; | |
603 | DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI"); | |
604 | seq_puts(s, "\t\t\t\t\t"); | |
605 | tmp = val & HDMI_CFG_HDCP_EN; | |
606 | DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable"); | |
607 | seq_puts(s, "\t\t\t\t\t"); | |
608 | tmp = val & HDMI_CFG_ESS_NOT_OESS; | |
609 | DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable"); | |
610 | seq_puts(s, "\t\t\t\t\t"); | |
611 | tmp = val & HDMI_CFG_SINK_TERM_DET_EN; | |
612 | DBGFS_PRINT_STR("Sink term detection:", tmp ? "enable" : "disable"); | |
613 | seq_puts(s, "\t\t\t\t\t"); | |
614 | tmp = val & HDMI_CFG_H_SYNC_POL_NEG; | |
615 | DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal"); | |
616 | seq_puts(s, "\t\t\t\t\t"); | |
617 | tmp = val & HDMI_CFG_V_SYNC_POL_NEG; | |
618 | DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal"); | |
619 | seq_puts(s, "\t\t\t\t\t"); | |
620 | tmp = val & HDMI_CFG_422_EN; | |
621 | DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable"); | |
622 | } | |
623 | ||
624 | static void hdmi_dbg_sta(struct seq_file *s, int val) | |
625 | { | |
626 | int tmp; | |
627 | ||
628 | seq_puts(s, "\t"); | |
629 | tmp = (val & HDMI_STA_DLL_LCK); | |
630 | DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked"); | |
631 | seq_puts(s, "\t\t\t\t\t"); | |
632 | tmp = (val & HDMI_STA_HOT_PLUG); | |
633 | DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected"); | |
634 | } | |
635 | ||
636 | static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val) | |
637 | { | |
638 | int tmp; | |
639 | char *const en_di[] = {"no transmission", | |
640 | "single transmission", | |
641 | "once every field", | |
642 | "once every frame"}; | |
643 | ||
644 | seq_puts(s, "\t"); | |
645 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1)); | |
646 | DBGFS_PRINT_STR("Data island 1:", en_di[tmp]); | |
647 | seq_puts(s, "\t\t\t\t\t"); | |
648 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4; | |
649 | DBGFS_PRINT_STR("Data island 2:", en_di[tmp]); | |
650 | seq_puts(s, "\t\t\t\t\t"); | |
651 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8; | |
652 | DBGFS_PRINT_STR("Data island 3:", en_di[tmp]); | |
653 | seq_puts(s, "\t\t\t\t\t"); | |
654 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12; | |
655 | DBGFS_PRINT_STR("Data island 4:", en_di[tmp]); | |
656 | seq_puts(s, "\t\t\t\t\t"); | |
657 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16; | |
658 | DBGFS_PRINT_STR("Data island 5:", en_di[tmp]); | |
659 | seq_puts(s, "\t\t\t\t\t"); | |
660 | tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20; | |
661 | DBGFS_PRINT_STR("Data island 6:", en_di[tmp]); | |
662 | } | |
663 | ||
664 | static int hdmi_dbg_show(struct seq_file *s, void *data) | |
665 | { | |
666 | struct drm_info_node *node = s->private; | |
667 | struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data; | |
7ea6e6e4 VA |
668 | |
669 | seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs); | |
670 | DBGFS_DUMP("\n", HDMI_CFG); | |
671 | hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG)); | |
672 | DBGFS_DUMP("", HDMI_INT_EN); | |
673 | DBGFS_DUMP("\n", HDMI_STA); | |
674 | hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA)); | |
675 | DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN); | |
676 | seq_puts(s, "\t"); | |
677 | DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN)); | |
678 | DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX); | |
679 | seq_puts(s, "\t"); | |
680 | DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX)); | |
681 | DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN); | |
682 | seq_puts(s, "\t"); | |
683 | DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN)); | |
684 | DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX); | |
685 | seq_puts(s, "\t"); | |
686 | DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX)); | |
687 | DBGFS_DUMP("", HDMI_SW_DI_CFG); | |
688 | hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG)); | |
689 | ||
2c348e50 AP |
690 | DBGFS_DUMP("\n", HDMI_AUDIO_CFG); |
691 | DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS); | |
692 | DBGFS_DUMP("\n", HDMI_AUDN); | |
693 | ||
7ea6e6e4 VA |
694 | seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):", |
695 | HDMI_IFRAME_SLOT_AVI); | |
696 | DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI); | |
697 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI); | |
698 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI); | |
699 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI); | |
700 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI); | |
701 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI); | |
702 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI); | |
703 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI); | |
704 | seq_puts(s, "\n"); | |
705 | seq_printf(s, "\n AUDIO Infoframe (Data Island slot N=%d):", | |
706 | HDMI_IFRAME_SLOT_AUDIO); | |
707 | DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO); | |
708 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO); | |
709 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO); | |
710 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO); | |
711 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO); | |
712 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO); | |
713 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO); | |
714 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO); | |
715 | seq_puts(s, "\n"); | |
716 | seq_printf(s, "\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):", | |
717 | HDMI_IFRAME_SLOT_VENDOR); | |
718 | DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR); | |
719 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR); | |
720 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR); | |
721 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR); | |
722 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR); | |
723 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR); | |
724 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR); | |
725 | DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR); | |
726 | seq_puts(s, "\n"); | |
727 | ||
7ea6e6e4 VA |
728 | return 0; |
729 | } | |
730 | ||
731 | static struct drm_info_list hdmi_debugfs_files[] = { | |
732 | { "hdmi", hdmi_dbg_show, 0, NULL }, | |
733 | }; | |
734 | ||
735 | static void hdmi_debugfs_exit(struct sti_hdmi *hdmi, struct drm_minor *minor) | |
736 | { | |
737 | drm_debugfs_remove_files(hdmi_debugfs_files, | |
738 | ARRAY_SIZE(hdmi_debugfs_files), | |
739 | minor); | |
740 | } | |
741 | ||
742 | static int hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor) | |
743 | { | |
744 | unsigned int i; | |
745 | ||
746 | for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++) | |
747 | hdmi_debugfs_files[i].data = hdmi; | |
748 | ||
749 | return drm_debugfs_create_files(hdmi_debugfs_files, | |
750 | ARRAY_SIZE(hdmi_debugfs_files), | |
751 | minor->debugfs_root, minor); | |
752 | } | |
753 | ||
5402626c BG |
754 | static void sti_hdmi_disable(struct drm_bridge *bridge) |
755 | { | |
756 | struct sti_hdmi *hdmi = bridge->driver_private; | |
757 | ||
758 | u32 val = hdmi_read(hdmi, HDMI_CFG); | |
759 | ||
760 | if (!hdmi->enabled) | |
761 | return; | |
762 | ||
763 | DRM_DEBUG_DRIVER("\n"); | |
764 | ||
765 | /* Disable HDMI */ | |
766 | val &= ~HDMI_CFG_DEVICE_EN; | |
767 | hdmi_write(hdmi, val, HDMI_CFG); | |
768 | ||
769 | hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR); | |
770 | ||
771 | /* Stop the phy */ | |
772 | hdmi->phy_ops->stop(hdmi); | |
773 | ||
181975a2 VA |
774 | /* Reset info frame transmission */ |
775 | hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI); | |
776 | hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO); | |
e42e7bd7 | 777 | hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR); |
181975a2 | 778 | |
5402626c BG |
779 | /* Set the default channel data to be a dark red */ |
780 | hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT); | |
781 | hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT); | |
782 | hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT); | |
783 | ||
784 | /* Disable/unprepare hdmi clock */ | |
785 | clk_disable_unprepare(hdmi->clk_phy); | |
786 | clk_disable_unprepare(hdmi->clk_tmds); | |
787 | clk_disable_unprepare(hdmi->clk_pix); | |
788 | ||
789 | hdmi->enabled = false; | |
790 | } | |
791 | ||
792 | static void sti_hdmi_pre_enable(struct drm_bridge *bridge) | |
793 | { | |
794 | struct sti_hdmi *hdmi = bridge->driver_private; | |
795 | ||
796 | DRM_DEBUG_DRIVER("\n"); | |
797 | ||
798 | if (hdmi->enabled) | |
799 | return; | |
800 | ||
801 | /* Prepare/enable clocks */ | |
802 | if (clk_prepare_enable(hdmi->clk_pix)) | |
803 | DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n"); | |
804 | if (clk_prepare_enable(hdmi->clk_tmds)) | |
805 | DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n"); | |
806 | if (clk_prepare_enable(hdmi->clk_phy)) | |
807 | DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n"); | |
808 | ||
809 | hdmi->enabled = true; | |
810 | ||
811 | /* Program hdmi serializer and start phy */ | |
812 | if (!hdmi->phy_ops->start(hdmi)) { | |
813 | DRM_ERROR("Unable to start hdmi phy\n"); | |
814 | return; | |
815 | } | |
816 | ||
817 | /* Program hdmi active area */ | |
818 | hdmi_active_area(hdmi); | |
819 | ||
820 | /* Enable working interrupts */ | |
821 | hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN); | |
822 | ||
823 | /* Program hdmi config */ | |
824 | hdmi_config(hdmi); | |
825 | ||
826 | /* Program AVI infoframe */ | |
827 | if (hdmi_avi_infoframe_config(hdmi)) | |
828 | DRM_ERROR("Unable to configure AVI infoframe\n"); | |
829 | ||
cffe1e89 AP |
830 | /* Program AUDIO infoframe */ |
831 | if (hdmi_audio_infoframe_config(hdmi)) | |
832 | DRM_ERROR("Unable to configure AUDIO infoframe\n"); | |
833 | ||
e42e7bd7 VA |
834 | /* Program VS infoframe */ |
835 | if (hdmi_vendor_infoframe_config(hdmi)) | |
836 | DRM_ERROR("Unable to configure VS infoframe\n"); | |
837 | ||
5402626c BG |
838 | /* Sw reset */ |
839 | hdmi_swreset(hdmi); | |
840 | } | |
841 | ||
842 | static void sti_hdmi_set_mode(struct drm_bridge *bridge, | |
843 | struct drm_display_mode *mode, | |
844 | struct drm_display_mode *adjusted_mode) | |
845 | { | |
846 | struct sti_hdmi *hdmi = bridge->driver_private; | |
847 | int ret; | |
848 | ||
849 | DRM_DEBUG_DRIVER("\n"); | |
850 | ||
851 | /* Copy the drm display mode in the connector local structure */ | |
852 | memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode)); | |
853 | ||
854 | /* Update clock framerate according to the selected mode */ | |
855 | ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000); | |
856 | if (ret < 0) { | |
857 | DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n", | |
858 | mode->clock * 1000); | |
859 | return; | |
860 | } | |
861 | ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000); | |
862 | if (ret < 0) { | |
863 | DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n", | |
864 | mode->clock * 1000); | |
865 | return; | |
866 | } | |
867 | } | |
868 | ||
869 | static void sti_hdmi_bridge_nope(struct drm_bridge *bridge) | |
870 | { | |
871 | /* do nothing */ | |
872 | } | |
873 | ||
5402626c BG |
874 | static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = { |
875 | .pre_enable = sti_hdmi_pre_enable, | |
876 | .enable = sti_hdmi_bridge_nope, | |
877 | .disable = sti_hdmi_disable, | |
878 | .post_disable = sti_hdmi_bridge_nope, | |
879 | .mode_set = sti_hdmi_set_mode, | |
5402626c BG |
880 | }; |
881 | ||
882 | static int sti_hdmi_connector_get_modes(struct drm_connector *connector) | |
883 | { | |
41a14623 BG |
884 | struct sti_hdmi_connector *hdmi_connector |
885 | = to_sti_hdmi_connector(connector); | |
886 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
5402626c BG |
887 | struct edid *edid; |
888 | int count; | |
889 | ||
890 | DRM_DEBUG_DRIVER("\n"); | |
891 | ||
41a14623 | 892 | edid = drm_get_edid(connector, hdmi->ddc_adapt); |
5402626c BG |
893 | if (!edid) |
894 | goto fail; | |
895 | ||
896 | count = drm_add_edid_modes(connector, edid); | |
897 | drm_mode_connector_update_edid_property(connector, edid); | |
2c348e50 | 898 | drm_edid_to_eld(connector, edid); |
5402626c BG |
899 | |
900 | kfree(edid); | |
901 | return count; | |
902 | ||
903 | fail: | |
871bcdfe | 904 | DRM_ERROR("Can't read HDMI EDID\n"); |
5402626c BG |
905 | return 0; |
906 | } | |
907 | ||
908 | #define CLK_TOLERANCE_HZ 50 | |
909 | ||
910 | static int sti_hdmi_connector_mode_valid(struct drm_connector *connector, | |
911 | struct drm_display_mode *mode) | |
912 | { | |
913 | int target = mode->clock * 1000; | |
914 | int target_min = target - CLK_TOLERANCE_HZ; | |
915 | int target_max = target + CLK_TOLERANCE_HZ; | |
916 | int result; | |
917 | struct sti_hdmi_connector *hdmi_connector | |
918 | = to_sti_hdmi_connector(connector); | |
919 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
920 | ||
921 | ||
922 | result = clk_round_rate(hdmi->clk_pix, target); | |
923 | ||
924 | DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", | |
925 | target, result); | |
926 | ||
927 | if ((result < target_min) || (result > target_max)) { | |
928 | DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target); | |
929 | return MODE_BAD; | |
930 | } | |
931 | ||
932 | return MODE_OK; | |
933 | } | |
934 | ||
c5de4853 VS |
935 | static const |
936 | struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = { | |
5402626c BG |
937 | .get_modes = sti_hdmi_connector_get_modes, |
938 | .mode_valid = sti_hdmi_connector_mode_valid, | |
5402626c BG |
939 | }; |
940 | ||
941 | /* get detection status of display device */ | |
942 | static enum drm_connector_status | |
943 | sti_hdmi_connector_detect(struct drm_connector *connector, bool force) | |
944 | { | |
945 | struct sti_hdmi_connector *hdmi_connector | |
946 | = to_sti_hdmi_connector(connector); | |
947 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
948 | ||
949 | DRM_DEBUG_DRIVER("\n"); | |
950 | ||
951 | if (hdmi->hpd) { | |
952 | DRM_DEBUG_DRIVER("hdmi cable connected\n"); | |
953 | return connector_status_connected; | |
954 | } | |
955 | ||
956 | DRM_DEBUG_DRIVER("hdmi cable disconnected\n"); | |
957 | return connector_status_disconnected; | |
958 | } | |
959 | ||
5671cefb VA |
960 | static void sti_hdmi_connector_init_property(struct drm_device *drm_dev, |
961 | struct drm_connector *connector) | |
962 | { | |
963 | struct sti_hdmi_connector *hdmi_connector | |
964 | = to_sti_hdmi_connector(connector); | |
965 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
966 | struct drm_property *prop; | |
967 | ||
968 | /* colorspace property */ | |
969 | hdmi->colorspace = DEFAULT_COLORSPACE_MODE; | |
970 | prop = drm_property_create_enum(drm_dev, 0, "colorspace", | |
971 | colorspace_mode_names, | |
972 | ARRAY_SIZE(colorspace_mode_names)); | |
973 | if (!prop) { | |
974 | DRM_ERROR("fails to create colorspace property\n"); | |
975 | return; | |
976 | } | |
977 | hdmi_connector->colorspace_property = prop; | |
978 | drm_object_attach_property(&connector->base, prop, hdmi->colorspace); | |
ffc4a6a1 VA |
979 | |
980 | /* hdmi_mode property */ | |
981 | hdmi->hdmi_mode = DEFAULT_HDMI_MODE; | |
982 | prop = drm_property_create_enum(drm_dev, 0, "hdmi_mode", | |
983 | hdmi_mode_names, | |
984 | ARRAY_SIZE(hdmi_mode_names)); | |
985 | if (!prop) { | |
986 | DRM_ERROR("fails to create colorspace property\n"); | |
987 | return; | |
988 | } | |
989 | hdmi_connector->hdmi_mode_property = prop; | |
990 | drm_object_attach_property(&connector->base, prop, hdmi->hdmi_mode); | |
991 | ||
5671cefb VA |
992 | } |
993 | ||
994 | static int | |
995 | sti_hdmi_connector_set_property(struct drm_connector *connector, | |
996 | struct drm_connector_state *state, | |
997 | struct drm_property *property, | |
998 | uint64_t val) | |
999 | { | |
1000 | struct sti_hdmi_connector *hdmi_connector | |
1001 | = to_sti_hdmi_connector(connector); | |
1002 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
1003 | ||
1004 | if (property == hdmi_connector->colorspace_property) { | |
1005 | hdmi->colorspace = val; | |
1006 | return 0; | |
1007 | } | |
1008 | ||
ffc4a6a1 VA |
1009 | if (property == hdmi_connector->hdmi_mode_property) { |
1010 | hdmi->hdmi_mode = val; | |
1011 | return 0; | |
1012 | } | |
1013 | ||
5671cefb VA |
1014 | DRM_ERROR("failed to set hdmi connector property\n"); |
1015 | return -EINVAL; | |
1016 | } | |
1017 | ||
1018 | static int | |
1019 | sti_hdmi_connector_get_property(struct drm_connector *connector, | |
1020 | const struct drm_connector_state *state, | |
1021 | struct drm_property *property, | |
1022 | uint64_t *val) | |
1023 | { | |
1024 | struct sti_hdmi_connector *hdmi_connector | |
1025 | = to_sti_hdmi_connector(connector); | |
1026 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
1027 | ||
1028 | if (property == hdmi_connector->colorspace_property) { | |
1029 | *val = hdmi->colorspace; | |
1030 | return 0; | |
1031 | } | |
1032 | ||
ffc4a6a1 VA |
1033 | if (property == hdmi_connector->hdmi_mode_property) { |
1034 | *val = hdmi->hdmi_mode; | |
1035 | return 0; | |
1036 | } | |
1037 | ||
5671cefb VA |
1038 | DRM_ERROR("failed to get hdmi connector property\n"); |
1039 | return -EINVAL; | |
1040 | } | |
1041 | ||
83af0a48 BG |
1042 | static int sti_hdmi_late_register(struct drm_connector *connector) |
1043 | { | |
1044 | struct sti_hdmi_connector *hdmi_connector | |
1045 | = to_sti_hdmi_connector(connector); | |
1046 | struct sti_hdmi *hdmi = hdmi_connector->hdmi; | |
1047 | ||
1048 | if (hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary)) { | |
1049 | DRM_ERROR("HDMI debugfs setup failed\n"); | |
1050 | return -EINVAL; | |
1051 | } | |
1052 | ||
1053 | return 0; | |
1054 | } | |
1055 | ||
c5de4853 | 1056 | static const struct drm_connector_funcs sti_hdmi_connector_funcs = { |
5402626c BG |
1057 | .fill_modes = drm_helper_probe_single_connector_modes, |
1058 | .detect = sti_hdmi_connector_detect, | |
84601dbd | 1059 | .destroy = drm_connector_cleanup, |
de4b00b0 | 1060 | .reset = drm_atomic_helper_connector_reset, |
5671cefb VA |
1061 | .set_property = drm_atomic_helper_connector_set_property, |
1062 | .atomic_set_property = sti_hdmi_connector_set_property, | |
1063 | .atomic_get_property = sti_hdmi_connector_get_property, | |
de4b00b0 BG |
1064 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
1065 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
83af0a48 | 1066 | .late_register = sti_hdmi_late_register, |
5402626c BG |
1067 | }; |
1068 | ||
1069 | static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev) | |
1070 | { | |
1071 | struct drm_encoder *encoder; | |
1072 | ||
1073 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1074 | if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) | |
1075 | return encoder; | |
1076 | } | |
1077 | ||
1078 | return NULL; | |
1079 | } | |
1080 | ||
2c348e50 AP |
1081 | /** |
1082 | * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent | |
1083 | * clocks. None-coherent clocks means that audio and TMDS clocks have not the | |
1084 | * same source (drifts between clocks). In this case assumption is that CTS is | |
1085 | * automatically calculated by hardware. | |
1086 | * | |
1087 | * @audio_fs: audio frame clock frequency in Hz | |
1088 | * | |
1089 | * Values computed are based on table described in HDMI specification 1.4b | |
1090 | * | |
1091 | * Returns n value. | |
1092 | */ | |
1093 | static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs) | |
1094 | { | |
1095 | unsigned int n; | |
1096 | ||
1097 | switch (audio_fs) { | |
1098 | case 32000: | |
1099 | n = 4096; | |
1100 | break; | |
1101 | case 44100: | |
1102 | n = 6272; | |
1103 | break; | |
1104 | case 48000: | |
1105 | n = 6144; | |
1106 | break; | |
1107 | case 88200: | |
1108 | n = 6272 * 2; | |
1109 | break; | |
1110 | case 96000: | |
1111 | n = 6144 * 2; | |
1112 | break; | |
1113 | case 176400: | |
1114 | n = 6272 * 4; | |
1115 | break; | |
1116 | case 192000: | |
1117 | n = 6144 * 4; | |
1118 | break; | |
1119 | default: | |
1120 | /* Not pre-defined, recommended value: 128 * fs / 1000 */ | |
1121 | n = (audio_fs * 128) / 1000; | |
1122 | } | |
1123 | ||
1124 | return n; | |
1125 | } | |
1126 | ||
1127 | static int hdmi_audio_configure(struct sti_hdmi *hdmi, | |
1128 | struct hdmi_audio_params *params) | |
1129 | { | |
1130 | int audio_cfg, n; | |
1131 | struct hdmi_audio_infoframe *info = ¶ms->cea; | |
1132 | ||
1133 | DRM_DEBUG_DRIVER("\n"); | |
1134 | ||
1135 | if (!hdmi->enabled) | |
1136 | return 0; | |
1137 | ||
1138 | /* update N parameter */ | |
1139 | n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate); | |
1140 | ||
1141 | DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n", | |
1142 | params->sample_rate, hdmi->mode.clock * 1000, n); | |
1143 | hdmi_write(hdmi, n, HDMI_AUDN); | |
1144 | ||
1145 | /* update HDMI registers according to configuration */ | |
1146 | audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | | |
1147 | HDMI_AUD_CFG_ONE_BIT_INVALID; | |
1148 | ||
1149 | switch (info->channels) { | |
1150 | case 8: | |
1151 | audio_cfg |= HDMI_AUD_CFG_CH78_VALID; | |
1152 | case 6: | |
1153 | audio_cfg |= HDMI_AUD_CFG_CH56_VALID; | |
1154 | case 4: | |
1155 | audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH; | |
1156 | case 2: | |
1157 | audio_cfg |= HDMI_AUD_CFG_CH12_VALID; | |
1158 | break; | |
1159 | default: | |
1160 | DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n", | |
1161 | info->channels); | |
1162 | return -EINVAL; | |
1163 | } | |
1164 | ||
1165 | hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); | |
1166 | ||
1167 | hdmi->audio = *params; | |
1168 | ||
1169 | return hdmi_audio_infoframe_config(hdmi); | |
1170 | } | |
1171 | ||
5dd0775e | 1172 | static void hdmi_audio_shutdown(struct device *dev, void *data) |
2c348e50 AP |
1173 | { |
1174 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1175 | int audio_cfg; | |
1176 | ||
1177 | DRM_DEBUG_DRIVER("\n"); | |
1178 | ||
1179 | /* disable audio */ | |
1180 | audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | | |
1181 | HDMI_AUD_CFG_ONE_BIT_INVALID; | |
1182 | hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); | |
1183 | ||
1184 | hdmi->audio.enabled = 0; | |
1185 | hdmi_audio_infoframe_config(hdmi); | |
1186 | } | |
1187 | ||
1188 | static int hdmi_audio_hw_params(struct device *dev, | |
5dd0775e | 1189 | void *data, |
2c348e50 AP |
1190 | struct hdmi_codec_daifmt *daifmt, |
1191 | struct hdmi_codec_params *params) | |
1192 | { | |
1193 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1194 | int ret; | |
1195 | struct hdmi_audio_params audio = { | |
1196 | .sample_width = params->sample_width, | |
1197 | .sample_rate = params->sample_rate, | |
1198 | .cea = params->cea, | |
1199 | }; | |
1200 | ||
1201 | DRM_DEBUG_DRIVER("\n"); | |
1202 | ||
1203 | if (!hdmi->enabled) | |
1204 | return 0; | |
1205 | ||
1206 | if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv || | |
1207 | daifmt->frame_clk_inv || daifmt->bit_clk_master || | |
1208 | daifmt->frame_clk_master) { | |
1209 | dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, | |
1210 | daifmt->bit_clk_inv, daifmt->frame_clk_inv, | |
1211 | daifmt->bit_clk_master, | |
1212 | daifmt->frame_clk_master); | |
1213 | return -EINVAL; | |
1214 | } | |
1215 | ||
1216 | audio.enabled = 1; | |
1217 | ||
1218 | ret = hdmi_audio_configure(hdmi, &audio); | |
1219 | if (ret < 0) | |
1220 | return ret; | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
5dd0775e | 1225 | static int hdmi_audio_digital_mute(struct device *dev, void *data, bool enable) |
2c348e50 AP |
1226 | { |
1227 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1228 | ||
1229 | DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable"); | |
1230 | ||
1231 | if (enable) | |
1232 | hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK); | |
1233 | else | |
1234 | hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK); | |
1235 | ||
1236 | return 0; | |
1237 | } | |
1238 | ||
5dd0775e | 1239 | static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) |
2c348e50 AP |
1240 | { |
1241 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1242 | struct drm_connector *connector = hdmi->drm_connector; | |
1243 | ||
1244 | DRM_DEBUG_DRIVER("\n"); | |
1245 | memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static const struct hdmi_codec_ops audio_codec_ops = { | |
1251 | .hw_params = hdmi_audio_hw_params, | |
1252 | .audio_shutdown = hdmi_audio_shutdown, | |
1253 | .digital_mute = hdmi_audio_digital_mute, | |
1254 | .get_eld = hdmi_audio_get_eld, | |
1255 | }; | |
1256 | ||
1257 | static int sti_hdmi_register_audio_driver(struct device *dev, | |
1258 | struct sti_hdmi *hdmi) | |
1259 | { | |
1260 | struct hdmi_codec_pdata codec_data = { | |
1261 | .ops = &audio_codec_ops, | |
1262 | .max_i2s_channels = 8, | |
1263 | .i2s = 1, | |
1264 | }; | |
1265 | ||
1266 | DRM_DEBUG_DRIVER("\n"); | |
1267 | ||
1268 | hdmi->audio.enabled = 0; | |
1269 | ||
1270 | hdmi->audio_pdev = platform_device_register_data( | |
1271 | dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, | |
1272 | &codec_data, sizeof(codec_data)); | |
1273 | ||
1274 | if (IS_ERR(hdmi->audio_pdev)) | |
1275 | return PTR_ERR(hdmi->audio_pdev); | |
1276 | ||
1277 | DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev)); | |
1278 | ||
1279 | return 0; | |
1280 | } | |
1281 | ||
5402626c BG |
1282 | static int sti_hdmi_bind(struct device *dev, struct device *master, void *data) |
1283 | { | |
1284 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); | |
1285 | struct drm_device *drm_dev = data; | |
1286 | struct drm_encoder *encoder; | |
1287 | struct sti_hdmi_connector *connector; | |
1288 | struct drm_connector *drm_connector; | |
1289 | struct drm_bridge *bridge; | |
5402626c BG |
1290 | int err; |
1291 | ||
5402626c BG |
1292 | /* Set the drm device handle */ |
1293 | hdmi->drm_dev = drm_dev; | |
1294 | ||
1295 | encoder = sti_hdmi_find_encoder(drm_dev); | |
1296 | if (!encoder) | |
807642d7 | 1297 | return -EINVAL; |
5402626c BG |
1298 | |
1299 | connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); | |
1300 | if (!connector) | |
807642d7 | 1301 | return -EINVAL; |
5402626c BG |
1302 | |
1303 | connector->hdmi = hdmi; | |
1304 | ||
1305 | bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); | |
1306 | if (!bridge) | |
807642d7 | 1307 | return -EINVAL; |
5402626c BG |
1308 | |
1309 | bridge->driver_private = hdmi; | |
b07b90fd | 1310 | bridge->funcs = &sti_hdmi_bridge_funcs; |
3d3f8b1f | 1311 | drm_bridge_attach(drm_dev, bridge); |
5402626c BG |
1312 | |
1313 | encoder->bridge = bridge; | |
1314 | connector->encoder = encoder; | |
1315 | ||
1316 | drm_connector = (struct drm_connector *)connector; | |
1317 | ||
1318 | drm_connector->polled = DRM_CONNECTOR_POLL_HPD; | |
1319 | ||
1320 | drm_connector_init(drm_dev, drm_connector, | |
1321 | &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA); | |
1322 | drm_connector_helper_add(drm_connector, | |
1323 | &sti_hdmi_connector_helper_funcs); | |
1324 | ||
5671cefb VA |
1325 | /* initialise property */ |
1326 | sti_hdmi_connector_init_property(drm_dev, drm_connector); | |
1327 | ||
2c348e50 AP |
1328 | hdmi->drm_connector = drm_connector; |
1329 | ||
5402626c BG |
1330 | err = drm_mode_connector_attach_encoder(drm_connector, encoder); |
1331 | if (err) { | |
1332 | DRM_ERROR("Failed to attach a connector to a encoder\n"); | |
1333 | goto err_sysfs; | |
1334 | } | |
1335 | ||
2c348e50 AP |
1336 | err = sti_hdmi_register_audio_driver(dev, hdmi); |
1337 | if (err) { | |
1338 | DRM_ERROR("Failed to attach an audio codec\n"); | |
1339 | goto err_sysfs; | |
1340 | } | |
1341 | ||
1342 | /* Initialize audio infoframe */ | |
1343 | err = hdmi_audio_infoframe_init(&hdmi->audio.cea); | |
1344 | if (err) { | |
1345 | DRM_ERROR("Failed to init audio infoframe\n"); | |
1346 | goto err_sysfs; | |
1347 | } | |
1348 | ||
5402626c BG |
1349 | /* Enable default interrupts */ |
1350 | hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN); | |
1351 | ||
1352 | return 0; | |
1353 | ||
1354 | err_sysfs: | |
84601dbd | 1355 | drm_bridge_remove(bridge); |
2c348e50 | 1356 | hdmi->drm_connector = NULL; |
5402626c BG |
1357 | return -EINVAL; |
1358 | } | |
1359 | ||
1360 | static void sti_hdmi_unbind(struct device *dev, | |
1361 | struct device *master, void *data) | |
1362 | { | |
7ea6e6e4 VA |
1363 | struct sti_hdmi *hdmi = dev_get_drvdata(dev); |
1364 | struct drm_device *drm_dev = data; | |
1365 | ||
1366 | hdmi_debugfs_exit(hdmi, drm_dev->primary); | |
5402626c BG |
1367 | } |
1368 | ||
1369 | static const struct component_ops sti_hdmi_ops = { | |
1370 | .bind = sti_hdmi_bind, | |
1371 | .unbind = sti_hdmi_unbind, | |
1372 | }; | |
1373 | ||
8e932cf0 | 1374 | static const struct of_device_id hdmi_of_match[] = { |
5402626c BG |
1375 | { |
1376 | .compatible = "st,stih416-hdmi", | |
1377 | .data = &tx3g0c55phy_ops, | |
1378 | }, { | |
1379 | .compatible = "st,stih407-hdmi", | |
1380 | .data = &tx3g4c28phy_ops, | |
1381 | }, { | |
1382 | /* end node */ | |
1383 | } | |
1384 | }; | |
1385 | MODULE_DEVICE_TABLE(of, hdmi_of_match); | |
1386 | ||
1387 | static int sti_hdmi_probe(struct platform_device *pdev) | |
1388 | { | |
1389 | struct device *dev = &pdev->dev; | |
1390 | struct sti_hdmi *hdmi; | |
1391 | struct device_node *np = dev->of_node; | |
1392 | struct resource *res; | |
53bdcf5f | 1393 | struct device_node *ddc; |
5402626c BG |
1394 | int ret; |
1395 | ||
1396 | DRM_INFO("%s\n", __func__); | |
1397 | ||
1398 | hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); | |
1399 | if (!hdmi) | |
1400 | return -ENOMEM; | |
1401 | ||
53bdcf5f BG |
1402 | ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0); |
1403 | if (ddc) { | |
4d5821a7 | 1404 | hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc); |
53bdcf5f | 1405 | of_node_put(ddc); |
4d5821a7 VZ |
1406 | if (!hdmi->ddc_adapt) |
1407 | return -EPROBE_DEFER; | |
53bdcf5f BG |
1408 | } |
1409 | ||
5402626c BG |
1410 | hdmi->dev = pdev->dev; |
1411 | ||
1412 | /* Get resources */ | |
1413 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg"); | |
1414 | if (!res) { | |
1415 | DRM_ERROR("Invalid hdmi resource\n"); | |
807642d7 VZ |
1416 | ret = -ENOMEM; |
1417 | goto release_adapter; | |
5402626c BG |
1418 | } |
1419 | hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | |
807642d7 VZ |
1420 | if (!hdmi->regs) { |
1421 | ret = -ENOMEM; | |
1422 | goto release_adapter; | |
1423 | } | |
5402626c BG |
1424 | |
1425 | if (of_device_is_compatible(np, "st,stih416-hdmi")) { | |
1426 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1427 | "syscfg"); | |
1428 | if (!res) { | |
1429 | DRM_ERROR("Invalid syscfg resource\n"); | |
807642d7 VZ |
1430 | ret = -ENOMEM; |
1431 | goto release_adapter; | |
5402626c BG |
1432 | } |
1433 | hdmi->syscfg = devm_ioremap_nocache(dev, res->start, | |
1434 | resource_size(res)); | |
807642d7 VZ |
1435 | if (!hdmi->syscfg) { |
1436 | ret = -ENOMEM; | |
1437 | goto release_adapter; | |
1438 | } | |
5402626c BG |
1439 | } |
1440 | ||
1441 | hdmi->phy_ops = (struct hdmi_phy_ops *) | |
1442 | of_match_node(hdmi_of_match, np)->data; | |
1443 | ||
1444 | /* Get clock resources */ | |
1445 | hdmi->clk_pix = devm_clk_get(dev, "pix"); | |
1446 | if (IS_ERR(hdmi->clk_pix)) { | |
1447 | DRM_ERROR("Cannot get hdmi_pix clock\n"); | |
807642d7 VZ |
1448 | ret = PTR_ERR(hdmi->clk_pix); |
1449 | goto release_adapter; | |
5402626c BG |
1450 | } |
1451 | ||
1452 | hdmi->clk_tmds = devm_clk_get(dev, "tmds"); | |
1453 | if (IS_ERR(hdmi->clk_tmds)) { | |
1454 | DRM_ERROR("Cannot get hdmi_tmds clock\n"); | |
807642d7 VZ |
1455 | ret = PTR_ERR(hdmi->clk_tmds); |
1456 | goto release_adapter; | |
5402626c BG |
1457 | } |
1458 | ||
1459 | hdmi->clk_phy = devm_clk_get(dev, "phy"); | |
1460 | if (IS_ERR(hdmi->clk_phy)) { | |
1461 | DRM_ERROR("Cannot get hdmi_phy clock\n"); | |
807642d7 VZ |
1462 | ret = PTR_ERR(hdmi->clk_phy); |
1463 | goto release_adapter; | |
5402626c BG |
1464 | } |
1465 | ||
1466 | hdmi->clk_audio = devm_clk_get(dev, "audio"); | |
1467 | if (IS_ERR(hdmi->clk_audio)) { | |
1468 | DRM_ERROR("Cannot get hdmi_audio clock\n"); | |
807642d7 VZ |
1469 | ret = PTR_ERR(hdmi->clk_audio); |
1470 | goto release_adapter; | |
5402626c BG |
1471 | } |
1472 | ||
76569207 | 1473 | hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; |
5402626c BG |
1474 | |
1475 | init_waitqueue_head(&hdmi->wait_event); | |
1476 | ||
1477 | hdmi->irq = platform_get_irq_byname(pdev, "irq"); | |
1478 | ||
1479 | ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq, | |
1480 | hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi); | |
1481 | if (ret) { | |
1482 | DRM_ERROR("Failed to register HDMI interrupt\n"); | |
807642d7 | 1483 | goto release_adapter; |
5402626c BG |
1484 | } |
1485 | ||
1486 | hdmi->reset = devm_reset_control_get(dev, "hdmi"); | |
1487 | /* Take hdmi out of reset */ | |
1488 | if (!IS_ERR(hdmi->reset)) | |
1489 | reset_control_deassert(hdmi->reset); | |
1490 | ||
1491 | platform_set_drvdata(pdev, hdmi); | |
1492 | ||
1493 | return component_add(&pdev->dev, &sti_hdmi_ops); | |
807642d7 VZ |
1494 | |
1495 | release_adapter: | |
4d5821a7 | 1496 | i2c_put_adapter(hdmi->ddc_adapt); |
807642d7 VZ |
1497 | |
1498 | return ret; | |
5402626c BG |
1499 | } |
1500 | ||
1501 | static int sti_hdmi_remove(struct platform_device *pdev) | |
1502 | { | |
41a14623 BG |
1503 | struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev); |
1504 | ||
4d5821a7 | 1505 | i2c_put_adapter(hdmi->ddc_adapt); |
2c348e50 AP |
1506 | if (hdmi->audio_pdev) |
1507 | platform_device_unregister(hdmi->audio_pdev); | |
5402626c | 1508 | component_del(&pdev->dev, &sti_hdmi_ops); |
4d5821a7 | 1509 | |
5402626c BG |
1510 | return 0; |
1511 | } | |
1512 | ||
1513 | struct platform_driver sti_hdmi_driver = { | |
1514 | .driver = { | |
1515 | .name = "sti-hdmi", | |
1516 | .owner = THIS_MODULE, | |
1517 | .of_match_table = hdmi_of_match, | |
1518 | }, | |
1519 | .probe = sti_hdmi_probe, | |
1520 | .remove = sti_hdmi_remove, | |
1521 | }; | |
1522 | ||
5402626c BG |
1523 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); |
1524 | MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); | |
1525 | MODULE_LICENSE("GPL"); |