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drm/i915: Update intel_logical_ring_begin() to take a request structure
[deliverable/linux.git] / drivers / gpu / drm / sti / sti_mixer.c
CommitLineData
e21e2193
BG		 1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Fabien Dessenne <fabien.dessenne@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
7 */
8
d219673d 9#include "sti_compositor.h"
e21e2193
BG		 10#include "sti_mixer.h"
11#include "sti_vtg.h"
12
13/* Identity: G=Y , B=Cb , R=Cr */
14static const u32 mixerColorSpaceMatIdentity[] = {
15 0x10000000, 0x00000000, 0x10000000, 0x00001000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000
17};
18
19/* regs offset */
20#define GAM_MIXER_CTL 0x00
21#define GAM_MIXER_BKC 0x04
22#define GAM_MIXER_BCO 0x0C
23#define GAM_MIXER_BCS 0x10
24#define GAM_MIXER_AVO 0x28
25#define GAM_MIXER_AVS 0x2C
26#define GAM_MIXER_CRB 0x34
27#define GAM_MIXER_ACT 0x38
28#define GAM_MIXER_MBP 0x3C
29#define GAM_MIXER_MX0 0x80
30
31/* id for depth of CRB reg */
32#define GAM_DEPTH_VID0_ID 1
33#define GAM_DEPTH_VID1_ID 2
34#define GAM_DEPTH_GDP0_ID 3
35#define GAM_DEPTH_GDP1_ID 4
36#define GAM_DEPTH_GDP2_ID 5
37#define GAM_DEPTH_GDP3_ID 6
38#define GAM_DEPTH_MASK_ID 7
39
40/* mask in CTL reg */
41#define GAM_CTL_BACK_MASK BIT(0)
42#define GAM_CTL_VID0_MASK BIT(1)
43#define GAM_CTL_VID1_MASK BIT(2)
44#define GAM_CTL_GDP0_MASK BIT(3)
45#define GAM_CTL_GDP1_MASK BIT(4)
46#define GAM_CTL_GDP2_MASK BIT(5)
47#define GAM_CTL_GDP3_MASK BIT(6)
96006a77 48#define GAM_CTL_CURSOR_MASK BIT(9)
e21e2193
BG		 49
50const char *sti_mixer_to_str(struct sti_mixer *mixer)
51{
52 switch (mixer->id) {
53 case STI_MIXER_MAIN:
54 return "MAIN_MIXER";
55 case STI_MIXER_AUX:
56 return "AUX_MIXER";
57 default:
58 return "<UNKNOWN MIXER>";
59 }
60}
61
62static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
63{
64 return readl(mixer->regs + reg_id);
65}
66
67static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
68 u32 reg_id, u32 val)
69{
70 writel(val, mixer->regs + reg_id);
71}
72
73void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
74{
75 u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
76
77 val &= ~GAM_CTL_BACK_MASK;
78 val |= enable;
79 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
80}
81
82static void sti_mixer_set_background_color(struct sti_mixer *mixer,
83 u8 red, u8 green, u8 blue)
84{
85 u32 val = (red << 16) | (green << 8) | blue;
86
87 sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
88}
89
90static void sti_mixer_set_background_area(struct sti_mixer *mixer,
91 struct drm_display_mode *mode)
92{
93 u32 ydo, xdo, yds, xds;
94
95 ydo = sti_vtg_get_line_number(*mode, 0);
96 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
97 xdo = sti_vtg_get_pixel_number(*mode, 0);
98 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
99
100 sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
101 sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
102}
103
104int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer)
105{
106 int layer_id = 0, depth = layer->zorder;
107 u32 mask, val;
108
109 if (depth >= GAM_MIXER_NB_DEPTH_LEVEL)
110 return 1;
111
112 switch (layer->desc) {
113 case STI_GDP_0:
114 layer_id = GAM_DEPTH_GDP0_ID;
115 break;
116 case STI_GDP_1:
117 layer_id = GAM_DEPTH_GDP1_ID;
118 break;
119 case STI_GDP_2:
120 layer_id = GAM_DEPTH_GDP2_ID;
121 break;
122 case STI_GDP_3:
123 layer_id = GAM_DEPTH_GDP3_ID;
124 break;
125 case STI_VID_0:
4fdbc678 126 case STI_HQVDP_0:
e21e2193
BG		 127 layer_id = GAM_DEPTH_VID0_ID;
128 break;
129 case STI_VID_1:
130 layer_id = GAM_DEPTH_VID1_ID;
131 break;
96006a77
BG		 132 case STI_CURSOR:
133 /* no need to set depth for cursor */
134 return 0;
e21e2193
BG		 135 default:
136 DRM_ERROR("Unknown layer %d\n", layer->desc);
137 return 1;
138 }
139 mask = GAM_DEPTH_MASK_ID << (3 * depth);
140 layer_id = layer_id << (3 * depth);
141
d219673d
BG		 142 DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
143 sti_layer_to_str(layer), depth);
e21e2193
BG		 144 dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
145 layer_id, mask);
146
147 val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
148 val &= ~mask;
149 val |= layer_id;
150 sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
151
152 dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
153 sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
154 return 0;
155}
156
157int sti_mixer_active_video_area(struct sti_mixer *mixer,
158 struct drm_display_mode *mode)
159{
160 u32 ydo, xdo, yds, xds;
161
162 ydo = sti_vtg_get_line_number(*mode, 0);
163 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
164 xdo = sti_vtg_get_pixel_number(*mode, 0);
165 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
166
167 DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
168 sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
169 sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
170 sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
171
172 sti_mixer_set_background_color(mixer, 0xFF, 0, 0);
173
174 sti_mixer_set_background_area(mixer, mode);
175 sti_mixer_set_background_status(mixer, true);
176 return 0;
177}
178
179static u32 sti_mixer_get_layer_mask(struct sti_layer *layer)
180{
181 switch (layer->desc) {
182 case STI_BACK:
183 return GAM_CTL_BACK_MASK;
184 case STI_GDP_0:
185 return GAM_CTL_GDP0_MASK;
186 case STI_GDP_1:
187 return GAM_CTL_GDP1_MASK;
188 case STI_GDP_2:
189 return GAM_CTL_GDP2_MASK;
190 case STI_GDP_3:
191 return GAM_CTL_GDP3_MASK;
192 case STI_VID_0:
4fdbc678 193 case STI_HQVDP_0:
e21e2193
BG		 194 return GAM_CTL_VID0_MASK;
195 case STI_VID_1:
196 return GAM_CTL_VID1_MASK;
96006a77
BG		 197 case STI_CURSOR:
198 return GAM_CTL_CURSOR_MASK;
e21e2193
BG		 199 default:
200 return 0;
201 }
202}
203
204int sti_mixer_set_layer_status(struct sti_mixer *mixer,
205 struct sti_layer *layer, bool status)
206{
207 u32 mask, val;
208
d219673d
BG		 209 DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
210 sti_mixer_to_str(mixer), sti_layer_to_str(layer));
211
e21e2193
BG		 212 mask = sti_mixer_get_layer_mask(layer);
213 if (!mask) {
214 DRM_ERROR("Can not find layer mask\n");
215 return -EINVAL;
216 }
217
218 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
219 val &= ~mask;
220 val |= status ? mask : 0;
221 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
222
223 return 0;
224}
225
2f7d0e82
BG		 226void sti_mixer_clear_all_layers(struct sti_mixer *mixer)
227{
228 u32 val;
229
230 DRM_DEBUG_DRIVER("%s clear all layer\n", sti_mixer_to_str(mixer));
231 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL) & 0xFFFF0000;
232 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
233}
234
e21e2193
BG		 235void sti_mixer_set_matrix(struct sti_mixer *mixer)
236{
237 unsigned int i;
238
239 for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
240 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
241 mixerColorSpaceMatIdentity[i]);
242}
243
244struct sti_mixer *sti_mixer_create(struct device *dev, int id,
245 void __iomem *baseaddr)
246{
247 struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
248 struct device_node *np = dev->of_node;
249
250 dev_dbg(dev, "%s\n", __func__);
251 if (!mixer) {
252 DRM_ERROR("Failed to allocated memory for mixer\n");
253 return NULL;
254 }
255 mixer->regs = baseaddr;
256 mixer->dev = dev;
257 mixer->id = id;
258
259 if (of_device_is_compatible(np, "st,stih416-compositor"))
260 sti_mixer_set_matrix(mixer);
261
262 DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
263 sti_mixer_to_str(mixer), mixer->regs);
264
265 return mixer;
266}
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