[deliverable/linux.git] / drivers / gpu / drm / sti / sti_mixer.c

/*
 * Copyright (C) STMicroelectronics SA 2014
 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
 *          Fabien Dessenne <fabien.dessenne@st.com>
 *          for STMicroelectronics.
 * License terms:  GNU General Public License (GPL), version 2
 */
#include <linux/seq_file.h>

#include "sti_compositor.h"
#include "sti_mixer.h"
#include "sti_vtg.h"

/* Module parameter to set the background color of the mixer */
static unsigned int bkg_color = 0x000000;
MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
module_param_named(bkgcolor, bkg_color, int, 0644);

/* Identity: G=Y , B=Cb , R=Cr */
static const u32 mixerColorSpaceMatIdentity[] = {
	0x10000000, 0x00000000, 0x10000000, 0x00001000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000
};

/* regs offset */
#define GAM_MIXER_CTL      0x00
#define GAM_MIXER_BKC      0x04
#define GAM_MIXER_BCO      0x0C
#define GAM_MIXER_BCS      0x10
#define GAM_MIXER_AVO      0x28
#define GAM_MIXER_AVS      0x2C
#define GAM_MIXER_CRB      0x34
#define GAM_MIXER_ACT      0x38
#define GAM_MIXER_MBP      0x3C
#define GAM_MIXER_MX0      0x80

/* id for depth of CRB reg */
#define GAM_DEPTH_VID0_ID  1
#define GAM_DEPTH_VID1_ID  2
#define GAM_DEPTH_GDP0_ID  3
#define GAM_DEPTH_GDP1_ID  4
#define GAM_DEPTH_GDP2_ID  5
#define GAM_DEPTH_GDP3_ID  6
#define GAM_DEPTH_MASK_ID  7

/* mask in CTL reg */
#define GAM_CTL_BACK_MASK  BIT(0)
#define GAM_CTL_VID0_MASK  BIT(1)
#define GAM_CTL_VID1_MASK  BIT(2)
#define GAM_CTL_GDP0_MASK  BIT(3)
#define GAM_CTL_GDP1_MASK  BIT(4)
#define GAM_CTL_GDP2_MASK  BIT(5)
#define GAM_CTL_GDP3_MASK  BIT(6)
#define GAM_CTL_CURSOR_MASK BIT(9)

const char *sti_mixer_to_str(struct sti_mixer *mixer)
{
	switch (mixer->id) {
	case STI_MIXER_MAIN:
		return "MAIN_MIXER";
	case STI_MIXER_AUX:
		return "AUX_MIXER";
	default:
		return "<UNKNOWN MIXER>";
	}
}

static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
{
	return readl(mixer->regs + reg_id);
}

static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
				       u32 reg_id, u32 val)
{
	writel(val, mixer->regs + reg_id);
}

#define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
				   sti_mixer_reg_read(mixer, reg))

static void mixer_dbg_ctl(struct seq_file *s, int val)
{
	unsigned int i;
	int count = 0;
	char *const disp_layer[] = {"BKG", "VID0", "VID1", "GDP0",
				    "GDP1", "GDP2", "GDP3"};

	seq_puts(s, "\tEnabled: ");
	for (i = 0; i < 7; i++) {
		if (val & 1) {
			seq_printf(s, "%s ", disp_layer[i]);
			count++;
		}
		val = val >> 1;
	}

	val = val >> 2;
	if (val & 1) {
		seq_puts(s, "CURS ");
		count++;
	}
	if (!count)
		seq_puts(s, "Nothing");
}

static void mixer_dbg_crb(struct seq_file *s, int val)
{
	int i;

	seq_puts(s, "\tDepth: ");
	for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
		switch (val & GAM_DEPTH_MASK_ID) {
		case GAM_DEPTH_VID0_ID:
			seq_puts(s, "VID0");
			break;
		case GAM_DEPTH_VID1_ID:
			seq_puts(s, "VID1");
			break;
		case GAM_DEPTH_GDP0_ID:
			seq_puts(s, "GDP0");
			break;
		case GAM_DEPTH_GDP1_ID:
			seq_puts(s, "GDP1");
			break;
		case GAM_DEPTH_GDP2_ID:
			seq_puts(s, "GDP2");
			break;
		case GAM_DEPTH_GDP3_ID:
			seq_puts(s, "GDP3");
			break;
		default:
			seq_puts(s, "---");
		}

		if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1)
			seq_puts(s, " < ");
		val = val >> 3;
	}
}

static void mixer_dbg_mxn(struct seq_file *s, void *addr)
{
	int i;

	for (i = 1; i < 8; i++)
		seq_printf(s, "-0x%08X", (int)readl(addr + i * 4));
}

static int mixer_dbg_show(struct seq_file *s, void *arg)
{
	struct drm_info_node *node = s->private;
	struct sti_mixer *mixer = (struct sti_mixer *)node->info_ent->data;

	seq_printf(s, "%s: (vaddr = 0x%p)",
		   sti_mixer_to_str(mixer), mixer->regs);

	DBGFS_DUMP(GAM_MIXER_CTL);
	mixer_dbg_ctl(s, sti_mixer_reg_read(mixer, GAM_MIXER_CTL));
	DBGFS_DUMP(GAM_MIXER_BKC);
	DBGFS_DUMP(GAM_MIXER_BCO);
	DBGFS_DUMP(GAM_MIXER_BCS);
	DBGFS_DUMP(GAM_MIXER_AVO);
	DBGFS_DUMP(GAM_MIXER_AVS);
	DBGFS_DUMP(GAM_MIXER_CRB);
	mixer_dbg_crb(s, sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
	DBGFS_DUMP(GAM_MIXER_ACT);
	DBGFS_DUMP(GAM_MIXER_MBP);
	DBGFS_DUMP(GAM_MIXER_MX0);
	mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0);
	seq_puts(s, "\n");

	return 0;
}

static struct drm_info_list mixer0_debugfs_files[] = {
	{ "mixer_main", mixer_dbg_show, 0, NULL },
};

static struct drm_info_list mixer1_debugfs_files[] = {
	{ "mixer_aux", mixer_dbg_show, 0, NULL },
};

int sti_mixer_debugfs_init(struct sti_mixer *mixer, struct drm_minor *minor)
{
	unsigned int i;
	struct drm_info_list *mixer_debugfs_files;
	int nb_files;

	switch (mixer->id) {
	case STI_MIXER_MAIN:
		mixer_debugfs_files = mixer0_debugfs_files;
		nb_files = ARRAY_SIZE(mixer0_debugfs_files);
		break;
	case STI_MIXER_AUX:
		mixer_debugfs_files = mixer1_debugfs_files;
		nb_files = ARRAY_SIZE(mixer1_debugfs_files);
		break;
	default:
		return -EINVAL;
	}

	for (i = 0; i < nb_files; i++)
		mixer_debugfs_files[i].data = mixer;

	return drm_debugfs_create_files(mixer_debugfs_files,
					nb_files,
					minor->debugfs_root, minor);
}

void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
{
	u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);

	val &= ~GAM_CTL_BACK_MASK;
	val |= enable;
	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
}

static void sti_mixer_set_background_color(struct sti_mixer *mixer,
					   unsigned int rgb)
{
	sti_mixer_reg_write(mixer, GAM_MIXER_BKC, rgb);
}

static void sti_mixer_set_background_area(struct sti_mixer *mixer,
					  struct drm_display_mode *mode)
{
	u32 ydo, xdo, yds, xds;

	ydo = sti_vtg_get_line_number(*mode, 0);
	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	xdo = sti_vtg_get_pixel_number(*mode, 0);
	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);

	sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
	sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
}

int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane)
{
	int plane_id, depth = plane->drm_plane.state->normalized_zpos;
	unsigned int i;
	u32 mask, val;

	switch (plane->desc) {
	case STI_GDP_0:
		plane_id = GAM_DEPTH_GDP0_ID;
		break;
	case STI_GDP_1:
		plane_id = GAM_DEPTH_GDP1_ID;
		break;
	case STI_GDP_2:
		plane_id = GAM_DEPTH_GDP2_ID;
		break;
	case STI_GDP_3:
		plane_id = GAM_DEPTH_GDP3_ID;
		break;
	case STI_HQVDP_0:
		plane_id = GAM_DEPTH_VID0_ID;
		break;
	case STI_CURSOR:
		/* no need to set depth for cursor */
		return 0;
	default:
		DRM_ERROR("Unknown plane %d\n", plane->desc);
		return 1;
	}

	/* Search if a previous depth was already assigned to the plane */
	val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
	for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
		mask = GAM_DEPTH_MASK_ID << (3 * i);
		if ((val & mask) == plane_id << (3 * i))
			break;
	}

	mask |= GAM_DEPTH_MASK_ID << (3 * depth);
	plane_id = plane_id << (3 * depth);

	DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
			 sti_plane_to_str(plane), depth);
	dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
		plane_id, mask);

	val &= ~mask;
	val |= plane_id;
	sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);

	dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
		sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
	return 0;
}

int sti_mixer_active_video_area(struct sti_mixer *mixer,
				struct drm_display_mode *mode)
{
	u32 ydo, xdo, yds, xds;

	ydo = sti_vtg_get_line_number(*mode, 0);
	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	xdo = sti_vtg_get_pixel_number(*mode, 0);
	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);

	DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
			 sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
	sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
	sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);

	sti_mixer_set_background_color(mixer, bkg_color);

	sti_mixer_set_background_area(mixer, mode);
	sti_mixer_set_background_status(mixer, true);
	return 0;
}

static u32 sti_mixer_get_plane_mask(struct sti_plane *plane)
{
	switch (plane->desc) {
	case STI_BACK:
		return GAM_CTL_BACK_MASK;
	case STI_GDP_0:
		return GAM_CTL_GDP0_MASK;
	case STI_GDP_1:
		return GAM_CTL_GDP1_MASK;
	case STI_GDP_2:
		return GAM_CTL_GDP2_MASK;
	case STI_GDP_3:
		return GAM_CTL_GDP3_MASK;
	case STI_HQVDP_0:
		return GAM_CTL_VID0_MASK;
	case STI_CURSOR:
		return GAM_CTL_CURSOR_MASK;
	default:
		return 0;
	}
}

int sti_mixer_set_plane_status(struct sti_mixer *mixer,
			       struct sti_plane *plane, bool status)
{
	u32 mask, val;

	DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
			 sti_mixer_to_str(mixer), sti_plane_to_str(plane));

	mask = sti_mixer_get_plane_mask(plane);
	if (!mask) {
		DRM_ERROR("Can't find layer mask\n");
		return -EINVAL;
	}

	val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
	val &= ~mask;
	val |= status ? mask : 0;
	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);

	return 0;
}

void sti_mixer_set_matrix(struct sti_mixer *mixer)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
		sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
				    mixerColorSpaceMatIdentity[i]);
}

struct sti_mixer *sti_mixer_create(struct device *dev,
				   struct drm_device *drm_dev,
				   int id,
				   void __iomem *baseaddr)
{
	struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
	struct device_node *np = dev->of_node;

	dev_dbg(dev, "%s\n", __func__);
	if (!mixer) {
		DRM_ERROR("Failed to allocated memory for mixer\n");
		return NULL;
	}
	mixer->regs = baseaddr;
	mixer->dev = dev;
	mixer->id = id;

	if (of_device_is_compatible(np, "st,stih416-compositor"))
		sti_mixer_set_matrix(mixer);

	DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
			 sti_mixer_to_str(mixer), mixer->regs);

	return mixer;
}
Commit	Line	Data
e21e2193 BG	1	/*
	2	* Copyright (C) STMicroelectronics SA 2014
	3	* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
	4	* Fabien Dessenne <fabien.dessenne@st.com>
	5	* for STMicroelectronics.
	6	* License terms: GNU General Public License (GPL), version 2
	7	*/
0f3e1561	8	#include <linux/seq_file.h>
e21e2193	9
d219673d	10	#include "sti_compositor.h"
e21e2193 BG	11	#include "sti_mixer.h"
	12	#include "sti_vtg.h"
	13
5260fb5b VA	14	/* Module parameter to set the background color of the mixer */
	15	static unsigned int bkg_color = 0x000000;
	16	MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
	17	module_param_named(bkgcolor, bkg_color, int, 0644);
	18
e21e2193 BG	19	/* Identity: G=Y , B=Cb , R=Cr */
	20	static const u32 mixerColorSpaceMatIdentity[] = {
	21	0x10000000, 0x00000000, 0x10000000, 0x00001000,
	22	0x00000000, 0x00000000, 0x00000000, 0x00000000
	23	};
	24
	25	/* regs offset */
	26	#define GAM_MIXER_CTL 0x00
	27	#define GAM_MIXER_BKC 0x04
	28	#define GAM_MIXER_BCO 0x0C
	29	#define GAM_MIXER_BCS 0x10
	30	#define GAM_MIXER_AVO 0x28
	31	#define GAM_MIXER_AVS 0x2C
	32	#define GAM_MIXER_CRB 0x34
	33	#define GAM_MIXER_ACT 0x38
	34	#define GAM_MIXER_MBP 0x3C
	35	#define GAM_MIXER_MX0 0x80
	36
	37	/* id for depth of CRB reg */
	38	#define GAM_DEPTH_VID0_ID 1
	39	#define GAM_DEPTH_VID1_ID 2
	40	#define GAM_DEPTH_GDP0_ID 3
	41	#define GAM_DEPTH_GDP1_ID 4
	42	#define GAM_DEPTH_GDP2_ID 5
	43	#define GAM_DEPTH_GDP3_ID 6
	44	#define GAM_DEPTH_MASK_ID 7
	45
	46	/* mask in CTL reg */
	47	#define GAM_CTL_BACK_MASK BIT(0)
	48	#define GAM_CTL_VID0_MASK BIT(1)
	49	#define GAM_CTL_VID1_MASK BIT(2)
	50	#define GAM_CTL_GDP0_MASK BIT(3)
	51	#define GAM_CTL_GDP1_MASK BIT(4)
	52	#define GAM_CTL_GDP2_MASK BIT(5)
	53	#define GAM_CTL_GDP3_MASK BIT(6)
96006a77	54	#define GAM_CTL_CURSOR_MASK BIT(9)
e21e2193 BG	55
	56	const char sti_mixer_to_str(struct sti_mixer mixer)
	57	{
	58	switch (mixer->id) {
	59	case STI_MIXER_MAIN:
	60	return "MAIN_MIXER";
	61	case STI_MIXER_AUX:
	62	return "AUX_MIXER";
	63	default:
	64	return "<UNKNOWN MIXER>";
	65	}
	66	}
	67
	68	static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
	69	{
	70	return readl(mixer->regs + reg_id);
	71	}
	72
	73	static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
	74	u32 reg_id, u32 val)
	75	{
	76	writel(val, mixer->regs + reg_id);
	77	}
	78
a5f81078 VA	79	#define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
	80	sti_mixer_reg_read(mixer, reg))
	81
	82	static void mixer_dbg_ctl(struct seq_file *s, int val)
	83	{
	84	unsigned int i;
	85	int count = 0;
	86	char *const disp_layer[] = {"BKG", "VID0", "VID1", "GDP0",
	87	"GDP1", "GDP2", "GDP3"};
	88
	89	seq_puts(s, "\tEnabled: ");
	90	for (i = 0; i < 7; i++) {
	91	if (val & 1) {
	92	seq_printf(s, "%s ", disp_layer[i]);
	93	count++;
	94	}
	95	val = val >> 1;
	96	}
	97
	98	val = val >> 2;
	99	if (val & 1) {
	100	seq_puts(s, "CURS ");
	101	count++;
	102	}
	103	if (!count)
	104	seq_puts(s, "Nothing");
	105	}
	106
	107	static void mixer_dbg_crb(struct seq_file *s, int val)
	108	{
	109	int i;
	110
	111	seq_puts(s, "\tDepth: ");
	112	for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
	113	switch (val & GAM_DEPTH_MASK_ID) {
	114	case GAM_DEPTH_VID0_ID:
	115	seq_puts(s, "VID0");
	116	break;
	117	case GAM_DEPTH_VID1_ID:
	118	seq_puts(s, "VID1");
	119	break;
	120	case GAM_DEPTH_GDP0_ID:
	121	seq_puts(s, "GDP0");
	122	break;
	123	case GAM_DEPTH_GDP1_ID:
	124	seq_puts(s, "GDP1");
	125	break;
	126	case GAM_DEPTH_GDP2_ID:
	127	seq_puts(s, "GDP2");
	128	break;
	129	case GAM_DEPTH_GDP3_ID:
	130	seq_puts(s, "GDP3");
	131	break;
	132	default:
	133	seq_puts(s, "---");
	134	}
	135
	136	if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1)
	137	seq_puts(s, " < ");
	138	val = val >> 3;
	139	}
	140	}
	141
	142	static void mixer_dbg_mxn(struct seq_file s, void addr)
143	{
144	int i;
145
146	for (i = 1; i < 8; i++)
147	seq_printf(s, "-0x%08X", (int)readl(addr + i * 4));
148	}
149
150	static int mixer_dbg_show(struct seq_file s, void arg)
151	{
152	struct drm_info_node *node = s->private;
153	struct sti_mixer mixer = (struct sti_mixer )node->info_ent->data;
a5f81078 VA	154
	155	seq_printf(s, "%s: (vaddr = 0x%p)",
	156	sti_mixer_to_str(mixer), mixer->regs);
	157
	158	DBGFS_DUMP(GAM_MIXER_CTL);
	159	mixer_dbg_ctl(s, sti_mixer_reg_read(mixer, GAM_MIXER_CTL));
	160	DBGFS_DUMP(GAM_MIXER_BKC);
	161	DBGFS_DUMP(GAM_MIXER_BCO);
	162	DBGFS_DUMP(GAM_MIXER_BCS);
	163	DBGFS_DUMP(GAM_MIXER_AVO);
	164	DBGFS_DUMP(GAM_MIXER_AVS);
	165	DBGFS_DUMP(GAM_MIXER_CRB);
	166	mixer_dbg_crb(s, sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
	167	DBGFS_DUMP(GAM_MIXER_ACT);
	168	DBGFS_DUMP(GAM_MIXER_MBP);
	169	DBGFS_DUMP(GAM_MIXER_MX0);
	170	mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0);
	171	seq_puts(s, "\n");
	172
a5f81078 VA	173	return 0;
	174	}
	175
	176	static struct drm_info_list mixer0_debugfs_files[] = {
	177	{ "mixer_main", mixer_dbg_show, 0, NULL },
	178	};
	179
	180	static struct drm_info_list mixer1_debugfs_files[] = {
	181	{ "mixer_aux", mixer_dbg_show, 0, NULL },
	182	};
	183
83af0a48	184	int sti_mixer_debugfs_init(struct sti_mixer mixer, struct drm_minor minor)
a5f81078 VA	185	{
	186	unsigned int i;
	187	struct drm_info_list *mixer_debugfs_files;
	188	int nb_files;
	189
	190	switch (mixer->id) {
	191	case STI_MIXER_MAIN:
	192	mixer_debugfs_files = mixer0_debugfs_files;
	193	nb_files = ARRAY_SIZE(mixer0_debugfs_files);
	194	break;
	195	case STI_MIXER_AUX:
	196	mixer_debugfs_files = mixer1_debugfs_files;
	197	nb_files = ARRAY_SIZE(mixer1_debugfs_files);
	198	break;
	199	default:
	200	return -EINVAL;
	201	}
	202
	203	for (i = 0; i < nb_files; i++)
	204	mixer_debugfs_files[i].data = mixer;
	205
	206	return drm_debugfs_create_files(mixer_debugfs_files,
	207	nb_files,
	208	minor->debugfs_root, minor);
	209	}
	210
e21e2193 BG	211	void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
	212	{
	213	u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
	214
	215	val &= ~GAM_CTL_BACK_MASK;
	216	val \|= enable;
	217	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
	218	}
	219
	220	static void sti_mixer_set_background_color(struct sti_mixer *mixer,
5260fb5b	221	unsigned int rgb)
e21e2193	222	{
5260fb5b	223	sti_mixer_reg_write(mixer, GAM_MIXER_BKC, rgb);
e21e2193 BG	224	}
	225
	226	static void sti_mixer_set_background_area(struct sti_mixer *mixer,
	227	struct drm_display_mode *mode)
	228	{
	229	u32 ydo, xdo, yds, xds;
	230
	231	ydo = sti_vtg_get_line_number(*mode, 0);
	232	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	233	xdo = sti_vtg_get_pixel_number(*mode, 0);
	234	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
	235
	236	sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 \| xdo);
	237	sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 \| xds);
	238	}
	239
871bcdfe	240	int sti_mixer_set_plane_depth(struct sti_mixer mixer, struct sti_plane plane)
e21e2193	241	{
bbd1e3a5	242	int plane_id, depth = plane->drm_plane.state->normalized_zpos;
bf60b29f	243	unsigned int i;
e21e2193 BG	244	u32 mask, val;
e21e2193 BG	245
871bcdfe	246	switch (plane->desc) {
e21e2193	247	case STI_GDP_0:
871bcdfe	248	plane_id = GAM_DEPTH_GDP0_ID;
e21e2193 BG	249	break;
e21e2193 BG	250	case STI_GDP_1:
871bcdfe	251	plane_id = GAM_DEPTH_GDP1_ID;
e21e2193 BG	252	break;
e21e2193 BG	253	case STI_GDP_2:
871bcdfe	254	plane_id = GAM_DEPTH_GDP2_ID;
e21e2193 BG	255	break;
e21e2193 BG	256	case STI_GDP_3:
871bcdfe	257	plane_id = GAM_DEPTH_GDP3_ID;
e21e2193	258	break;
4fdbc678	259	case STI_HQVDP_0:
871bcdfe	260	plane_id = GAM_DEPTH_VID0_ID;
e21e2193	261	break;
96006a77 BG	262	case STI_CURSOR:
	263	/* no need to set depth for cursor */
	264	return 0;
e21e2193	265	default:
871bcdfe	266	DRM_ERROR("Unknown plane %d\n", plane->desc);
e21e2193 BG	267	return 1;
e21e2193 BG	268	}
bf60b29f	269
871bcdfe	270	/* Search if a previous depth was already assigned to the plane */
bf60b29f VA	271	val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
	272	for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
	273	mask = GAM_DEPTH_MASK_ID << (3 * i);
871bcdfe	274	if ((val & mask) == plane_id << (3 * i))
bf60b29f VA	275	break;
	276	}
	277
bbd1e3a5 BG	278	mask \|= GAM_DEPTH_MASK_ID << (3 * depth);
bbd1e3a5 BG	279	plane_id = plane_id << (3 * depth);
e21e2193	280
d219673d	281	DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
871bcdfe	282	sti_plane_to_str(plane), depth);
e21e2193	283	dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
871bcdfe	284	plane_id, mask);
e21e2193	285
e21e2193	286	val &= ~mask;
871bcdfe	287	val \|= plane_id;
e21e2193 BG	288	sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
	289
	290	dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
	291	sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
	292	return 0;
	293	}
	294
	295	int sti_mixer_active_video_area(struct sti_mixer *mixer,
	296	struct drm_display_mode *mode)
	297	{
	298	u32 ydo, xdo, yds, xds;
	299
	300	ydo = sti_vtg_get_line_number(*mode, 0);
	301	yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
	302	xdo = sti_vtg_get_pixel_number(*mode, 0);
	303	xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
	304
	305	DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
	306	sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
	307	sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 \| xdo);
	308	sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 \| xds);
	309
5260fb5b	310	sti_mixer_set_background_color(mixer, bkg_color);
e21e2193 BG	311
	312	sti_mixer_set_background_area(mixer, mode);
	313	sti_mixer_set_background_status(mixer, true);
	314	return 0;
	315	}
	316
871bcdfe	317	static u32 sti_mixer_get_plane_mask(struct sti_plane *plane)
e21e2193	318	{
871bcdfe	319	switch (plane->desc) {
e21e2193 BG	320	case STI_BACK:
	321	return GAM_CTL_BACK_MASK;
	322	case STI_GDP_0:
	323	return GAM_CTL_GDP0_MASK;
	324	case STI_GDP_1:
	325	return GAM_CTL_GDP1_MASK;
	326	case STI_GDP_2:
	327	return GAM_CTL_GDP2_MASK;
	328	case STI_GDP_3:
	329	return GAM_CTL_GDP3_MASK;
4fdbc678	330	case STI_HQVDP_0:
e21e2193	331	return GAM_CTL_VID0_MASK;
96006a77 BG	332	case STI_CURSOR:
96006a77 BG	333	return GAM_CTL_CURSOR_MASK;
e21e2193 BG	334	default:
	335	return 0;
	336	}
	337	}
	338
871bcdfe VA	339	int sti_mixer_set_plane_status(struct sti_mixer *mixer,
871bcdfe VA	340	struct sti_plane *plane, bool status)
e21e2193 BG	341	{
	342	u32 mask, val;
	343
d219673d	344	DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
871bcdfe	345	sti_mixer_to_str(mixer), sti_plane_to_str(plane));
d219673d	346
871bcdfe	347	mask = sti_mixer_get_plane_mask(plane);
e21e2193	348	if (!mask) {
871bcdfe	349	DRM_ERROR("Can't find layer mask\n");
e21e2193 BG	350	return -EINVAL;
	351	}
	352
	353	val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
	354	val &= ~mask;
	355	val \|= status ? mask : 0;
	356	sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
	357
	358	return 0;
	359	}
	360
	361	void sti_mixer_set_matrix(struct sti_mixer *mixer)
	362	{
	363	unsigned int i;
	364
	365	for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
	366	sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
	367	mixerColorSpaceMatIdentity[i]);
	368	}
	369
a5f81078 VA	370	struct sti_mixer sti_mixer_create(struct device dev,
	371	struct drm_device *drm_dev,
	372	int id,
e21e2193 BG	373	void __iomem *baseaddr)
	374	{
	375	struct sti_mixer mixer = devm_kzalloc(dev, sizeof(mixer), GFP_KERNEL);
	376	struct device_node *np = dev->of_node;
	377
	378	dev_dbg(dev, "%s\n", __func__);
	379	if (!mixer) {
	380	DRM_ERROR("Failed to allocated memory for mixer\n");
	381	return NULL;
	382	}
	383	mixer->regs = baseaddr;
	384	mixer->dev = dev;
	385	mixer->id = id;
	386
	387	if (of_device_is_compatible(np, "st,stih416-compositor"))
	388	sti_mixer_set_matrix(mixer);
	389
	390	DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
	391	sti_mixer_to_str(mixer), mixer->regs);
	392
	393	return mixer;
	394	}