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drm/sti: adapt YUV colorspace in display pipeline
[deliverable/linux.git] / drivers / gpu / drm / sti / sti_tvout.c
CommitLineData
cdfbff78
BG		 1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Vincent Abriou <vincent.abriou@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
7 */
8
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/module.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/reset.h>
15
16#include <drm/drmP.h>
17#include <drm/drm_crtc_helper.h>
18
9e1f05b2 19#include "sti_crtc.h"
503290ce 20#include "sti_vtg.h"
5e03abc5 21
cdfbff78
BG		 22/* glue registers */
23#define TVO_CSC_MAIN_M0 0x000
24#define TVO_CSC_MAIN_M1 0x004
25#define TVO_CSC_MAIN_M2 0x008
26#define TVO_CSC_MAIN_M3 0x00c
27#define TVO_CSC_MAIN_M4 0x010
28#define TVO_CSC_MAIN_M5 0x014
29#define TVO_CSC_MAIN_M6 0x018
30#define TVO_CSC_MAIN_M7 0x01c
31#define TVO_MAIN_IN_VID_FORMAT 0x030
32#define TVO_CSC_AUX_M0 0x100
33#define TVO_CSC_AUX_M1 0x104
34#define TVO_CSC_AUX_M2 0x108
35#define TVO_CSC_AUX_M3 0x10c
36#define TVO_CSC_AUX_M4 0x110
37#define TVO_CSC_AUX_M5 0x114
38#define TVO_CSC_AUX_M6 0x118
39#define TVO_CSC_AUX_M7 0x11c
40#define TVO_AUX_IN_VID_FORMAT 0x130
41#define TVO_VIP_HDF 0x400
42#define TVO_HD_SYNC_SEL 0x418
43#define TVO_HD_DAC_CFG_OFF 0x420
44#define TVO_VIP_HDMI 0x500
45#define TVO_HDMI_FORCE_COLOR_0 0x504
46#define TVO_HDMI_FORCE_COLOR_1 0x508
47#define TVO_HDMI_CLIP_VALUE_B_CB 0x50c
48#define TVO_HDMI_CLIP_VALUE_Y_G 0x510
49#define TVO_HDMI_CLIP_VALUE_R_CR 0x514
50#define TVO_HDMI_SYNC_SEL 0x518
51#define TVO_HDMI_DFV_OBS 0x540
f32c4c50
BG		 52#define TVO_VIP_DVO 0x600
53#define TVO_DVO_SYNC_SEL 0x618
54#define TVO_DVO_CONFIG 0x620
cdfbff78
BG		 55
56#define TVO_IN_FMT_SIGNED BIT(0)
57#define TVO_SYNC_EXT BIT(4)
58
59#define TVO_VIP_REORDER_R_SHIFT 24
60#define TVO_VIP_REORDER_G_SHIFT 20
61#define TVO_VIP_REORDER_B_SHIFT 16
62#define TVO_VIP_REORDER_MASK 0x3
63#define TVO_VIP_REORDER_Y_G_SEL 0
64#define TVO_VIP_REORDER_CB_B_SEL 1
65#define TVO_VIP_REORDER_CR_R_SEL 2
66
67#define TVO_VIP_CLIP_SHIFT 8
68#define TVO_VIP_CLIP_MASK 0x7
69#define TVO_VIP_CLIP_DISABLED 0
70#define TVO_VIP_CLIP_EAV_SAV 1
71#define TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y 2
72#define TVO_VIP_CLIP_LIMITED_RANGE_CB_CR 3
73#define TVO_VIP_CLIP_PROG_RANGE 4
74
75#define TVO_VIP_RND_SHIFT 4
76#define TVO_VIP_RND_MASK 0x3
77#define TVO_VIP_RND_8BIT_ROUNDED 0
78#define TVO_VIP_RND_10BIT_ROUNDED 1
79#define TVO_VIP_RND_12BIT_ROUNDED 2
80
81#define TVO_VIP_SEL_INPUT_MASK 0xf
82#define TVO_VIP_SEL_INPUT_MAIN 0x0
83#define TVO_VIP_SEL_INPUT_AUX 0x8
84#define TVO_VIP_SEL_INPUT_FORCE_COLOR 0xf
85#define TVO_VIP_SEL_INPUT_BYPASS_MASK 0x1
86#define TVO_VIP_SEL_INPUT_BYPASSED 1
87
88#define TVO_SYNC_MAIN_VTG_SET_REF 0x00
cdfbff78 89#define TVO_SYNC_AUX_VTG_SET_REF 0x10
cdfbff78
BG		 90
91#define TVO_SYNC_HD_DCS_SHIFT 8
92
f32c4c50
BG		 93#define TVO_SYNC_DVO_PAD_HSYNC_SHIFT 8
94#define TVO_SYNC_DVO_PAD_VSYNC_SHIFT 16
95
5e03abc5 96#define ENCODER_CRTC_MASK (BIT(0) | BIT(1))
cdfbff78 97
05a142c2
BH		 98#define TVO_MIN_HD_HEIGHT 720
99
cdfbff78
BG		 100/* enum listing the supported output data format */
101enum sti_tvout_video_out_type {
102 STI_TVOUT_VIDEO_OUT_RGB,
103 STI_TVOUT_VIDEO_OUT_YUV,
104};
105
106struct sti_tvout {
107 struct device *dev;
108 struct drm_device *drm_dev;
109 void __iomem *regs;
110 struct reset_control *reset;
111 struct drm_encoder *hdmi;
112 struct drm_encoder *hda;
f32c4c50 113 struct drm_encoder *dvo;
cdfbff78
BG		 114};
115
116struct sti_tvout_encoder {
117 struct drm_encoder encoder;
118 struct sti_tvout *tvout;
119};
120
121#define to_sti_tvout_encoder(x) \
122 container_of(x, struct sti_tvout_encoder, encoder)
123
124#define to_sti_tvout(x) to_sti_tvout_encoder(x)->tvout
125
126/* preformatter conversion matrix */
127static const u32 rgb_to_ycbcr_601[8] = {
128 0xF927082E, 0x04C9FEAB, 0x01D30964, 0xFA95FD3D,
129 0x0000082E, 0x00002000, 0x00002000, 0x00000000
130};
131
132/* 709 RGB to YCbCr */
133static const u32 rgb_to_ycbcr_709[8] = {
134 0xF891082F, 0x0367FF40, 0x01280B71, 0xF9B1FE20,
135 0x0000082F, 0x00002000, 0x00002000, 0x00000000
136};
137
138static u32 tvout_read(struct sti_tvout *tvout, int offset)
139{
140 return readl(tvout->regs + offset);
141}
142
143static void tvout_write(struct sti_tvout *tvout, u32 val, int offset)
144{
145 writel(val, tvout->regs + offset);
146}
147
148/**
149 * Set the clipping mode of a VIP
150 *
151 * @tvout: tvout structure
ca279601 152 * @reg: register to set
cdfbff78
BG		 153 * @cr_r:
154 * @y_g:
155 * @cb_b:
156 */
ca279601 157static void tvout_vip_set_color_order(struct sti_tvout *tvout, int reg,
cdfbff78
BG		 158 u32 cr_r, u32 y_g, u32 cb_b)
159{
ca279601 160 u32 val = tvout_read(tvout, reg);
cdfbff78
BG		 161
162 val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT);
163 val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT);
164 val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT);
165 val |= cr_r << TVO_VIP_REORDER_R_SHIFT;
166 val |= y_g << TVO_VIP_REORDER_G_SHIFT;
167 val |= cb_b << TVO_VIP_REORDER_B_SHIFT;
168
ca279601 169 tvout_write(tvout, val, reg);
cdfbff78
BG		 170}
171
172/**
173 * Set the clipping mode of a VIP
174 *
175 * @tvout: tvout structure
ca279601 176 * @reg: register to set
cdfbff78
BG		 177 * @range: clipping range
178 */
ca279601 179static void tvout_vip_set_clip_mode(struct sti_tvout *tvout, int reg, u32 range)
cdfbff78 180{
ca279601 181 u32 val = tvout_read(tvout, reg);
cdfbff78
BG		 182
183 val &= ~(TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT);
184 val |= range << TVO_VIP_CLIP_SHIFT;
ca279601 185 tvout_write(tvout, val, reg);
cdfbff78
BG		 186}
187
188/**
189 * Set the rounded value of a VIP
190 *
191 * @tvout: tvout structure
ca279601 192 * @reg: register to set
cdfbff78
BG		 193 * @rnd: rounded val per component
194 */
ca279601 195static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd)
cdfbff78 196{
ca279601 197 u32 val = tvout_read(tvout, reg);
cdfbff78
BG		 198
199 val &= ~(TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT);
200 val |= rnd << TVO_VIP_RND_SHIFT;
ca279601 201 tvout_write(tvout, val, reg);
cdfbff78
BG		 202}
203
204/**
205 * Select the VIP input
206 *
207 * @tvout: tvout structure
ca279601
BG		 208 * @reg: register to set
209 * @main_path: main or auxiliary path
210 * @sel_input_logic_inverted: need to invert the logic
cdfbff78
BG		 211 * @sel_input: selected_input (main/aux + conv)
212 */
213static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
ca279601 214 int reg,
cdfbff78
BG		 215 bool main_path,
216 bool sel_input_logic_inverted,
217 enum sti_tvout_video_out_type video_out)
218{
219 u32 sel_input;
ca279601 220 u32 val = tvout_read(tvout, reg);
cdfbff78
BG		 221
222 if (main_path)
223 sel_input = TVO_VIP_SEL_INPUT_MAIN;
224 else
225 sel_input = TVO_VIP_SEL_INPUT_AUX;
226
227 switch (video_out) {
228 case STI_TVOUT_VIDEO_OUT_RGB:
229 sel_input |= TVO_VIP_SEL_INPUT_BYPASSED;
230 break;
231 case STI_TVOUT_VIDEO_OUT_YUV:
232 sel_input &= ~TVO_VIP_SEL_INPUT_BYPASSED;
233 break;
234 }
235
236 /* on stih407 chip the sel_input bypass mode logic is inverted */
237 if (sel_input_logic_inverted)
238 sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
239
240 val &= ~TVO_VIP_SEL_INPUT_MASK;
241 val |= sel_input;
ca279601 242 tvout_write(tvout, val, reg);
cdfbff78
BG		 243}
244
245/**
246 * Select the input video signed or unsigned
247 *
248 * @tvout: tvout structure
ca279601 249 * @reg: register to set
cdfbff78
BG		 250 * @in_vid_signed: used video input format
251 */
ca279601
BG		 252static void tvout_vip_set_in_vid_fmt(struct sti_tvout *tvout,
253 int reg, u32 in_vid_fmt)
cdfbff78 254{
ca279601 255 u32 val = tvout_read(tvout, reg);
cdfbff78
BG		 256
257 val &= ~TVO_IN_FMT_SIGNED;
258 val |= in_vid_fmt;
ca279601 259 tvout_write(tvout, val, reg);
cdfbff78
BG		 260}
261
05a142c2
BH		 262/**
263 * Set preformatter matrix
264 *
265 * @tvout: tvout structure
266 * @mode: display mode structure
267 */
268static void tvout_preformatter_set_matrix(struct sti_tvout *tvout,
269 struct drm_display_mode *mode)
270{
271 unsigned int i;
272 const u32 *pf_matrix;
273
274 if (mode->vdisplay >= TVO_MIN_HD_HEIGHT)
275 pf_matrix = rgb_to_ycbcr_709;
276 else
277 pf_matrix = rgb_to_ycbcr_601;
278
279 for (i = 0; i < 8; i++) {
280 tvout_write(tvout, *(pf_matrix + i),
281 TVO_CSC_MAIN_M0 + (i * 4));
282 tvout_write(tvout, *(pf_matrix + i),
283 TVO_CSC_AUX_M0 + (i * 4));
284 }
285}
286
f32c4c50
BG		 287/**
288 * Start VIP block for DVO output
289 *
290 * @tvout: pointer on tvout structure
291 * @main_path: true if main path has to be used in the vip configuration
292 * else aux path is used.
293 */
294static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
295{
296 struct device_node *node = tvout->dev->of_node;
297 bool sel_input_logic_inverted = false;
298 u32 tvo_in_vid_format;
503290ce 299 int val, tmp;
f32c4c50
BG		 300
301 dev_dbg(tvout->dev, "%s\n", __func__);
302
303 if (main_path) {
304 DRM_DEBUG_DRIVER("main vip for DVO\n");
503290ce
VA		 305 /* Select the input sync for dvo */
306 tmp = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_DVO;
307 val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT;
308 val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT;
309 val |= tmp;
f32c4c50
BG		 310 tvout_write(tvout, val, TVO_DVO_SYNC_SEL);
311 tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
312 } else {
313 DRM_DEBUG_DRIVER("aux vip for DVO\n");
503290ce
VA		 314 /* Select the input sync for dvo */
315 tmp = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_DVO;
316 val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT;
317 val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT;
318 val |= tmp;
f32c4c50
BG		 319 tvout_write(tvout, val, TVO_DVO_SYNC_SEL);
320 tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
321 }
322
323 /* Set color channel order */
324 tvout_vip_set_color_order(tvout, TVO_VIP_DVO,
325 TVO_VIP_REORDER_CR_R_SEL,
326 TVO_VIP_REORDER_Y_G_SEL,
327 TVO_VIP_REORDER_CB_B_SEL);
328
329 /* Set clipping mode (Limited range RGB/Y) */
330 tvout_vip_set_clip_mode(tvout, TVO_VIP_DVO,
331 TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y);
332
333 /* Set round mode (rounded to 8-bit per component) */
334 tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED);
335
336 if (of_device_is_compatible(node, "st,stih407-tvout")) {
337 /* Set input video format */
338 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
339 TVO_IN_FMT_SIGNED);
340 sel_input_logic_inverted = true;
341 }
342
343 /* Input selection */
344 tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path,
345 sel_input_logic_inverted,
346 STI_TVOUT_VIDEO_OUT_RGB);
347}
348
cdfbff78
BG		 349/**
350 * Start VIP block for HDMI output
351 *
352 * @tvout: pointer on tvout structure
353 * @main_path: true if main path has to be used in the vip configuration
354 * else aux path is used.
355 */
356static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
357{
358 struct device_node *node = tvout->dev->of_node;
359 bool sel_input_logic_inverted = false;
ca279601 360 u32 tvo_in_vid_format;
cdfbff78
BG		 361
362 dev_dbg(tvout->dev, "%s\n", __func__);
363
364 if (main_path) {
365 DRM_DEBUG_DRIVER("main vip for hdmi\n");
503290ce
VA		 366 /* select the input sync for hdmi */
367 tvout_write(tvout,
368 TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDMI,
369 TVO_HDMI_SYNC_SEL);
ca279601 370 tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
cdfbff78
BG		 371 } else {
372 DRM_DEBUG_DRIVER("aux vip for hdmi\n");
503290ce
VA		 373 /* select the input sync for hdmi */
374 tvout_write(tvout,
375 TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDMI,
376 TVO_HDMI_SYNC_SEL);
ca279601 377 tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
cdfbff78
BG		 378 }
379
380 /* set color channel order */
ca279601 381 tvout_vip_set_color_order(tvout, TVO_VIP_HDMI,
cdfbff78
BG		 382 TVO_VIP_REORDER_CR_R_SEL,
383 TVO_VIP_REORDER_Y_G_SEL,
384 TVO_VIP_REORDER_CB_B_SEL);
385
386 /* set clipping mode (Limited range RGB/Y) */
ca279601
BG		 387 tvout_vip_set_clip_mode(tvout, TVO_VIP_HDMI,
388 TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y);
cdfbff78
BG		 389
390 /* set round mode (rounded to 8-bit per component) */
ca279601 391 tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED);
cdfbff78
BG		 392
393 if (of_device_is_compatible(node, "st,stih407-tvout")) {
394 /* set input video format */
ca279601
BG		 395 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
396 TVO_IN_FMT_SIGNED);
cdfbff78
BG		 397 sel_input_logic_inverted = true;
398 }
399
400 /* input selection */
ca279601 401 tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path,
cdfbff78
BG		 402 sel_input_logic_inverted, STI_TVOUT_VIDEO_OUT_RGB);
403}
404
405/**
406 * Start HDF VIP and HD DAC
407 *
408 * @tvout: pointer on tvout structure
409 * @main_path: true if main path has to be used in the vip configuration
410 * else aux path is used.
411 */
412static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
413{
414 struct device_node *node = tvout->dev->of_node;
415 bool sel_input_logic_inverted = false;
ca279601
BG		 416 u32 tvo_in_vid_format;
417 int val;
cdfbff78
BG		 418
419 dev_dbg(tvout->dev, "%s\n", __func__);
420
ca279601 421 if (main_path) {
503290ce
VA		 422 DRM_DEBUG_DRIVER("main vip for HDF\n");
423 /* Select the input sync for HD analog and HD DCS */
424 val = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDDCS;
425 val = val << TVO_SYNC_HD_DCS_SHIFT;
426 val |= TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDF;
ca279601
BG		 427 tvout_write(tvout, val, TVO_HD_SYNC_SEL);
428 tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
429 } else {
503290ce
VA		 430 DRM_DEBUG_DRIVER("aux vip for HDF\n");
431 /* Select the input sync for HD analog and HD DCS */
432 val = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDDCS;
433 val = val << TVO_SYNC_HD_DCS_SHIFT;
434 val |= TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDF;
ca279601
BG		 435 tvout_write(tvout, val, TVO_HD_SYNC_SEL);
436 tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
cdfbff78
BG		 437 }
438
cdfbff78 439 /* set color channel order */
ca279601 440 tvout_vip_set_color_order(tvout, TVO_VIP_HDF,
cdfbff78
BG		 441 TVO_VIP_REORDER_CR_R_SEL,
442 TVO_VIP_REORDER_Y_G_SEL,
443 TVO_VIP_REORDER_CB_B_SEL);
444
ca279601
BG		 445 /* set clipping mode (EAV/SAV clipping) */
446 tvout_vip_set_clip_mode(tvout, TVO_VIP_HDF, TVO_VIP_CLIP_EAV_SAV);
cdfbff78
BG		 447
448 /* set round mode (rounded to 10-bit per component) */
ca279601 449 tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED);
cdfbff78
BG		 450
451 if (of_device_is_compatible(node, "st,stih407-tvout")) {
452 /* set input video format */
ca279601
BG		 453 tvout_vip_set_in_vid_fmt(tvout,
454 tvo_in_vid_format, TVO_IN_FMT_SIGNED);
cdfbff78
BG		 455 sel_input_logic_inverted = true;
456 }
457
458 /* Input selection */
ca279601 459 tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path,
cdfbff78
BG		 460 sel_input_logic_inverted,
461 STI_TVOUT_VIDEO_OUT_YUV);
462
cdfbff78
BG		 463 /* power up HD DAC */
464 tvout_write(tvout, 0, TVO_HD_DAC_CFG_OFF);
465}
466
467static void sti_tvout_encoder_dpms(struct drm_encoder *encoder, int mode)
468{
469}
470
cdfbff78
BG		 471static void sti_tvout_encoder_mode_set(struct drm_encoder *encoder,
472 struct drm_display_mode *mode,
473 struct drm_display_mode *adjusted_mode)
474{
475}
476
cdfbff78
BG		 477static void sti_tvout_encoder_destroy(struct drm_encoder *encoder)
478{
479 struct sti_tvout_encoder *sti_encoder = to_sti_tvout_encoder(encoder);
480
481 drm_encoder_cleanup(encoder);
482 kfree(sti_encoder);
483}
484
485static const struct drm_encoder_funcs sti_tvout_encoder_funcs = {
486 .destroy = sti_tvout_encoder_destroy,
487};
488
05a142c2 489static void sti_dvo_encoder_enable(struct drm_encoder *encoder)
f32c4c50
BG		 490{
491 struct sti_tvout *tvout = to_sti_tvout(encoder);
492
05a142c2
BH		 493 tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode);
494
9e1f05b2 495 tvout_dvo_start(tvout, sti_crtc_is_main(encoder->crtc));
f32c4c50
BG		 496}
497
498static void sti_dvo_encoder_disable(struct drm_encoder *encoder)
499{
500 struct sti_tvout *tvout = to_sti_tvout(encoder);
501
502 /* Reset VIP register */
503 tvout_write(tvout, 0x0, TVO_VIP_DVO);
504}
505
506static const struct drm_encoder_helper_funcs sti_dvo_encoder_helper_funcs = {
507 .dpms = sti_tvout_encoder_dpms,
f32c4c50 508 .mode_set = sti_tvout_encoder_mode_set,
05a142c2 509 .enable = sti_dvo_encoder_enable,
f32c4c50
BG		 510 .disable = sti_dvo_encoder_disable,
511};
512
513static struct drm_encoder *
514sti_tvout_create_dvo_encoder(struct drm_device *dev,
515 struct sti_tvout *tvout)
516{
517 struct sti_tvout_encoder *encoder;
518 struct drm_encoder *drm_encoder;
519
520 encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
521 if (!encoder)
522 return NULL;
523
524 encoder->tvout = tvout;
525
526 drm_encoder = (struct drm_encoder *)encoder;
527
528 drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
529 drm_encoder->possible_clones = 1 << 0;
530
531 drm_encoder_init(dev, drm_encoder,
13a3d91f
VS		 532 &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_LVDS,
533 NULL);
f32c4c50
BG		 534
535 drm_encoder_helper_add(drm_encoder, &sti_dvo_encoder_helper_funcs);
536
537 return drm_encoder;
538}
539
05a142c2 540static void sti_hda_encoder_enable(struct drm_encoder *encoder)
cdfbff78
BG		 541{
542 struct sti_tvout *tvout = to_sti_tvout(encoder);
543
05a142c2
BH		 544 tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode);
545
9e1f05b2 546 tvout_hda_start(tvout, sti_crtc_is_main(encoder->crtc));
cdfbff78
BG		 547}
548
549static void sti_hda_encoder_disable(struct drm_encoder *encoder)
550{
551 struct sti_tvout *tvout = to_sti_tvout(encoder);
552
553 /* reset VIP register */
554 tvout_write(tvout, 0x0, TVO_VIP_HDF);
555
556 /* power down HD DAC */
557 tvout_write(tvout, 1, TVO_HD_DAC_CFG_OFF);
558}
559
560static const struct drm_encoder_helper_funcs sti_hda_encoder_helper_funcs = {
561 .dpms = sti_tvout_encoder_dpms,
cdfbff78 562 .mode_set = sti_tvout_encoder_mode_set,
05a142c2 563 .commit = sti_hda_encoder_enable,
cdfbff78
BG		 564 .disable = sti_hda_encoder_disable,
565};
566
567static struct drm_encoder *sti_tvout_create_hda_encoder(struct drm_device *dev,
568 struct sti_tvout *tvout)
569{
570 struct sti_tvout_encoder *encoder;
571 struct drm_encoder *drm_encoder;
572
573 encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
574 if (!encoder)
575 return NULL;
576
577 encoder->tvout = tvout;
578
579 drm_encoder = (struct drm_encoder *) encoder;
580
5e03abc5 581 drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
cdfbff78
BG		 582 drm_encoder->possible_clones = 1 << 0;
583
584 drm_encoder_init(dev, drm_encoder,
13a3d91f 585 &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL);
cdfbff78
BG		 586
587 drm_encoder_helper_add(drm_encoder, &sti_hda_encoder_helper_funcs);
588
589 return drm_encoder;
590}
591
05a142c2 592static void sti_hdmi_encoder_enable(struct drm_encoder *encoder)
cdfbff78
BG		 593{
594 struct sti_tvout *tvout = to_sti_tvout(encoder);
595
05a142c2
BH		 596 tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode);
597
9e1f05b2 598 tvout_hdmi_start(tvout, sti_crtc_is_main(encoder->crtc));
cdfbff78
BG		 599}
600
601static void sti_hdmi_encoder_disable(struct drm_encoder *encoder)
602{
603 struct sti_tvout *tvout = to_sti_tvout(encoder);
604
605 /* reset VIP register */
606 tvout_write(tvout, 0x0, TVO_VIP_HDMI);
607}
608
609static const struct drm_encoder_helper_funcs sti_hdmi_encoder_helper_funcs = {
610 .dpms = sti_tvout_encoder_dpms,
cdfbff78 611 .mode_set = sti_tvout_encoder_mode_set,
05a142c2 612 .commit = sti_hdmi_encoder_enable,
cdfbff78
BG		 613 .disable = sti_hdmi_encoder_disable,
614};
615
616static struct drm_encoder *sti_tvout_create_hdmi_encoder(struct drm_device *dev,
617 struct sti_tvout *tvout)
618{
619 struct sti_tvout_encoder *encoder;
620 struct drm_encoder *drm_encoder;
621
622 encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
623 if (!encoder)
624 return NULL;
625
626 encoder->tvout = tvout;
627
628 drm_encoder = (struct drm_encoder *) encoder;
629
5e03abc5 630 drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
cdfbff78
BG		 631 drm_encoder->possible_clones = 1 << 1;
632
633 drm_encoder_init(dev, drm_encoder,
13a3d91f 634 &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL);
cdfbff78
BG		 635
636 drm_encoder_helper_add(drm_encoder, &sti_hdmi_encoder_helper_funcs);
637
638 return drm_encoder;
639}
640
641static void sti_tvout_create_encoders(struct drm_device *dev,
642 struct sti_tvout *tvout)
643{
644 tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout);
645 tvout->hda = sti_tvout_create_hda_encoder(dev, tvout);
f32c4c50 646 tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout);
cdfbff78
BG		 647}
648
649static void sti_tvout_destroy_encoders(struct sti_tvout *tvout)
650{
651 if (tvout->hdmi)
652 drm_encoder_cleanup(tvout->hdmi);
653 tvout->hdmi = NULL;
654
655 if (tvout->hda)
656 drm_encoder_cleanup(tvout->hda);
657 tvout->hda = NULL;
658}
659
660static int sti_tvout_bind(struct device *dev, struct device *master, void *data)
661{
662 struct sti_tvout *tvout = dev_get_drvdata(dev);
663 struct drm_device *drm_dev = data;
cdfbff78
BG		 664
665 tvout->drm_dev = drm_dev;
666
cdfbff78
BG		 667 sti_tvout_create_encoders(drm_dev, tvout);
668
53bdcf5f 669 return 0;
cdfbff78
BG		 670}
671
672static void sti_tvout_unbind(struct device *dev, struct device *master,
673 void *data)
674{
53bdcf5f
BG		 675 struct sti_tvout *tvout = dev_get_drvdata(dev);
676
677 sti_tvout_destroy_encoders(tvout);
cdfbff78
BG		 678}
679
680static const struct component_ops sti_tvout_ops = {
681 .bind = sti_tvout_bind,
682 .unbind = sti_tvout_unbind,
683};
684
cdfbff78
BG		 685static int sti_tvout_probe(struct platform_device *pdev)
686{
687 struct device *dev = &pdev->dev;
688 struct device_node *node = dev->of_node;
689 struct sti_tvout *tvout;
690 struct resource *res;
cdfbff78
BG		 691
692 DRM_INFO("%s\n", __func__);
693
694 if (!node)
695 return -ENODEV;
696
697 tvout = devm_kzalloc(dev, sizeof(*tvout), GFP_KERNEL);
698 if (!tvout)
699 return -ENOMEM;
700
701 tvout->dev = dev;
702
703 /* get Memory ressources */
704 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg");
705 if (!res) {
706 DRM_ERROR("Invalid glue resource\n");
707 return -ENOMEM;
708 }
709 tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
31f32a21
WY		 710 if (!tvout->regs)
711 return -ENOMEM;
cdfbff78
BG		 712
713 /* get reset resources */
714 tvout->reset = devm_reset_control_get(dev, "tvout");
715 /* take tvout out of reset */
716 if (!IS_ERR(tvout->reset))
717 reset_control_deassert(tvout->reset);
718
719 platform_set_drvdata(pdev, tvout);
720
cdfbff78
BG		 721 return component_add(dev, &sti_tvout_ops);
722}
723
724static int sti_tvout_remove(struct platform_device *pdev)
725{
cdfbff78
BG		 726 component_del(&pdev->dev, &sti_tvout_ops);
727 return 0;
728}
729
8e932cf0 730static const struct of_device_id tvout_of_match[] = {
cdfbff78
BG		 731 { .compatible = "st,stih416-tvout", },
732 { .compatible = "st,stih407-tvout", },
733 { /* end node */ }
734};
735MODULE_DEVICE_TABLE(of, tvout_of_match);
736
737struct platform_driver sti_tvout_driver = {
738 .driver = {
739 .name = "sti-tvout",
740 .owner = THIS_MODULE,
741 .of_match_table = tvout_of_match,
742 },
743 .probe = sti_tvout_probe,
744 .remove = sti_tvout_remove,
745};
746
cdfbff78
BG		 747MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
748MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
749MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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