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cdfbff78 BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> | |
4 | * Vincent Abriou <vincent.abriou@st.com> | |
5 | * for STMicroelectronics. | |
6 | * License terms: GNU General Public License (GPL), version 2 | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/component.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_platform.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/reset.h> | |
15 | ||
16 | #include <drm/drmP.h> | |
17 | #include <drm/drm_crtc_helper.h> | |
18 | ||
9e1f05b2 | 19 | #include "sti_crtc.h" |
503290ce | 20 | #include "sti_vtg.h" |
5e03abc5 | 21 | |
cdfbff78 BG |
22 | /* glue registers */ |
23 | #define TVO_CSC_MAIN_M0 0x000 | |
24 | #define TVO_CSC_MAIN_M1 0x004 | |
25 | #define TVO_CSC_MAIN_M2 0x008 | |
26 | #define TVO_CSC_MAIN_M3 0x00c | |
27 | #define TVO_CSC_MAIN_M4 0x010 | |
28 | #define TVO_CSC_MAIN_M5 0x014 | |
29 | #define TVO_CSC_MAIN_M6 0x018 | |
30 | #define TVO_CSC_MAIN_M7 0x01c | |
31 | #define TVO_MAIN_IN_VID_FORMAT 0x030 | |
32 | #define TVO_CSC_AUX_M0 0x100 | |
33 | #define TVO_CSC_AUX_M1 0x104 | |
34 | #define TVO_CSC_AUX_M2 0x108 | |
35 | #define TVO_CSC_AUX_M3 0x10c | |
36 | #define TVO_CSC_AUX_M4 0x110 | |
37 | #define TVO_CSC_AUX_M5 0x114 | |
38 | #define TVO_CSC_AUX_M6 0x118 | |
39 | #define TVO_CSC_AUX_M7 0x11c | |
40 | #define TVO_AUX_IN_VID_FORMAT 0x130 | |
41 | #define TVO_VIP_HDF 0x400 | |
42 | #define TVO_HD_SYNC_SEL 0x418 | |
43 | #define TVO_HD_DAC_CFG_OFF 0x420 | |
44 | #define TVO_VIP_HDMI 0x500 | |
45 | #define TVO_HDMI_FORCE_COLOR_0 0x504 | |
46 | #define TVO_HDMI_FORCE_COLOR_1 0x508 | |
47 | #define TVO_HDMI_CLIP_VALUE_B_CB 0x50c | |
48 | #define TVO_HDMI_CLIP_VALUE_Y_G 0x510 | |
49 | #define TVO_HDMI_CLIP_VALUE_R_CR 0x514 | |
50 | #define TVO_HDMI_SYNC_SEL 0x518 | |
51 | #define TVO_HDMI_DFV_OBS 0x540 | |
f32c4c50 BG |
52 | #define TVO_VIP_DVO 0x600 |
53 | #define TVO_DVO_SYNC_SEL 0x618 | |
54 | #define TVO_DVO_CONFIG 0x620 | |
cdfbff78 BG |
55 | |
56 | #define TVO_IN_FMT_SIGNED BIT(0) | |
57 | #define TVO_SYNC_EXT BIT(4) | |
58 | ||
59 | #define TVO_VIP_REORDER_R_SHIFT 24 | |
60 | #define TVO_VIP_REORDER_G_SHIFT 20 | |
61 | #define TVO_VIP_REORDER_B_SHIFT 16 | |
62 | #define TVO_VIP_REORDER_MASK 0x3 | |
63 | #define TVO_VIP_REORDER_Y_G_SEL 0 | |
64 | #define TVO_VIP_REORDER_CB_B_SEL 1 | |
65 | #define TVO_VIP_REORDER_CR_R_SEL 2 | |
66 | ||
67 | #define TVO_VIP_CLIP_SHIFT 8 | |
68 | #define TVO_VIP_CLIP_MASK 0x7 | |
69 | #define TVO_VIP_CLIP_DISABLED 0 | |
70 | #define TVO_VIP_CLIP_EAV_SAV 1 | |
71 | #define TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y 2 | |
72 | #define TVO_VIP_CLIP_LIMITED_RANGE_CB_CR 3 | |
73 | #define TVO_VIP_CLIP_PROG_RANGE 4 | |
74 | ||
75 | #define TVO_VIP_RND_SHIFT 4 | |
76 | #define TVO_VIP_RND_MASK 0x3 | |
77 | #define TVO_VIP_RND_8BIT_ROUNDED 0 | |
78 | #define TVO_VIP_RND_10BIT_ROUNDED 1 | |
79 | #define TVO_VIP_RND_12BIT_ROUNDED 2 | |
80 | ||
81 | #define TVO_VIP_SEL_INPUT_MASK 0xf | |
82 | #define TVO_VIP_SEL_INPUT_MAIN 0x0 | |
83 | #define TVO_VIP_SEL_INPUT_AUX 0x8 | |
84 | #define TVO_VIP_SEL_INPUT_FORCE_COLOR 0xf | |
85 | #define TVO_VIP_SEL_INPUT_BYPASS_MASK 0x1 | |
86 | #define TVO_VIP_SEL_INPUT_BYPASSED 1 | |
87 | ||
88 | #define TVO_SYNC_MAIN_VTG_SET_REF 0x00 | |
cdfbff78 | 89 | #define TVO_SYNC_AUX_VTG_SET_REF 0x10 |
cdfbff78 BG |
90 | |
91 | #define TVO_SYNC_HD_DCS_SHIFT 8 | |
92 | ||
f32c4c50 BG |
93 | #define TVO_SYNC_DVO_PAD_HSYNC_SHIFT 8 |
94 | #define TVO_SYNC_DVO_PAD_VSYNC_SHIFT 16 | |
95 | ||
5e03abc5 | 96 | #define ENCODER_CRTC_MASK (BIT(0) | BIT(1)) |
cdfbff78 | 97 | |
05a142c2 BH |
98 | #define TVO_MIN_HD_HEIGHT 720 |
99 | ||
cdfbff78 BG |
100 | /* enum listing the supported output data format */ |
101 | enum sti_tvout_video_out_type { | |
102 | STI_TVOUT_VIDEO_OUT_RGB, | |
103 | STI_TVOUT_VIDEO_OUT_YUV, | |
104 | }; | |
105 | ||
106 | struct sti_tvout { | |
107 | struct device *dev; | |
108 | struct drm_device *drm_dev; | |
109 | void __iomem *regs; | |
110 | struct reset_control *reset; | |
111 | struct drm_encoder *hdmi; | |
112 | struct drm_encoder *hda; | |
f32c4c50 | 113 | struct drm_encoder *dvo; |
cdfbff78 BG |
114 | }; |
115 | ||
116 | struct sti_tvout_encoder { | |
117 | struct drm_encoder encoder; | |
118 | struct sti_tvout *tvout; | |
119 | }; | |
120 | ||
121 | #define to_sti_tvout_encoder(x) \ | |
122 | container_of(x, struct sti_tvout_encoder, encoder) | |
123 | ||
124 | #define to_sti_tvout(x) to_sti_tvout_encoder(x)->tvout | |
125 | ||
126 | /* preformatter conversion matrix */ | |
127 | static const u32 rgb_to_ycbcr_601[8] = { | |
128 | 0xF927082E, 0x04C9FEAB, 0x01D30964, 0xFA95FD3D, | |
129 | 0x0000082E, 0x00002000, 0x00002000, 0x00000000 | |
130 | }; | |
131 | ||
132 | /* 709 RGB to YCbCr */ | |
133 | static const u32 rgb_to_ycbcr_709[8] = { | |
134 | 0xF891082F, 0x0367FF40, 0x01280B71, 0xF9B1FE20, | |
135 | 0x0000082F, 0x00002000, 0x00002000, 0x00000000 | |
136 | }; | |
137 | ||
138 | static u32 tvout_read(struct sti_tvout *tvout, int offset) | |
139 | { | |
140 | return readl(tvout->regs + offset); | |
141 | } | |
142 | ||
143 | static void tvout_write(struct sti_tvout *tvout, u32 val, int offset) | |
144 | { | |
145 | writel(val, tvout->regs + offset); | |
146 | } | |
147 | ||
148 | /** | |
149 | * Set the clipping mode of a VIP | |
150 | * | |
151 | * @tvout: tvout structure | |
ca279601 | 152 | * @reg: register to set |
cdfbff78 BG |
153 | * @cr_r: |
154 | * @y_g: | |
155 | * @cb_b: | |
156 | */ | |
ca279601 | 157 | static void tvout_vip_set_color_order(struct sti_tvout *tvout, int reg, |
cdfbff78 BG |
158 | u32 cr_r, u32 y_g, u32 cb_b) |
159 | { | |
ca279601 | 160 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
161 | |
162 | val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT); | |
163 | val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT); | |
164 | val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT); | |
165 | val |= cr_r << TVO_VIP_REORDER_R_SHIFT; | |
166 | val |= y_g << TVO_VIP_REORDER_G_SHIFT; | |
167 | val |= cb_b << TVO_VIP_REORDER_B_SHIFT; | |
168 | ||
ca279601 | 169 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
170 | } |
171 | ||
172 | /** | |
173 | * Set the clipping mode of a VIP | |
174 | * | |
175 | * @tvout: tvout structure | |
ca279601 | 176 | * @reg: register to set |
cdfbff78 BG |
177 | * @range: clipping range |
178 | */ | |
ca279601 | 179 | static void tvout_vip_set_clip_mode(struct sti_tvout *tvout, int reg, u32 range) |
cdfbff78 | 180 | { |
ca279601 | 181 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
182 | |
183 | val &= ~(TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT); | |
184 | val |= range << TVO_VIP_CLIP_SHIFT; | |
ca279601 | 185 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
186 | } |
187 | ||
188 | /** | |
189 | * Set the rounded value of a VIP | |
190 | * | |
191 | * @tvout: tvout structure | |
ca279601 | 192 | * @reg: register to set |
cdfbff78 BG |
193 | * @rnd: rounded val per component |
194 | */ | |
ca279601 | 195 | static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd) |
cdfbff78 | 196 | { |
ca279601 | 197 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
198 | |
199 | val &= ~(TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT); | |
200 | val |= rnd << TVO_VIP_RND_SHIFT; | |
ca279601 | 201 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
202 | } |
203 | ||
204 | /** | |
205 | * Select the VIP input | |
206 | * | |
207 | * @tvout: tvout structure | |
ca279601 BG |
208 | * @reg: register to set |
209 | * @main_path: main or auxiliary path | |
210 | * @sel_input_logic_inverted: need to invert the logic | |
cdfbff78 BG |
211 | * @sel_input: selected_input (main/aux + conv) |
212 | */ | |
213 | static void tvout_vip_set_sel_input(struct sti_tvout *tvout, | |
ca279601 | 214 | int reg, |
cdfbff78 BG |
215 | bool main_path, |
216 | bool sel_input_logic_inverted, | |
217 | enum sti_tvout_video_out_type video_out) | |
218 | { | |
219 | u32 sel_input; | |
ca279601 | 220 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
221 | |
222 | if (main_path) | |
223 | sel_input = TVO_VIP_SEL_INPUT_MAIN; | |
224 | else | |
225 | sel_input = TVO_VIP_SEL_INPUT_AUX; | |
226 | ||
227 | switch (video_out) { | |
228 | case STI_TVOUT_VIDEO_OUT_RGB: | |
229 | sel_input |= TVO_VIP_SEL_INPUT_BYPASSED; | |
230 | break; | |
231 | case STI_TVOUT_VIDEO_OUT_YUV: | |
232 | sel_input &= ~TVO_VIP_SEL_INPUT_BYPASSED; | |
233 | break; | |
234 | } | |
235 | ||
236 | /* on stih407 chip the sel_input bypass mode logic is inverted */ | |
237 | if (sel_input_logic_inverted) | |
238 | sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK; | |
239 | ||
240 | val &= ~TVO_VIP_SEL_INPUT_MASK; | |
241 | val |= sel_input; | |
ca279601 | 242 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
243 | } |
244 | ||
245 | /** | |
246 | * Select the input video signed or unsigned | |
247 | * | |
248 | * @tvout: tvout structure | |
ca279601 | 249 | * @reg: register to set |
cdfbff78 BG |
250 | * @in_vid_signed: used video input format |
251 | */ | |
ca279601 BG |
252 | static void tvout_vip_set_in_vid_fmt(struct sti_tvout *tvout, |
253 | int reg, u32 in_vid_fmt) | |
cdfbff78 | 254 | { |
ca279601 | 255 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
256 | |
257 | val &= ~TVO_IN_FMT_SIGNED; | |
258 | val |= in_vid_fmt; | |
ca279601 | 259 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
260 | } |
261 | ||
05a142c2 BH |
262 | /** |
263 | * Set preformatter matrix | |
264 | * | |
265 | * @tvout: tvout structure | |
266 | * @mode: display mode structure | |
267 | */ | |
268 | static void tvout_preformatter_set_matrix(struct sti_tvout *tvout, | |
269 | struct drm_display_mode *mode) | |
270 | { | |
271 | unsigned int i; | |
272 | const u32 *pf_matrix; | |
273 | ||
274 | if (mode->vdisplay >= TVO_MIN_HD_HEIGHT) | |
275 | pf_matrix = rgb_to_ycbcr_709; | |
276 | else | |
277 | pf_matrix = rgb_to_ycbcr_601; | |
278 | ||
279 | for (i = 0; i < 8; i++) { | |
280 | tvout_write(tvout, *(pf_matrix + i), | |
281 | TVO_CSC_MAIN_M0 + (i * 4)); | |
282 | tvout_write(tvout, *(pf_matrix + i), | |
283 | TVO_CSC_AUX_M0 + (i * 4)); | |
284 | } | |
285 | } | |
286 | ||
f32c4c50 BG |
287 | /** |
288 | * Start VIP block for DVO output | |
289 | * | |
290 | * @tvout: pointer on tvout structure | |
291 | * @main_path: true if main path has to be used in the vip configuration | |
292 | * else aux path is used. | |
293 | */ | |
294 | static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path) | |
295 | { | |
296 | struct device_node *node = tvout->dev->of_node; | |
297 | bool sel_input_logic_inverted = false; | |
298 | u32 tvo_in_vid_format; | |
503290ce | 299 | int val, tmp; |
f32c4c50 BG |
300 | |
301 | dev_dbg(tvout->dev, "%s\n", __func__); | |
302 | ||
303 | if (main_path) { | |
304 | DRM_DEBUG_DRIVER("main vip for DVO\n"); | |
503290ce VA |
305 | /* Select the input sync for dvo */ |
306 | tmp = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_DVO; | |
307 | val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; | |
308 | val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; | |
309 | val |= tmp; | |
f32c4c50 BG |
310 | tvout_write(tvout, val, TVO_DVO_SYNC_SEL); |
311 | tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; | |
312 | } else { | |
313 | DRM_DEBUG_DRIVER("aux vip for DVO\n"); | |
503290ce VA |
314 | /* Select the input sync for dvo */ |
315 | tmp = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_DVO; | |
316 | val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; | |
317 | val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; | |
318 | val |= tmp; | |
f32c4c50 BG |
319 | tvout_write(tvout, val, TVO_DVO_SYNC_SEL); |
320 | tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; | |
321 | } | |
322 | ||
323 | /* Set color channel order */ | |
324 | tvout_vip_set_color_order(tvout, TVO_VIP_DVO, | |
325 | TVO_VIP_REORDER_CR_R_SEL, | |
326 | TVO_VIP_REORDER_Y_G_SEL, | |
327 | TVO_VIP_REORDER_CB_B_SEL); | |
328 | ||
1834b84d VA |
329 | /* Set clipping mode */ |
330 | tvout_vip_set_clip_mode(tvout, TVO_VIP_DVO, TVO_VIP_CLIP_DISABLED); | |
f32c4c50 BG |
331 | |
332 | /* Set round mode (rounded to 8-bit per component) */ | |
333 | tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED); | |
334 | ||
335 | if (of_device_is_compatible(node, "st,stih407-tvout")) { | |
336 | /* Set input video format */ | |
337 | tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, | |
338 | TVO_IN_FMT_SIGNED); | |
339 | sel_input_logic_inverted = true; | |
340 | } | |
341 | ||
342 | /* Input selection */ | |
343 | tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path, | |
344 | sel_input_logic_inverted, | |
345 | STI_TVOUT_VIDEO_OUT_RGB); | |
346 | } | |
347 | ||
cdfbff78 BG |
348 | /** |
349 | * Start VIP block for HDMI output | |
350 | * | |
351 | * @tvout: pointer on tvout structure | |
352 | * @main_path: true if main path has to be used in the vip configuration | |
353 | * else aux path is used. | |
354 | */ | |
355 | static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path) | |
356 | { | |
357 | struct device_node *node = tvout->dev->of_node; | |
358 | bool sel_input_logic_inverted = false; | |
ca279601 | 359 | u32 tvo_in_vid_format; |
cdfbff78 BG |
360 | |
361 | dev_dbg(tvout->dev, "%s\n", __func__); | |
362 | ||
363 | if (main_path) { | |
364 | DRM_DEBUG_DRIVER("main vip for hdmi\n"); | |
503290ce VA |
365 | /* select the input sync for hdmi */ |
366 | tvout_write(tvout, | |
367 | TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDMI, | |
368 | TVO_HDMI_SYNC_SEL); | |
ca279601 | 369 | tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; |
cdfbff78 BG |
370 | } else { |
371 | DRM_DEBUG_DRIVER("aux vip for hdmi\n"); | |
503290ce VA |
372 | /* select the input sync for hdmi */ |
373 | tvout_write(tvout, | |
374 | TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDMI, | |
375 | TVO_HDMI_SYNC_SEL); | |
ca279601 | 376 | tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; |
cdfbff78 BG |
377 | } |
378 | ||
379 | /* set color channel order */ | |
ca279601 | 380 | tvout_vip_set_color_order(tvout, TVO_VIP_HDMI, |
cdfbff78 BG |
381 | TVO_VIP_REORDER_CR_R_SEL, |
382 | TVO_VIP_REORDER_Y_G_SEL, | |
383 | TVO_VIP_REORDER_CB_B_SEL); | |
384 | ||
1834b84d VA |
385 | /* set clipping mode */ |
386 | tvout_vip_set_clip_mode(tvout, TVO_VIP_HDMI, TVO_VIP_CLIP_DISABLED); | |
cdfbff78 BG |
387 | |
388 | /* set round mode (rounded to 8-bit per component) */ | |
ca279601 | 389 | tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED); |
cdfbff78 BG |
390 | |
391 | if (of_device_is_compatible(node, "st,stih407-tvout")) { | |
392 | /* set input video format */ | |
ca279601 BG |
393 | tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, |
394 | TVO_IN_FMT_SIGNED); | |
cdfbff78 BG |
395 | sel_input_logic_inverted = true; |
396 | } | |
397 | ||
398 | /* input selection */ | |
ca279601 | 399 | tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path, |
cdfbff78 BG |
400 | sel_input_logic_inverted, STI_TVOUT_VIDEO_OUT_RGB); |
401 | } | |
402 | ||
403 | /** | |
404 | * Start HDF VIP and HD DAC | |
405 | * | |
406 | * @tvout: pointer on tvout structure | |
407 | * @main_path: true if main path has to be used in the vip configuration | |
408 | * else aux path is used. | |
409 | */ | |
410 | static void tvout_hda_start(struct sti_tvout *tvout, bool main_path) | |
411 | { | |
412 | struct device_node *node = tvout->dev->of_node; | |
413 | bool sel_input_logic_inverted = false; | |
ca279601 BG |
414 | u32 tvo_in_vid_format; |
415 | int val; | |
cdfbff78 BG |
416 | |
417 | dev_dbg(tvout->dev, "%s\n", __func__); | |
418 | ||
ca279601 | 419 | if (main_path) { |
503290ce VA |
420 | DRM_DEBUG_DRIVER("main vip for HDF\n"); |
421 | /* Select the input sync for HD analog and HD DCS */ | |
422 | val = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDDCS; | |
423 | val = val << TVO_SYNC_HD_DCS_SHIFT; | |
424 | val |= TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDF; | |
ca279601 BG |
425 | tvout_write(tvout, val, TVO_HD_SYNC_SEL); |
426 | tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; | |
427 | } else { | |
503290ce VA |
428 | DRM_DEBUG_DRIVER("aux vip for HDF\n"); |
429 | /* Select the input sync for HD analog and HD DCS */ | |
430 | val = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDDCS; | |
431 | val = val << TVO_SYNC_HD_DCS_SHIFT; | |
432 | val |= TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDF; | |
ca279601 BG |
433 | tvout_write(tvout, val, TVO_HD_SYNC_SEL); |
434 | tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; | |
cdfbff78 BG |
435 | } |
436 | ||
cdfbff78 | 437 | /* set color channel order */ |
ca279601 | 438 | tvout_vip_set_color_order(tvout, TVO_VIP_HDF, |
cdfbff78 BG |
439 | TVO_VIP_REORDER_CR_R_SEL, |
440 | TVO_VIP_REORDER_Y_G_SEL, | |
441 | TVO_VIP_REORDER_CB_B_SEL); | |
442 | ||
1834b84d VA |
443 | /* set clipping mode */ |
444 | tvout_vip_set_clip_mode(tvout, TVO_VIP_HDF, TVO_VIP_CLIP_DISABLED); | |
cdfbff78 BG |
445 | |
446 | /* set round mode (rounded to 10-bit per component) */ | |
ca279601 | 447 | tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED); |
cdfbff78 BG |
448 | |
449 | if (of_device_is_compatible(node, "st,stih407-tvout")) { | |
450 | /* set input video format */ | |
ca279601 BG |
451 | tvout_vip_set_in_vid_fmt(tvout, |
452 | tvo_in_vid_format, TVO_IN_FMT_SIGNED); | |
cdfbff78 BG |
453 | sel_input_logic_inverted = true; |
454 | } | |
455 | ||
456 | /* Input selection */ | |
ca279601 | 457 | tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path, |
cdfbff78 BG |
458 | sel_input_logic_inverted, |
459 | STI_TVOUT_VIDEO_OUT_YUV); | |
460 | ||
cdfbff78 BG |
461 | /* power up HD DAC */ |
462 | tvout_write(tvout, 0, TVO_HD_DAC_CFG_OFF); | |
463 | } | |
464 | ||
465 | static void sti_tvout_encoder_dpms(struct drm_encoder *encoder, int mode) | |
466 | { | |
467 | } | |
468 | ||
cdfbff78 BG |
469 | static void sti_tvout_encoder_mode_set(struct drm_encoder *encoder, |
470 | struct drm_display_mode *mode, | |
471 | struct drm_display_mode *adjusted_mode) | |
472 | { | |
473 | } | |
474 | ||
cdfbff78 BG |
475 | static void sti_tvout_encoder_destroy(struct drm_encoder *encoder) |
476 | { | |
477 | struct sti_tvout_encoder *sti_encoder = to_sti_tvout_encoder(encoder); | |
478 | ||
479 | drm_encoder_cleanup(encoder); | |
480 | kfree(sti_encoder); | |
481 | } | |
482 | ||
483 | static const struct drm_encoder_funcs sti_tvout_encoder_funcs = { | |
484 | .destroy = sti_tvout_encoder_destroy, | |
485 | }; | |
486 | ||
05a142c2 | 487 | static void sti_dvo_encoder_enable(struct drm_encoder *encoder) |
f32c4c50 BG |
488 | { |
489 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
490 | ||
05a142c2 BH |
491 | tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode); |
492 | ||
9e1f05b2 | 493 | tvout_dvo_start(tvout, sti_crtc_is_main(encoder->crtc)); |
f32c4c50 BG |
494 | } |
495 | ||
496 | static void sti_dvo_encoder_disable(struct drm_encoder *encoder) | |
497 | { | |
498 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
499 | ||
500 | /* Reset VIP register */ | |
501 | tvout_write(tvout, 0x0, TVO_VIP_DVO); | |
502 | } | |
503 | ||
504 | static const struct drm_encoder_helper_funcs sti_dvo_encoder_helper_funcs = { | |
505 | .dpms = sti_tvout_encoder_dpms, | |
f32c4c50 | 506 | .mode_set = sti_tvout_encoder_mode_set, |
05a142c2 | 507 | .enable = sti_dvo_encoder_enable, |
f32c4c50 BG |
508 | .disable = sti_dvo_encoder_disable, |
509 | }; | |
510 | ||
511 | static struct drm_encoder * | |
512 | sti_tvout_create_dvo_encoder(struct drm_device *dev, | |
513 | struct sti_tvout *tvout) | |
514 | { | |
515 | struct sti_tvout_encoder *encoder; | |
516 | struct drm_encoder *drm_encoder; | |
517 | ||
518 | encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL); | |
519 | if (!encoder) | |
520 | return NULL; | |
521 | ||
522 | encoder->tvout = tvout; | |
523 | ||
524 | drm_encoder = (struct drm_encoder *)encoder; | |
525 | ||
526 | drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; | |
527 | drm_encoder->possible_clones = 1 << 0; | |
528 | ||
529 | drm_encoder_init(dev, drm_encoder, | |
13a3d91f VS |
530 | &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_LVDS, |
531 | NULL); | |
f32c4c50 BG |
532 | |
533 | drm_encoder_helper_add(drm_encoder, &sti_dvo_encoder_helper_funcs); | |
534 | ||
535 | return drm_encoder; | |
536 | } | |
537 | ||
05a142c2 | 538 | static void sti_hda_encoder_enable(struct drm_encoder *encoder) |
cdfbff78 BG |
539 | { |
540 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
541 | ||
05a142c2 BH |
542 | tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode); |
543 | ||
9e1f05b2 | 544 | tvout_hda_start(tvout, sti_crtc_is_main(encoder->crtc)); |
cdfbff78 BG |
545 | } |
546 | ||
547 | static void sti_hda_encoder_disable(struct drm_encoder *encoder) | |
548 | { | |
549 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
550 | ||
551 | /* reset VIP register */ | |
552 | tvout_write(tvout, 0x0, TVO_VIP_HDF); | |
553 | ||
554 | /* power down HD DAC */ | |
555 | tvout_write(tvout, 1, TVO_HD_DAC_CFG_OFF); | |
556 | } | |
557 | ||
558 | static const struct drm_encoder_helper_funcs sti_hda_encoder_helper_funcs = { | |
559 | .dpms = sti_tvout_encoder_dpms, | |
cdfbff78 | 560 | .mode_set = sti_tvout_encoder_mode_set, |
05a142c2 | 561 | .commit = sti_hda_encoder_enable, |
cdfbff78 BG |
562 | .disable = sti_hda_encoder_disable, |
563 | }; | |
564 | ||
565 | static struct drm_encoder *sti_tvout_create_hda_encoder(struct drm_device *dev, | |
566 | struct sti_tvout *tvout) | |
567 | { | |
568 | struct sti_tvout_encoder *encoder; | |
569 | struct drm_encoder *drm_encoder; | |
570 | ||
571 | encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL); | |
572 | if (!encoder) | |
573 | return NULL; | |
574 | ||
575 | encoder->tvout = tvout; | |
576 | ||
577 | drm_encoder = (struct drm_encoder *) encoder; | |
578 | ||
5e03abc5 | 579 | drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; |
cdfbff78 BG |
580 | drm_encoder->possible_clones = 1 << 0; |
581 | ||
582 | drm_encoder_init(dev, drm_encoder, | |
13a3d91f | 583 | &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL); |
cdfbff78 BG |
584 | |
585 | drm_encoder_helper_add(drm_encoder, &sti_hda_encoder_helper_funcs); | |
586 | ||
587 | return drm_encoder; | |
588 | } | |
589 | ||
05a142c2 | 590 | static void sti_hdmi_encoder_enable(struct drm_encoder *encoder) |
cdfbff78 BG |
591 | { |
592 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
593 | ||
05a142c2 BH |
594 | tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode); |
595 | ||
9e1f05b2 | 596 | tvout_hdmi_start(tvout, sti_crtc_is_main(encoder->crtc)); |
cdfbff78 BG |
597 | } |
598 | ||
599 | static void sti_hdmi_encoder_disable(struct drm_encoder *encoder) | |
600 | { | |
601 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
602 | ||
603 | /* reset VIP register */ | |
604 | tvout_write(tvout, 0x0, TVO_VIP_HDMI); | |
605 | } | |
606 | ||
607 | static const struct drm_encoder_helper_funcs sti_hdmi_encoder_helper_funcs = { | |
608 | .dpms = sti_tvout_encoder_dpms, | |
cdfbff78 | 609 | .mode_set = sti_tvout_encoder_mode_set, |
05a142c2 | 610 | .commit = sti_hdmi_encoder_enable, |
cdfbff78 BG |
611 | .disable = sti_hdmi_encoder_disable, |
612 | }; | |
613 | ||
614 | static struct drm_encoder *sti_tvout_create_hdmi_encoder(struct drm_device *dev, | |
615 | struct sti_tvout *tvout) | |
616 | { | |
617 | struct sti_tvout_encoder *encoder; | |
618 | struct drm_encoder *drm_encoder; | |
619 | ||
620 | encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL); | |
621 | if (!encoder) | |
622 | return NULL; | |
623 | ||
624 | encoder->tvout = tvout; | |
625 | ||
626 | drm_encoder = (struct drm_encoder *) encoder; | |
627 | ||
5e03abc5 | 628 | drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; |
cdfbff78 BG |
629 | drm_encoder->possible_clones = 1 << 1; |
630 | ||
631 | drm_encoder_init(dev, drm_encoder, | |
13a3d91f | 632 | &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); |
cdfbff78 BG |
633 | |
634 | drm_encoder_helper_add(drm_encoder, &sti_hdmi_encoder_helper_funcs); | |
635 | ||
636 | return drm_encoder; | |
637 | } | |
638 | ||
639 | static void sti_tvout_create_encoders(struct drm_device *dev, | |
640 | struct sti_tvout *tvout) | |
641 | { | |
642 | tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout); | |
643 | tvout->hda = sti_tvout_create_hda_encoder(dev, tvout); | |
f32c4c50 | 644 | tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout); |
cdfbff78 BG |
645 | } |
646 | ||
647 | static void sti_tvout_destroy_encoders(struct sti_tvout *tvout) | |
648 | { | |
649 | if (tvout->hdmi) | |
650 | drm_encoder_cleanup(tvout->hdmi); | |
651 | tvout->hdmi = NULL; | |
652 | ||
653 | if (tvout->hda) | |
654 | drm_encoder_cleanup(tvout->hda); | |
655 | tvout->hda = NULL; | |
0a1dc29d VA |
656 | |
657 | if (tvout->dvo) | |
658 | drm_encoder_cleanup(tvout->dvo); | |
659 | tvout->dvo = NULL; | |
cdfbff78 BG |
660 | } |
661 | ||
662 | static int sti_tvout_bind(struct device *dev, struct device *master, void *data) | |
663 | { | |
664 | struct sti_tvout *tvout = dev_get_drvdata(dev); | |
665 | struct drm_device *drm_dev = data; | |
cdfbff78 BG |
666 | |
667 | tvout->drm_dev = drm_dev; | |
668 | ||
cdfbff78 BG |
669 | sti_tvout_create_encoders(drm_dev, tvout); |
670 | ||
53bdcf5f | 671 | return 0; |
cdfbff78 BG |
672 | } |
673 | ||
674 | static void sti_tvout_unbind(struct device *dev, struct device *master, | |
675 | void *data) | |
676 | { | |
53bdcf5f BG |
677 | struct sti_tvout *tvout = dev_get_drvdata(dev); |
678 | ||
679 | sti_tvout_destroy_encoders(tvout); | |
cdfbff78 BG |
680 | } |
681 | ||
682 | static const struct component_ops sti_tvout_ops = { | |
683 | .bind = sti_tvout_bind, | |
684 | .unbind = sti_tvout_unbind, | |
685 | }; | |
686 | ||
cdfbff78 BG |
687 | static int sti_tvout_probe(struct platform_device *pdev) |
688 | { | |
689 | struct device *dev = &pdev->dev; | |
690 | struct device_node *node = dev->of_node; | |
691 | struct sti_tvout *tvout; | |
692 | struct resource *res; | |
cdfbff78 BG |
693 | |
694 | DRM_INFO("%s\n", __func__); | |
695 | ||
696 | if (!node) | |
697 | return -ENODEV; | |
698 | ||
699 | tvout = devm_kzalloc(dev, sizeof(*tvout), GFP_KERNEL); | |
700 | if (!tvout) | |
701 | return -ENOMEM; | |
702 | ||
703 | tvout->dev = dev; | |
704 | ||
705 | /* get Memory ressources */ | |
706 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg"); | |
707 | if (!res) { | |
708 | DRM_ERROR("Invalid glue resource\n"); | |
709 | return -ENOMEM; | |
710 | } | |
711 | tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | |
31f32a21 WY |
712 | if (!tvout->regs) |
713 | return -ENOMEM; | |
cdfbff78 BG |
714 | |
715 | /* get reset resources */ | |
716 | tvout->reset = devm_reset_control_get(dev, "tvout"); | |
717 | /* take tvout out of reset */ | |
718 | if (!IS_ERR(tvout->reset)) | |
719 | reset_control_deassert(tvout->reset); | |
720 | ||
721 | platform_set_drvdata(pdev, tvout); | |
722 | ||
cdfbff78 BG |
723 | return component_add(dev, &sti_tvout_ops); |
724 | } | |
725 | ||
726 | static int sti_tvout_remove(struct platform_device *pdev) | |
727 | { | |
cdfbff78 BG |
728 | component_del(&pdev->dev, &sti_tvout_ops); |
729 | return 0; | |
730 | } | |
731 | ||
8e932cf0 | 732 | static const struct of_device_id tvout_of_match[] = { |
cdfbff78 BG |
733 | { .compatible = "st,stih416-tvout", }, |
734 | { .compatible = "st,stih407-tvout", }, | |
735 | { /* end node */ } | |
736 | }; | |
737 | MODULE_DEVICE_TABLE(of, tvout_of_match); | |
738 | ||
739 | struct platform_driver sti_tvout_driver = { | |
740 | .driver = { | |
741 | .name = "sti-tvout", | |
742 | .owner = THIS_MODULE, | |
743 | .of_match_table = tvout_of_match, | |
744 | }, | |
745 | .probe = sti_tvout_probe, | |
746 | .remove = sti_tvout_remove, | |
747 | }; | |
748 | ||
cdfbff78 BG |
749 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); |
750 | MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); | |
751 | MODULE_LICENSE("GPL"); |