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cdfbff78 BG |
1 | /* |
2 | * Copyright (C) STMicroelectronics SA 2014 | |
3 | * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> | |
4 | * Vincent Abriou <vincent.abriou@st.com> | |
5 | * for STMicroelectronics. | |
6 | * License terms: GNU General Public License (GPL), version 2 | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/component.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_platform.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/reset.h> | |
0f3e1561 | 15 | #include <linux/seq_file.h> |
cdfbff78 BG |
16 | |
17 | #include <drm/drmP.h> | |
18 | #include <drm/drm_crtc_helper.h> | |
19 | ||
9e1f05b2 | 20 | #include "sti_crtc.h" |
503290ce | 21 | #include "sti_vtg.h" |
5e03abc5 | 22 | |
cdfbff78 BG |
23 | /* glue registers */ |
24 | #define TVO_CSC_MAIN_M0 0x000 | |
25 | #define TVO_CSC_MAIN_M1 0x004 | |
26 | #define TVO_CSC_MAIN_M2 0x008 | |
27 | #define TVO_CSC_MAIN_M3 0x00c | |
28 | #define TVO_CSC_MAIN_M4 0x010 | |
29 | #define TVO_CSC_MAIN_M5 0x014 | |
30 | #define TVO_CSC_MAIN_M6 0x018 | |
31 | #define TVO_CSC_MAIN_M7 0x01c | |
32 | #define TVO_MAIN_IN_VID_FORMAT 0x030 | |
33 | #define TVO_CSC_AUX_M0 0x100 | |
34 | #define TVO_CSC_AUX_M1 0x104 | |
35 | #define TVO_CSC_AUX_M2 0x108 | |
36 | #define TVO_CSC_AUX_M3 0x10c | |
37 | #define TVO_CSC_AUX_M4 0x110 | |
38 | #define TVO_CSC_AUX_M5 0x114 | |
39 | #define TVO_CSC_AUX_M6 0x118 | |
40 | #define TVO_CSC_AUX_M7 0x11c | |
41 | #define TVO_AUX_IN_VID_FORMAT 0x130 | |
42 | #define TVO_VIP_HDF 0x400 | |
43 | #define TVO_HD_SYNC_SEL 0x418 | |
44 | #define TVO_HD_DAC_CFG_OFF 0x420 | |
45 | #define TVO_VIP_HDMI 0x500 | |
46 | #define TVO_HDMI_FORCE_COLOR_0 0x504 | |
47 | #define TVO_HDMI_FORCE_COLOR_1 0x508 | |
48 | #define TVO_HDMI_CLIP_VALUE_B_CB 0x50c | |
49 | #define TVO_HDMI_CLIP_VALUE_Y_G 0x510 | |
50 | #define TVO_HDMI_CLIP_VALUE_R_CR 0x514 | |
51 | #define TVO_HDMI_SYNC_SEL 0x518 | |
52 | #define TVO_HDMI_DFV_OBS 0x540 | |
f32c4c50 BG |
53 | #define TVO_VIP_DVO 0x600 |
54 | #define TVO_DVO_SYNC_SEL 0x618 | |
55 | #define TVO_DVO_CONFIG 0x620 | |
cdfbff78 BG |
56 | |
57 | #define TVO_IN_FMT_SIGNED BIT(0) | |
58 | #define TVO_SYNC_EXT BIT(4) | |
59 | ||
60 | #define TVO_VIP_REORDER_R_SHIFT 24 | |
61 | #define TVO_VIP_REORDER_G_SHIFT 20 | |
62 | #define TVO_VIP_REORDER_B_SHIFT 16 | |
63 | #define TVO_VIP_REORDER_MASK 0x3 | |
64 | #define TVO_VIP_REORDER_Y_G_SEL 0 | |
65 | #define TVO_VIP_REORDER_CB_B_SEL 1 | |
66 | #define TVO_VIP_REORDER_CR_R_SEL 2 | |
67 | ||
68 | #define TVO_VIP_CLIP_SHIFT 8 | |
69 | #define TVO_VIP_CLIP_MASK 0x7 | |
70 | #define TVO_VIP_CLIP_DISABLED 0 | |
71 | #define TVO_VIP_CLIP_EAV_SAV 1 | |
72 | #define TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y 2 | |
73 | #define TVO_VIP_CLIP_LIMITED_RANGE_CB_CR 3 | |
74 | #define TVO_VIP_CLIP_PROG_RANGE 4 | |
75 | ||
76 | #define TVO_VIP_RND_SHIFT 4 | |
77 | #define TVO_VIP_RND_MASK 0x3 | |
78 | #define TVO_VIP_RND_8BIT_ROUNDED 0 | |
79 | #define TVO_VIP_RND_10BIT_ROUNDED 1 | |
80 | #define TVO_VIP_RND_12BIT_ROUNDED 2 | |
81 | ||
82 | #define TVO_VIP_SEL_INPUT_MASK 0xf | |
83 | #define TVO_VIP_SEL_INPUT_MAIN 0x0 | |
84 | #define TVO_VIP_SEL_INPUT_AUX 0x8 | |
85 | #define TVO_VIP_SEL_INPUT_FORCE_COLOR 0xf | |
86 | #define TVO_VIP_SEL_INPUT_BYPASS_MASK 0x1 | |
87 | #define TVO_VIP_SEL_INPUT_BYPASSED 1 | |
88 | ||
89 | #define TVO_SYNC_MAIN_VTG_SET_REF 0x00 | |
cdfbff78 | 90 | #define TVO_SYNC_AUX_VTG_SET_REF 0x10 |
cdfbff78 BG |
91 | |
92 | #define TVO_SYNC_HD_DCS_SHIFT 8 | |
93 | ||
f32c4c50 BG |
94 | #define TVO_SYNC_DVO_PAD_HSYNC_SHIFT 8 |
95 | #define TVO_SYNC_DVO_PAD_VSYNC_SHIFT 16 | |
96 | ||
5e03abc5 | 97 | #define ENCODER_CRTC_MASK (BIT(0) | BIT(1)) |
cdfbff78 | 98 | |
05a142c2 BH |
99 | #define TVO_MIN_HD_HEIGHT 720 |
100 | ||
cdfbff78 BG |
101 | /* enum listing the supported output data format */ |
102 | enum sti_tvout_video_out_type { | |
103 | STI_TVOUT_VIDEO_OUT_RGB, | |
104 | STI_TVOUT_VIDEO_OUT_YUV, | |
105 | }; | |
106 | ||
107 | struct sti_tvout { | |
108 | struct device *dev; | |
109 | struct drm_device *drm_dev; | |
110 | void __iomem *regs; | |
111 | struct reset_control *reset; | |
112 | struct drm_encoder *hdmi; | |
113 | struct drm_encoder *hda; | |
f32c4c50 | 114 | struct drm_encoder *dvo; |
83af0a48 | 115 | bool debugfs_registered; |
cdfbff78 BG |
116 | }; |
117 | ||
118 | struct sti_tvout_encoder { | |
119 | struct drm_encoder encoder; | |
120 | struct sti_tvout *tvout; | |
121 | }; | |
122 | ||
123 | #define to_sti_tvout_encoder(x) \ | |
124 | container_of(x, struct sti_tvout_encoder, encoder) | |
125 | ||
126 | #define to_sti_tvout(x) to_sti_tvout_encoder(x)->tvout | |
127 | ||
128 | /* preformatter conversion matrix */ | |
129 | static const u32 rgb_to_ycbcr_601[8] = { | |
130 | 0xF927082E, 0x04C9FEAB, 0x01D30964, 0xFA95FD3D, | |
131 | 0x0000082E, 0x00002000, 0x00002000, 0x00000000 | |
132 | }; | |
133 | ||
134 | /* 709 RGB to YCbCr */ | |
135 | static const u32 rgb_to_ycbcr_709[8] = { | |
136 | 0xF891082F, 0x0367FF40, 0x01280B71, 0xF9B1FE20, | |
137 | 0x0000082F, 0x00002000, 0x00002000, 0x00000000 | |
138 | }; | |
139 | ||
140 | static u32 tvout_read(struct sti_tvout *tvout, int offset) | |
141 | { | |
142 | return readl(tvout->regs + offset); | |
143 | } | |
144 | ||
145 | static void tvout_write(struct sti_tvout *tvout, u32 val, int offset) | |
146 | { | |
147 | writel(val, tvout->regs + offset); | |
148 | } | |
149 | ||
150 | /** | |
151 | * Set the clipping mode of a VIP | |
152 | * | |
153 | * @tvout: tvout structure | |
ca279601 | 154 | * @reg: register to set |
cdfbff78 BG |
155 | * @cr_r: |
156 | * @y_g: | |
157 | * @cb_b: | |
158 | */ | |
ca279601 | 159 | static void tvout_vip_set_color_order(struct sti_tvout *tvout, int reg, |
cdfbff78 BG |
160 | u32 cr_r, u32 y_g, u32 cb_b) |
161 | { | |
ca279601 | 162 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
163 | |
164 | val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT); | |
165 | val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT); | |
166 | val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT); | |
167 | val |= cr_r << TVO_VIP_REORDER_R_SHIFT; | |
168 | val |= y_g << TVO_VIP_REORDER_G_SHIFT; | |
169 | val |= cb_b << TVO_VIP_REORDER_B_SHIFT; | |
170 | ||
ca279601 | 171 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
172 | } |
173 | ||
174 | /** | |
175 | * Set the clipping mode of a VIP | |
176 | * | |
177 | * @tvout: tvout structure | |
ca279601 | 178 | * @reg: register to set |
cdfbff78 BG |
179 | * @range: clipping range |
180 | */ | |
ca279601 | 181 | static void tvout_vip_set_clip_mode(struct sti_tvout *tvout, int reg, u32 range) |
cdfbff78 | 182 | { |
ca279601 | 183 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
184 | |
185 | val &= ~(TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT); | |
186 | val |= range << TVO_VIP_CLIP_SHIFT; | |
ca279601 | 187 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
188 | } |
189 | ||
190 | /** | |
191 | * Set the rounded value of a VIP | |
192 | * | |
193 | * @tvout: tvout structure | |
ca279601 | 194 | * @reg: register to set |
cdfbff78 BG |
195 | * @rnd: rounded val per component |
196 | */ | |
ca279601 | 197 | static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd) |
cdfbff78 | 198 | { |
ca279601 | 199 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
200 | |
201 | val &= ~(TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT); | |
202 | val |= rnd << TVO_VIP_RND_SHIFT; | |
ca279601 | 203 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
204 | } |
205 | ||
206 | /** | |
207 | * Select the VIP input | |
208 | * | |
209 | * @tvout: tvout structure | |
ca279601 BG |
210 | * @reg: register to set |
211 | * @main_path: main or auxiliary path | |
212 | * @sel_input_logic_inverted: need to invert the logic | |
cdfbff78 BG |
213 | * @sel_input: selected_input (main/aux + conv) |
214 | */ | |
215 | static void tvout_vip_set_sel_input(struct sti_tvout *tvout, | |
ca279601 | 216 | int reg, |
cdfbff78 BG |
217 | bool main_path, |
218 | bool sel_input_logic_inverted, | |
219 | enum sti_tvout_video_out_type video_out) | |
220 | { | |
221 | u32 sel_input; | |
ca279601 | 222 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
223 | |
224 | if (main_path) | |
225 | sel_input = TVO_VIP_SEL_INPUT_MAIN; | |
226 | else | |
227 | sel_input = TVO_VIP_SEL_INPUT_AUX; | |
228 | ||
229 | switch (video_out) { | |
230 | case STI_TVOUT_VIDEO_OUT_RGB: | |
231 | sel_input |= TVO_VIP_SEL_INPUT_BYPASSED; | |
232 | break; | |
233 | case STI_TVOUT_VIDEO_OUT_YUV: | |
234 | sel_input &= ~TVO_VIP_SEL_INPUT_BYPASSED; | |
235 | break; | |
236 | } | |
237 | ||
238 | /* on stih407 chip the sel_input bypass mode logic is inverted */ | |
239 | if (sel_input_logic_inverted) | |
240 | sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK; | |
241 | ||
242 | val &= ~TVO_VIP_SEL_INPUT_MASK; | |
243 | val |= sel_input; | |
ca279601 | 244 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
245 | } |
246 | ||
247 | /** | |
248 | * Select the input video signed or unsigned | |
249 | * | |
250 | * @tvout: tvout structure | |
ca279601 | 251 | * @reg: register to set |
cdfbff78 BG |
252 | * @in_vid_signed: used video input format |
253 | */ | |
ca279601 BG |
254 | static void tvout_vip_set_in_vid_fmt(struct sti_tvout *tvout, |
255 | int reg, u32 in_vid_fmt) | |
cdfbff78 | 256 | { |
ca279601 | 257 | u32 val = tvout_read(tvout, reg); |
cdfbff78 BG |
258 | |
259 | val &= ~TVO_IN_FMT_SIGNED; | |
260 | val |= in_vid_fmt; | |
ca279601 | 261 | tvout_write(tvout, val, reg); |
cdfbff78 BG |
262 | } |
263 | ||
05a142c2 BH |
264 | /** |
265 | * Set preformatter matrix | |
266 | * | |
267 | * @tvout: tvout structure | |
268 | * @mode: display mode structure | |
269 | */ | |
270 | static void tvout_preformatter_set_matrix(struct sti_tvout *tvout, | |
271 | struct drm_display_mode *mode) | |
272 | { | |
273 | unsigned int i; | |
274 | const u32 *pf_matrix; | |
275 | ||
276 | if (mode->vdisplay >= TVO_MIN_HD_HEIGHT) | |
277 | pf_matrix = rgb_to_ycbcr_709; | |
278 | else | |
279 | pf_matrix = rgb_to_ycbcr_601; | |
280 | ||
281 | for (i = 0; i < 8; i++) { | |
282 | tvout_write(tvout, *(pf_matrix + i), | |
283 | TVO_CSC_MAIN_M0 + (i * 4)); | |
284 | tvout_write(tvout, *(pf_matrix + i), | |
285 | TVO_CSC_AUX_M0 + (i * 4)); | |
286 | } | |
287 | } | |
288 | ||
f32c4c50 BG |
289 | /** |
290 | * Start VIP block for DVO output | |
291 | * | |
292 | * @tvout: pointer on tvout structure | |
293 | * @main_path: true if main path has to be used in the vip configuration | |
294 | * else aux path is used. | |
295 | */ | |
296 | static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path) | |
297 | { | |
298 | struct device_node *node = tvout->dev->of_node; | |
299 | bool sel_input_logic_inverted = false; | |
300 | u32 tvo_in_vid_format; | |
503290ce | 301 | int val, tmp; |
f32c4c50 BG |
302 | |
303 | dev_dbg(tvout->dev, "%s\n", __func__); | |
304 | ||
305 | if (main_path) { | |
306 | DRM_DEBUG_DRIVER("main vip for DVO\n"); | |
503290ce VA |
307 | /* Select the input sync for dvo */ |
308 | tmp = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_DVO; | |
309 | val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; | |
310 | val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; | |
311 | val |= tmp; | |
f32c4c50 BG |
312 | tvout_write(tvout, val, TVO_DVO_SYNC_SEL); |
313 | tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; | |
314 | } else { | |
315 | DRM_DEBUG_DRIVER("aux vip for DVO\n"); | |
503290ce VA |
316 | /* Select the input sync for dvo */ |
317 | tmp = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_DVO; | |
318 | val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; | |
319 | val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; | |
320 | val |= tmp; | |
f32c4c50 BG |
321 | tvout_write(tvout, val, TVO_DVO_SYNC_SEL); |
322 | tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; | |
323 | } | |
324 | ||
325 | /* Set color channel order */ | |
326 | tvout_vip_set_color_order(tvout, TVO_VIP_DVO, | |
327 | TVO_VIP_REORDER_CR_R_SEL, | |
328 | TVO_VIP_REORDER_Y_G_SEL, | |
329 | TVO_VIP_REORDER_CB_B_SEL); | |
330 | ||
1834b84d VA |
331 | /* Set clipping mode */ |
332 | tvout_vip_set_clip_mode(tvout, TVO_VIP_DVO, TVO_VIP_CLIP_DISABLED); | |
f32c4c50 BG |
333 | |
334 | /* Set round mode (rounded to 8-bit per component) */ | |
335 | tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED); | |
336 | ||
337 | if (of_device_is_compatible(node, "st,stih407-tvout")) { | |
338 | /* Set input video format */ | |
339 | tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, | |
340 | TVO_IN_FMT_SIGNED); | |
341 | sel_input_logic_inverted = true; | |
342 | } | |
343 | ||
344 | /* Input selection */ | |
345 | tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path, | |
346 | sel_input_logic_inverted, | |
347 | STI_TVOUT_VIDEO_OUT_RGB); | |
348 | } | |
349 | ||
cdfbff78 BG |
350 | /** |
351 | * Start VIP block for HDMI output | |
352 | * | |
353 | * @tvout: pointer on tvout structure | |
354 | * @main_path: true if main path has to be used in the vip configuration | |
355 | * else aux path is used. | |
356 | */ | |
357 | static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path) | |
358 | { | |
359 | struct device_node *node = tvout->dev->of_node; | |
360 | bool sel_input_logic_inverted = false; | |
ca279601 | 361 | u32 tvo_in_vid_format; |
cdfbff78 BG |
362 | |
363 | dev_dbg(tvout->dev, "%s\n", __func__); | |
364 | ||
365 | if (main_path) { | |
366 | DRM_DEBUG_DRIVER("main vip for hdmi\n"); | |
503290ce VA |
367 | /* select the input sync for hdmi */ |
368 | tvout_write(tvout, | |
369 | TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDMI, | |
370 | TVO_HDMI_SYNC_SEL); | |
ca279601 | 371 | tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; |
cdfbff78 BG |
372 | } else { |
373 | DRM_DEBUG_DRIVER("aux vip for hdmi\n"); | |
503290ce VA |
374 | /* select the input sync for hdmi */ |
375 | tvout_write(tvout, | |
376 | TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDMI, | |
377 | TVO_HDMI_SYNC_SEL); | |
ca279601 | 378 | tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; |
cdfbff78 BG |
379 | } |
380 | ||
381 | /* set color channel order */ | |
ca279601 | 382 | tvout_vip_set_color_order(tvout, TVO_VIP_HDMI, |
cdfbff78 BG |
383 | TVO_VIP_REORDER_CR_R_SEL, |
384 | TVO_VIP_REORDER_Y_G_SEL, | |
385 | TVO_VIP_REORDER_CB_B_SEL); | |
386 | ||
1834b84d VA |
387 | /* set clipping mode */ |
388 | tvout_vip_set_clip_mode(tvout, TVO_VIP_HDMI, TVO_VIP_CLIP_DISABLED); | |
cdfbff78 BG |
389 | |
390 | /* set round mode (rounded to 8-bit per component) */ | |
ca279601 | 391 | tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED); |
cdfbff78 BG |
392 | |
393 | if (of_device_is_compatible(node, "st,stih407-tvout")) { | |
394 | /* set input video format */ | |
ca279601 BG |
395 | tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, |
396 | TVO_IN_FMT_SIGNED); | |
cdfbff78 BG |
397 | sel_input_logic_inverted = true; |
398 | } | |
399 | ||
400 | /* input selection */ | |
ca279601 | 401 | tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path, |
cdfbff78 BG |
402 | sel_input_logic_inverted, STI_TVOUT_VIDEO_OUT_RGB); |
403 | } | |
404 | ||
405 | /** | |
406 | * Start HDF VIP and HD DAC | |
407 | * | |
408 | * @tvout: pointer on tvout structure | |
409 | * @main_path: true if main path has to be used in the vip configuration | |
410 | * else aux path is used. | |
411 | */ | |
412 | static void tvout_hda_start(struct sti_tvout *tvout, bool main_path) | |
413 | { | |
414 | struct device_node *node = tvout->dev->of_node; | |
415 | bool sel_input_logic_inverted = false; | |
ca279601 BG |
416 | u32 tvo_in_vid_format; |
417 | int val; | |
cdfbff78 BG |
418 | |
419 | dev_dbg(tvout->dev, "%s\n", __func__); | |
420 | ||
ca279601 | 421 | if (main_path) { |
503290ce VA |
422 | DRM_DEBUG_DRIVER("main vip for HDF\n"); |
423 | /* Select the input sync for HD analog and HD DCS */ | |
424 | val = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDDCS; | |
425 | val = val << TVO_SYNC_HD_DCS_SHIFT; | |
426 | val |= TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDF; | |
ca279601 BG |
427 | tvout_write(tvout, val, TVO_HD_SYNC_SEL); |
428 | tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; | |
429 | } else { | |
503290ce VA |
430 | DRM_DEBUG_DRIVER("aux vip for HDF\n"); |
431 | /* Select the input sync for HD analog and HD DCS */ | |
432 | val = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDDCS; | |
433 | val = val << TVO_SYNC_HD_DCS_SHIFT; | |
434 | val |= TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDF; | |
ca279601 BG |
435 | tvout_write(tvout, val, TVO_HD_SYNC_SEL); |
436 | tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; | |
cdfbff78 BG |
437 | } |
438 | ||
cdfbff78 | 439 | /* set color channel order */ |
ca279601 | 440 | tvout_vip_set_color_order(tvout, TVO_VIP_HDF, |
cdfbff78 BG |
441 | TVO_VIP_REORDER_CR_R_SEL, |
442 | TVO_VIP_REORDER_Y_G_SEL, | |
443 | TVO_VIP_REORDER_CB_B_SEL); | |
444 | ||
1834b84d VA |
445 | /* set clipping mode */ |
446 | tvout_vip_set_clip_mode(tvout, TVO_VIP_HDF, TVO_VIP_CLIP_DISABLED); | |
cdfbff78 BG |
447 | |
448 | /* set round mode (rounded to 10-bit per component) */ | |
ca279601 | 449 | tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED); |
cdfbff78 BG |
450 | |
451 | if (of_device_is_compatible(node, "st,stih407-tvout")) { | |
452 | /* set input video format */ | |
ca279601 BG |
453 | tvout_vip_set_in_vid_fmt(tvout, |
454 | tvo_in_vid_format, TVO_IN_FMT_SIGNED); | |
cdfbff78 BG |
455 | sel_input_logic_inverted = true; |
456 | } | |
457 | ||
458 | /* Input selection */ | |
ca279601 | 459 | tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path, |
cdfbff78 BG |
460 | sel_input_logic_inverted, |
461 | STI_TVOUT_VIDEO_OUT_YUV); | |
462 | ||
cdfbff78 BG |
463 | /* power up HD DAC */ |
464 | tvout_write(tvout, 0, TVO_HD_DAC_CFG_OFF); | |
465 | } | |
466 | ||
b514bee7 VA |
467 | #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ |
468 | readl(tvout->regs + reg)) | |
469 | ||
470 | static void tvout_dbg_vip(struct seq_file *s, int val) | |
471 | { | |
472 | int r, g, b, tmp, mask; | |
473 | char *const reorder[] = {"Y_G", "Cb_B", "Cr_R"}; | |
474 | char *const clipping[] = {"No", "EAV/SAV", "Limited range RGB/Y", | |
475 | "Limited range Cb/Cr", "decided by register"}; | |
476 | char *const round[] = {"8-bit", "10-bit", "12-bit"}; | |
477 | char *const input_sel[] = {"Main (color matrix enabled)", | |
478 | "Main (color matrix by-passed)", | |
479 | "", "", "", "", "", "", | |
480 | "Aux (color matrix enabled)", | |
481 | "Aux (color matrix by-passed)", | |
482 | "", "", "", "", "", "Force value"}; | |
483 | ||
484 | seq_puts(s, "\t"); | |
485 | mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT; | |
486 | r = (val & mask) >> TVO_VIP_REORDER_R_SHIFT; | |
487 | mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT; | |
488 | g = (val & mask) >> TVO_VIP_REORDER_G_SHIFT; | |
489 | mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT; | |
490 | b = (val & mask) >> TVO_VIP_REORDER_B_SHIFT; | |
491 | seq_printf(s, "%-24s %s->%s %s->%s %s->%s\n", "Reorder:", | |
492 | reorder[r], reorder[TVO_VIP_REORDER_CR_R_SEL], | |
493 | reorder[g], reorder[TVO_VIP_REORDER_Y_G_SEL], | |
494 | reorder[b], reorder[TVO_VIP_REORDER_CB_B_SEL]); | |
495 | seq_puts(s, "\t\t\t\t\t"); | |
496 | mask = TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT; | |
497 | tmp = (val & mask) >> TVO_VIP_CLIP_SHIFT; | |
498 | seq_printf(s, "%-24s %s\n", "Clipping:", clipping[tmp]); | |
499 | seq_puts(s, "\t\t\t\t\t"); | |
500 | mask = TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT; | |
501 | tmp = (val & mask) >> TVO_VIP_RND_SHIFT; | |
502 | seq_printf(s, "%-24s input data rounded to %s per component\n", | |
503 | "Round:", round[tmp]); | |
504 | seq_puts(s, "\t\t\t\t\t"); | |
505 | tmp = (val & TVO_VIP_SEL_INPUT_MASK); | |
506 | seq_printf(s, "%-24s %s", "Input selection:", input_sel[tmp]); | |
507 | } | |
508 | ||
509 | static void tvout_dbg_hd_dac_cfg(struct seq_file *s, int val) | |
510 | { | |
511 | seq_printf(s, "\t%-24s %s", "HD DAC:", | |
512 | val & 1 ? "disabled" : "enabled"); | |
513 | } | |
514 | ||
515 | static int tvout_dbg_show(struct seq_file *s, void *data) | |
516 | { | |
517 | struct drm_info_node *node = s->private; | |
518 | struct sti_tvout *tvout = (struct sti_tvout *)node->info_ent->data; | |
b514bee7 | 519 | struct drm_crtc *crtc; |
b514bee7 VA |
520 | |
521 | seq_printf(s, "TVOUT: (vaddr = 0x%p)", tvout->regs); | |
522 | ||
523 | seq_puts(s, "\n\n HDMI encoder: "); | |
524 | crtc = tvout->hdmi->crtc; | |
525 | if (crtc) { | |
526 | seq_printf(s, "connected to %s path", | |
527 | sti_crtc_is_main(crtc) ? "main" : "aux"); | |
528 | DBGFS_DUMP(TVO_HDMI_SYNC_SEL); | |
529 | DBGFS_DUMP(TVO_VIP_HDMI); | |
530 | tvout_dbg_vip(s, readl(tvout->regs + TVO_VIP_HDMI)); | |
531 | } else { | |
532 | seq_puts(s, "disabled"); | |
533 | } | |
534 | ||
535 | seq_puts(s, "\n\n DVO encoder: "); | |
536 | crtc = tvout->dvo->crtc; | |
537 | if (crtc) { | |
538 | seq_printf(s, "connected to %s path", | |
539 | sti_crtc_is_main(crtc) ? "main" : "aux"); | |
540 | DBGFS_DUMP(TVO_DVO_SYNC_SEL); | |
541 | DBGFS_DUMP(TVO_DVO_CONFIG); | |
542 | DBGFS_DUMP(TVO_VIP_DVO); | |
543 | tvout_dbg_vip(s, readl(tvout->regs + TVO_VIP_DVO)); | |
544 | } else { | |
545 | seq_puts(s, "disabled"); | |
546 | } | |
547 | ||
548 | seq_puts(s, "\n\n HDA encoder: "); | |
549 | crtc = tvout->hda->crtc; | |
550 | if (crtc) { | |
551 | seq_printf(s, "connected to %s path", | |
552 | sti_crtc_is_main(crtc) ? "main" : "aux"); | |
553 | DBGFS_DUMP(TVO_HD_SYNC_SEL); | |
554 | DBGFS_DUMP(TVO_HD_DAC_CFG_OFF); | |
555 | tvout_dbg_hd_dac_cfg(s, | |
556 | readl(tvout->regs + TVO_HD_DAC_CFG_OFF)); | |
557 | DBGFS_DUMP(TVO_VIP_HDF); | |
558 | tvout_dbg_vip(s, readl(tvout->regs + TVO_VIP_HDF)); | |
559 | } else { | |
560 | seq_puts(s, "disabled"); | |
561 | } | |
562 | ||
563 | seq_puts(s, "\n\n main path configuration"); | |
564 | DBGFS_DUMP(TVO_CSC_MAIN_M0); | |
565 | DBGFS_DUMP(TVO_CSC_MAIN_M1); | |
566 | DBGFS_DUMP(TVO_CSC_MAIN_M2); | |
567 | DBGFS_DUMP(TVO_CSC_MAIN_M3); | |
568 | DBGFS_DUMP(TVO_CSC_MAIN_M4); | |
569 | DBGFS_DUMP(TVO_CSC_MAIN_M5); | |
570 | DBGFS_DUMP(TVO_CSC_MAIN_M6); | |
571 | DBGFS_DUMP(TVO_CSC_MAIN_M7); | |
572 | DBGFS_DUMP(TVO_MAIN_IN_VID_FORMAT); | |
573 | ||
574 | seq_puts(s, "\n\n auxiliary path configuration"); | |
575 | DBGFS_DUMP(TVO_CSC_AUX_M0); | |
576 | DBGFS_DUMP(TVO_CSC_AUX_M2); | |
577 | DBGFS_DUMP(TVO_CSC_AUX_M3); | |
578 | DBGFS_DUMP(TVO_CSC_AUX_M4); | |
579 | DBGFS_DUMP(TVO_CSC_AUX_M5); | |
580 | DBGFS_DUMP(TVO_CSC_AUX_M6); | |
581 | DBGFS_DUMP(TVO_CSC_AUX_M7); | |
582 | DBGFS_DUMP(TVO_AUX_IN_VID_FORMAT); | |
583 | seq_puts(s, "\n"); | |
584 | ||
b514bee7 VA |
585 | return 0; |
586 | } | |
587 | ||
588 | static struct drm_info_list tvout_debugfs_files[] = { | |
589 | { "tvout", tvout_dbg_show, 0, NULL }, | |
590 | }; | |
591 | ||
592 | static void tvout_debugfs_exit(struct sti_tvout *tvout, struct drm_minor *minor) | |
593 | { | |
594 | drm_debugfs_remove_files(tvout_debugfs_files, | |
595 | ARRAY_SIZE(tvout_debugfs_files), | |
596 | minor); | |
597 | } | |
598 | ||
599 | static int tvout_debugfs_init(struct sti_tvout *tvout, struct drm_minor *minor) | |
600 | { | |
601 | unsigned int i; | |
602 | ||
603 | for (i = 0; i < ARRAY_SIZE(tvout_debugfs_files); i++) | |
604 | tvout_debugfs_files[i].data = tvout; | |
605 | ||
606 | return drm_debugfs_create_files(tvout_debugfs_files, | |
607 | ARRAY_SIZE(tvout_debugfs_files), | |
608 | minor->debugfs_root, minor); | |
609 | } | |
610 | ||
cdfbff78 BG |
611 | static void sti_tvout_encoder_dpms(struct drm_encoder *encoder, int mode) |
612 | { | |
613 | } | |
614 | ||
cdfbff78 BG |
615 | static void sti_tvout_encoder_mode_set(struct drm_encoder *encoder, |
616 | struct drm_display_mode *mode, | |
617 | struct drm_display_mode *adjusted_mode) | |
618 | { | |
619 | } | |
620 | ||
cdfbff78 BG |
621 | static void sti_tvout_encoder_destroy(struct drm_encoder *encoder) |
622 | { | |
623 | struct sti_tvout_encoder *sti_encoder = to_sti_tvout_encoder(encoder); | |
624 | ||
625 | drm_encoder_cleanup(encoder); | |
626 | kfree(sti_encoder); | |
627 | } | |
628 | ||
83af0a48 BG |
629 | static int sti_tvout_late_register(struct drm_encoder *encoder) |
630 | { | |
631 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
632 | int ret; | |
633 | ||
634 | if (tvout->debugfs_registered) | |
635 | return 0; | |
636 | ||
637 | ret = tvout_debugfs_init(tvout, encoder->dev->primary); | |
638 | if (ret) | |
639 | return ret; | |
640 | ||
641 | tvout->debugfs_registered = true; | |
642 | return 0; | |
643 | } | |
644 | ||
645 | static void sti_tvout_early_unregister(struct drm_encoder *encoder) | |
646 | { | |
647 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
648 | ||
649 | if (!tvout->debugfs_registered) | |
650 | return; | |
651 | ||
652 | tvout_debugfs_exit(tvout, encoder->dev->primary); | |
653 | tvout->debugfs_registered = false; | |
654 | } | |
655 | ||
cdfbff78 BG |
656 | static const struct drm_encoder_funcs sti_tvout_encoder_funcs = { |
657 | .destroy = sti_tvout_encoder_destroy, | |
83af0a48 BG |
658 | .late_register = sti_tvout_late_register, |
659 | .early_unregister = sti_tvout_early_unregister, | |
cdfbff78 BG |
660 | }; |
661 | ||
05a142c2 | 662 | static void sti_dvo_encoder_enable(struct drm_encoder *encoder) |
f32c4c50 BG |
663 | { |
664 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
665 | ||
05a142c2 BH |
666 | tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode); |
667 | ||
9e1f05b2 | 668 | tvout_dvo_start(tvout, sti_crtc_is_main(encoder->crtc)); |
f32c4c50 BG |
669 | } |
670 | ||
671 | static void sti_dvo_encoder_disable(struct drm_encoder *encoder) | |
672 | { | |
673 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
674 | ||
675 | /* Reset VIP register */ | |
676 | tvout_write(tvout, 0x0, TVO_VIP_DVO); | |
677 | } | |
678 | ||
679 | static const struct drm_encoder_helper_funcs sti_dvo_encoder_helper_funcs = { | |
680 | .dpms = sti_tvout_encoder_dpms, | |
f32c4c50 | 681 | .mode_set = sti_tvout_encoder_mode_set, |
05a142c2 | 682 | .enable = sti_dvo_encoder_enable, |
f32c4c50 BG |
683 | .disable = sti_dvo_encoder_disable, |
684 | }; | |
685 | ||
686 | static struct drm_encoder * | |
687 | sti_tvout_create_dvo_encoder(struct drm_device *dev, | |
688 | struct sti_tvout *tvout) | |
689 | { | |
690 | struct sti_tvout_encoder *encoder; | |
691 | struct drm_encoder *drm_encoder; | |
692 | ||
693 | encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL); | |
694 | if (!encoder) | |
695 | return NULL; | |
696 | ||
697 | encoder->tvout = tvout; | |
698 | ||
699 | drm_encoder = (struct drm_encoder *)encoder; | |
700 | ||
701 | drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; | |
702 | drm_encoder->possible_clones = 1 << 0; | |
703 | ||
704 | drm_encoder_init(dev, drm_encoder, | |
13a3d91f VS |
705 | &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_LVDS, |
706 | NULL); | |
f32c4c50 BG |
707 | |
708 | drm_encoder_helper_add(drm_encoder, &sti_dvo_encoder_helper_funcs); | |
709 | ||
710 | return drm_encoder; | |
711 | } | |
712 | ||
05a142c2 | 713 | static void sti_hda_encoder_enable(struct drm_encoder *encoder) |
cdfbff78 BG |
714 | { |
715 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
716 | ||
05a142c2 BH |
717 | tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode); |
718 | ||
9e1f05b2 | 719 | tvout_hda_start(tvout, sti_crtc_is_main(encoder->crtc)); |
cdfbff78 BG |
720 | } |
721 | ||
722 | static void sti_hda_encoder_disable(struct drm_encoder *encoder) | |
723 | { | |
724 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
725 | ||
726 | /* reset VIP register */ | |
727 | tvout_write(tvout, 0x0, TVO_VIP_HDF); | |
728 | ||
729 | /* power down HD DAC */ | |
730 | tvout_write(tvout, 1, TVO_HD_DAC_CFG_OFF); | |
731 | } | |
732 | ||
733 | static const struct drm_encoder_helper_funcs sti_hda_encoder_helper_funcs = { | |
734 | .dpms = sti_tvout_encoder_dpms, | |
cdfbff78 | 735 | .mode_set = sti_tvout_encoder_mode_set, |
05a142c2 | 736 | .commit = sti_hda_encoder_enable, |
cdfbff78 BG |
737 | .disable = sti_hda_encoder_disable, |
738 | }; | |
739 | ||
740 | static struct drm_encoder *sti_tvout_create_hda_encoder(struct drm_device *dev, | |
741 | struct sti_tvout *tvout) | |
742 | { | |
743 | struct sti_tvout_encoder *encoder; | |
744 | struct drm_encoder *drm_encoder; | |
745 | ||
746 | encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL); | |
747 | if (!encoder) | |
748 | return NULL; | |
749 | ||
750 | encoder->tvout = tvout; | |
751 | ||
752 | drm_encoder = (struct drm_encoder *) encoder; | |
753 | ||
5e03abc5 | 754 | drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; |
cdfbff78 BG |
755 | drm_encoder->possible_clones = 1 << 0; |
756 | ||
757 | drm_encoder_init(dev, drm_encoder, | |
13a3d91f | 758 | &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL); |
cdfbff78 BG |
759 | |
760 | drm_encoder_helper_add(drm_encoder, &sti_hda_encoder_helper_funcs); | |
761 | ||
762 | return drm_encoder; | |
763 | } | |
764 | ||
05a142c2 | 765 | static void sti_hdmi_encoder_enable(struct drm_encoder *encoder) |
cdfbff78 BG |
766 | { |
767 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
768 | ||
05a142c2 BH |
769 | tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode); |
770 | ||
9e1f05b2 | 771 | tvout_hdmi_start(tvout, sti_crtc_is_main(encoder->crtc)); |
cdfbff78 BG |
772 | } |
773 | ||
774 | static void sti_hdmi_encoder_disable(struct drm_encoder *encoder) | |
775 | { | |
776 | struct sti_tvout *tvout = to_sti_tvout(encoder); | |
777 | ||
778 | /* reset VIP register */ | |
779 | tvout_write(tvout, 0x0, TVO_VIP_HDMI); | |
780 | } | |
781 | ||
782 | static const struct drm_encoder_helper_funcs sti_hdmi_encoder_helper_funcs = { | |
783 | .dpms = sti_tvout_encoder_dpms, | |
cdfbff78 | 784 | .mode_set = sti_tvout_encoder_mode_set, |
05a142c2 | 785 | .commit = sti_hdmi_encoder_enable, |
cdfbff78 BG |
786 | .disable = sti_hdmi_encoder_disable, |
787 | }; | |
788 | ||
789 | static struct drm_encoder *sti_tvout_create_hdmi_encoder(struct drm_device *dev, | |
790 | struct sti_tvout *tvout) | |
791 | { | |
792 | struct sti_tvout_encoder *encoder; | |
793 | struct drm_encoder *drm_encoder; | |
794 | ||
795 | encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL); | |
796 | if (!encoder) | |
797 | return NULL; | |
798 | ||
799 | encoder->tvout = tvout; | |
800 | ||
801 | drm_encoder = (struct drm_encoder *) encoder; | |
802 | ||
5e03abc5 | 803 | drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; |
cdfbff78 BG |
804 | drm_encoder->possible_clones = 1 << 1; |
805 | ||
806 | drm_encoder_init(dev, drm_encoder, | |
13a3d91f | 807 | &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); |
cdfbff78 BG |
808 | |
809 | drm_encoder_helper_add(drm_encoder, &sti_hdmi_encoder_helper_funcs); | |
810 | ||
811 | return drm_encoder; | |
812 | } | |
813 | ||
814 | static void sti_tvout_create_encoders(struct drm_device *dev, | |
815 | struct sti_tvout *tvout) | |
816 | { | |
817 | tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout); | |
818 | tvout->hda = sti_tvout_create_hda_encoder(dev, tvout); | |
f32c4c50 | 819 | tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout); |
cdfbff78 BG |
820 | } |
821 | ||
822 | static void sti_tvout_destroy_encoders(struct sti_tvout *tvout) | |
823 | { | |
824 | if (tvout->hdmi) | |
825 | drm_encoder_cleanup(tvout->hdmi); | |
826 | tvout->hdmi = NULL; | |
827 | ||
828 | if (tvout->hda) | |
829 | drm_encoder_cleanup(tvout->hda); | |
830 | tvout->hda = NULL; | |
0a1dc29d VA |
831 | |
832 | if (tvout->dvo) | |
833 | drm_encoder_cleanup(tvout->dvo); | |
834 | tvout->dvo = NULL; | |
cdfbff78 BG |
835 | } |
836 | ||
837 | static int sti_tvout_bind(struct device *dev, struct device *master, void *data) | |
838 | { | |
839 | struct sti_tvout *tvout = dev_get_drvdata(dev); | |
840 | struct drm_device *drm_dev = data; | |
cdfbff78 BG |
841 | |
842 | tvout->drm_dev = drm_dev; | |
843 | ||
cdfbff78 BG |
844 | sti_tvout_create_encoders(drm_dev, tvout); |
845 | ||
53bdcf5f | 846 | return 0; |
cdfbff78 BG |
847 | } |
848 | ||
849 | static void sti_tvout_unbind(struct device *dev, struct device *master, | |
850 | void *data) | |
851 | { | |
53bdcf5f BG |
852 | struct sti_tvout *tvout = dev_get_drvdata(dev); |
853 | ||
854 | sti_tvout_destroy_encoders(tvout); | |
cdfbff78 BG |
855 | } |
856 | ||
857 | static const struct component_ops sti_tvout_ops = { | |
858 | .bind = sti_tvout_bind, | |
859 | .unbind = sti_tvout_unbind, | |
860 | }; | |
861 | ||
cdfbff78 BG |
862 | static int sti_tvout_probe(struct platform_device *pdev) |
863 | { | |
864 | struct device *dev = &pdev->dev; | |
865 | struct device_node *node = dev->of_node; | |
866 | struct sti_tvout *tvout; | |
867 | struct resource *res; | |
cdfbff78 BG |
868 | |
869 | DRM_INFO("%s\n", __func__); | |
870 | ||
871 | if (!node) | |
872 | return -ENODEV; | |
873 | ||
874 | tvout = devm_kzalloc(dev, sizeof(*tvout), GFP_KERNEL); | |
875 | if (!tvout) | |
876 | return -ENOMEM; | |
877 | ||
878 | tvout->dev = dev; | |
879 | ||
880 | /* get Memory ressources */ | |
881 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg"); | |
882 | if (!res) { | |
883 | DRM_ERROR("Invalid glue resource\n"); | |
884 | return -ENOMEM; | |
885 | } | |
886 | tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); | |
31f32a21 WY |
887 | if (!tvout->regs) |
888 | return -ENOMEM; | |
cdfbff78 BG |
889 | |
890 | /* get reset resources */ | |
891 | tvout->reset = devm_reset_control_get(dev, "tvout"); | |
892 | /* take tvout out of reset */ | |
893 | if (!IS_ERR(tvout->reset)) | |
894 | reset_control_deassert(tvout->reset); | |
895 | ||
896 | platform_set_drvdata(pdev, tvout); | |
897 | ||
cdfbff78 BG |
898 | return component_add(dev, &sti_tvout_ops); |
899 | } | |
900 | ||
901 | static int sti_tvout_remove(struct platform_device *pdev) | |
902 | { | |
cdfbff78 BG |
903 | component_del(&pdev->dev, &sti_tvout_ops); |
904 | return 0; | |
905 | } | |
906 | ||
8e932cf0 | 907 | static const struct of_device_id tvout_of_match[] = { |
cdfbff78 BG |
908 | { .compatible = "st,stih416-tvout", }, |
909 | { .compatible = "st,stih407-tvout", }, | |
910 | { /* end node */ } | |
911 | }; | |
912 | MODULE_DEVICE_TABLE(of, tvout_of_match); | |
913 | ||
914 | struct platform_driver sti_tvout_driver = { | |
915 | .driver = { | |
916 | .name = "sti-tvout", | |
917 | .owner = THIS_MODULE, | |
918 | .of_match_table = tvout_of_match, | |
919 | }, | |
920 | .probe = sti_tvout_probe, | |
921 | .remove = sti_tvout_remove, | |
922 | }; | |
923 | ||
cdfbff78 BG |
924 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); |
925 | MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); | |
926 | MODULE_LICENSE("GPL"); |