[deliverable/linux.git] / drivers / gpu / drm / sti / sti_vid.c

/*
 * Copyright (C) STMicroelectronics SA 2014
 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
 * License terms:  GNU General Public License (GPL), version 2
 */
#include <linux/seq_file.h>

#include <drm/drmP.h>

#include "sti_plane.h"
#include "sti_vid.h"
#include "sti_vtg.h"

/* Registers */
#define VID_CTL                 0x00
#define VID_ALP                 0x04
#define VID_CLF                 0x08
#define VID_VPO                 0x0C
#define VID_VPS                 0x10
#define VID_KEY1                0x28
#define VID_KEY2                0x2C
#define VID_MPR0                0x30
#define VID_MPR1                0x34
#define VID_MPR2                0x38
#define VID_MPR3                0x3C
#define VID_MST                 0x68
#define VID_BC                  0x70
#define VID_TINT                0x74
#define VID_CSAT                0x78

/* Registers values */
#define VID_CTL_IGNORE          (BIT(31) | BIT(30))
#define VID_CTL_PSI_ENABLE      (BIT(2) | BIT(1) | BIT(0))
#define VID_ALP_OPAQUE          0x00000080
#define VID_BC_DFLT             0x00008000
#define VID_TINT_DFLT           0x00000000
#define VID_CSAT_DFLT           0x00000080
/* YCbCr to RGB BT709:
 * R = Y+1.5391Cr
 * G = Y-0.4590Cr-0.1826Cb
 * B = Y+1.8125Cb */
#define VID_MPR0_BT709          0x0A800000
#define VID_MPR1_BT709          0x0AC50000
#define VID_MPR2_BT709          0x07150545
#define VID_MPR3_BT709          0x00000AE8
/* YCbCr to RGB BT709:
 * R = Y+1.3711Cr
 * G = Y-0.6992Cr-0.3359Cb
 * B = Y+1.7344Cb
 */
#define VID_MPR0_BT601          0x0A800000
#define VID_MPR1_BT601          0x0AAF0000
#define VID_MPR2_BT601          0x094E0754
#define VID_MPR3_BT601          0x00000ADD

#define VID_MIN_HD_HEIGHT       720

#define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
				   readl(vid->regs + reg))

static void vid_dbg_ctl(struct seq_file *s, int val)
{
	val = val >> 30;
	seq_puts(s, "\t");

	if (!(val & 1))
		seq_puts(s, "NOT ");
	seq_puts(s, "ignored on main mixer - ");

	if (!(val & 2))
		seq_puts(s, "NOT ");
	seq_puts(s, "ignored on aux mixer");
}

static void vid_dbg_vpo(struct seq_file *s, int val)
{
	seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF);
}

static void vid_dbg_vps(struct seq_file *s, int val)
{
	seq_printf(s, "\txds:%4d\tyds:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF);
}

static void vid_dbg_mst(struct seq_file *s, int val)
{
	if (val & 1)
		seq_puts(s, "\tBUFFER UNDERFLOW!");
}

static int vid_dbg_show(struct seq_file *s, void *arg)
{
	struct drm_info_node *node = s->private;
	struct sti_vid *vid = (struct sti_vid *)node->info_ent->data;

	seq_printf(s, "VID: (vaddr= 0x%p)", vid->regs);

	DBGFS_DUMP(VID_CTL);
	vid_dbg_ctl(s, readl(vid->regs + VID_CTL));
	DBGFS_DUMP(VID_ALP);
	DBGFS_DUMP(VID_CLF);
	DBGFS_DUMP(VID_VPO);
	vid_dbg_vpo(s, readl(vid->regs + VID_VPO));
	DBGFS_DUMP(VID_VPS);
	vid_dbg_vps(s, readl(vid->regs + VID_VPS));
	DBGFS_DUMP(VID_KEY1);
	DBGFS_DUMP(VID_KEY2);
	DBGFS_DUMP(VID_MPR0);
	DBGFS_DUMP(VID_MPR1);
	DBGFS_DUMP(VID_MPR2);
	DBGFS_DUMP(VID_MPR3);
	DBGFS_DUMP(VID_MST);
	vid_dbg_mst(s, readl(vid->regs + VID_MST));
	DBGFS_DUMP(VID_BC);
	DBGFS_DUMP(VID_TINT);
	DBGFS_DUMP(VID_CSAT);
	seq_puts(s, "\n");

	return 0;
}

static struct drm_info_list vid_debugfs_files[] = {
	{ "vid", vid_dbg_show, 0, NULL },
};

int vid_debugfs_init(struct sti_vid *vid, struct drm_minor *minor)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(vid_debugfs_files); i++)
		vid_debugfs_files[i].data = vid;

	return drm_debugfs_create_files(vid_debugfs_files,
					ARRAY_SIZE(vid_debugfs_files),
					minor->debugfs_root, minor);
}

void sti_vid_commit(struct sti_vid *vid,
		    struct drm_plane_state *state)
{
	struct drm_crtc *crtc = state->crtc;
	struct drm_display_mode *mode = &crtc->mode;
	int dst_x = state->crtc_x;
	int dst_y = state->crtc_y;
	int dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
	int dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
	int src_h = state->src_h >> 16;
	u32 val, ydo, xdo, yds, xds;

	/* Input / output size
	 * Align to upper even value */
	dst_w = ALIGN(dst_w, 2);
	dst_h = ALIGN(dst_h, 2);

	/* Unmask */
	val = readl(vid->regs + VID_CTL);
	val &= ~VID_CTL_IGNORE;
	writel(val, vid->regs + VID_CTL);

	ydo = sti_vtg_get_line_number(*mode, dst_y);
	yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
	xdo = sti_vtg_get_pixel_number(*mode, dst_x);
	xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);

	writel((ydo << 16) | xdo, vid->regs + VID_VPO);
	writel((yds << 16) | xds, vid->regs + VID_VPS);

	/* Color conversion parameters */
	if (src_h >= VID_MIN_HD_HEIGHT) {
		writel(VID_MPR0_BT709, vid->regs + VID_MPR0);
		writel(VID_MPR1_BT709, vid->regs + VID_MPR1);
		writel(VID_MPR2_BT709, vid->regs + VID_MPR2);
		writel(VID_MPR3_BT709, vid->regs + VID_MPR3);
	} else {
		writel(VID_MPR0_BT601, vid->regs + VID_MPR0);
		writel(VID_MPR1_BT601, vid->regs + VID_MPR1);
		writel(VID_MPR2_BT601, vid->regs + VID_MPR2);
		writel(VID_MPR3_BT601, vid->regs + VID_MPR3);
	}
}

void sti_vid_disable(struct sti_vid *vid)
{
	u32 val;

	/* Mask */
	val = readl(vid->regs + VID_CTL);
	val |= VID_CTL_IGNORE;
	writel(val, vid->regs + VID_CTL);
}

static void sti_vid_init(struct sti_vid *vid)
{
	/* Enable PSI, Mask layer */
	writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL);

	/* Opaque */
	writel(VID_ALP_OPAQUE, vid->regs + VID_ALP);

	/* Brightness, contrast, tint, saturation */
	writel(VID_BC_DFLT, vid->regs + VID_BC);
	writel(VID_TINT_DFLT, vid->regs + VID_TINT);
	writel(VID_CSAT_DFLT, vid->regs + VID_CSAT);
}

struct sti_vid *sti_vid_create(struct device *dev, struct drm_device *drm_dev,
			       int id, void __iomem *baseaddr)
{
	struct sti_vid *vid;

	vid = devm_kzalloc(dev, sizeof(*vid), GFP_KERNEL);
	if (!vid) {
		DRM_ERROR("Failed to allocate memory for VID\n");
		return NULL;
	}

	vid->dev = dev;
	vid->regs = baseaddr;
	vid->id = id;

	sti_vid_init(vid);

	return vid;
}
Commit	Line	Data
cfd8d744 BG	1	/*
	2	* Copyright (C) STMicroelectronics SA 2014
	3	* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
	4	* License terms: GNU General Public License (GPL), version 2
	5	*/
0f3e1561	6	#include <linux/seq_file.h>
cfd8d744 BG	7
	8	#include <drm/drmP.h>
	9
9e1f05b2	10	#include "sti_plane.h"
cfd8d744 BG	11	#include "sti_vid.h"
	12	#include "sti_vtg.h"
	13
	14	/* Registers */
	15	#define VID_CTL 0x00
	16	#define VID_ALP 0x04
	17	#define VID_CLF 0x08
	18	#define VID_VPO 0x0C
	19	#define VID_VPS 0x10
	20	#define VID_KEY1 0x28
	21	#define VID_KEY2 0x2C
	22	#define VID_MPR0 0x30
	23	#define VID_MPR1 0x34
	24	#define VID_MPR2 0x38
	25	#define VID_MPR3 0x3C
	26	#define VID_MST 0x68
	27	#define VID_BC 0x70
	28	#define VID_TINT 0x74
	29	#define VID_CSAT 0x78
	30
	31	/* Registers values */
	32	#define VID_CTL_IGNORE (BIT(31) \| BIT(30))
	33	#define VID_CTL_PSI_ENABLE (BIT(2) \| BIT(1) \| BIT(0))
	34	#define VID_ALP_OPAQUE 0x00000080
	35	#define VID_BC_DFLT 0x00008000
	36	#define VID_TINT_DFLT 0x00000000
	37	#define VID_CSAT_DFLT 0x00000080
	38	/* YCbCr to RGB BT709:
	39	* R = Y+1.5391Cr
	40	* G = Y-0.4590Cr-0.1826Cb
	41	* B = Y+1.8125Cb */
	42	#define VID_MPR0_BT709 0x0A800000
	43	#define VID_MPR1_BT709 0x0AC50000
	44	#define VID_MPR2_BT709 0x07150545
	45	#define VID_MPR3_BT709 0x00000AE8
05a142c2 BH	46	/* YCbCr to RGB BT709:
	47	* R = Y+1.3711Cr
	48	* G = Y-0.6992Cr-0.3359Cb
	49	* B = Y+1.7344Cb
	50	*/
	51	#define VID_MPR0_BT601 0x0A800000
	52	#define VID_MPR1_BT601 0x0AAF0000
	53	#define VID_MPR2_BT601 0x094E0754
	54	#define VID_MPR3_BT601 0x00000ADD
	55
	56	#define VID_MIN_HD_HEIGHT 720
cfd8d744	57
90dffef5 VA	58	#define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
	59	readl(vid->regs + reg))
	60
	61	static void vid_dbg_ctl(struct seq_file *s, int val)
	62	{
	63	val = val >> 30;
	64	seq_puts(s, "\t");
	65
	66	if (!(val & 1))
	67	seq_puts(s, "NOT ");
	68	seq_puts(s, "ignored on main mixer - ");
	69
	70	if (!(val & 2))
	71	seq_puts(s, "NOT ");
	72	seq_puts(s, "ignored on aux mixer");
	73	}
	74
	75	static void vid_dbg_vpo(struct seq_file *s, int val)
	76	{
	77	seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF);
	78	}
	79
	80	static void vid_dbg_vps(struct seq_file *s, int val)
	81	{
	82	seq_printf(s, "\txds:%4d\tyds:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF);
	83	}
	84
	85	static void vid_dbg_mst(struct seq_file *s, int val)
	86	{
	87	if (val & 1)
	88	seq_puts(s, "\tBUFFER UNDERFLOW!");
	89	}
	90
	91	static int vid_dbg_show(struct seq_file s, void arg)
	92	{
	93	struct drm_info_node *node = s->private;
	94	struct sti_vid vid = (struct sti_vid )node->info_ent->data;
90dffef5 VA	95
	96	seq_printf(s, "VID: (vaddr= 0x%p)", vid->regs);
	97
	98	DBGFS_DUMP(VID_CTL);
	99	vid_dbg_ctl(s, readl(vid->regs + VID_CTL));
	100	DBGFS_DUMP(VID_ALP);
	101	DBGFS_DUMP(VID_CLF);
	102	DBGFS_DUMP(VID_VPO);
	103	vid_dbg_vpo(s, readl(vid->regs + VID_VPO));
	104	DBGFS_DUMP(VID_VPS);
	105	vid_dbg_vps(s, readl(vid->regs + VID_VPS));
	106	DBGFS_DUMP(VID_KEY1);
	107	DBGFS_DUMP(VID_KEY2);
	108	DBGFS_DUMP(VID_MPR0);
	109	DBGFS_DUMP(VID_MPR1);
	110	DBGFS_DUMP(VID_MPR2);
	111	DBGFS_DUMP(VID_MPR3);
	112	DBGFS_DUMP(VID_MST);
	113	vid_dbg_mst(s, readl(vid->regs + VID_MST));
	114	DBGFS_DUMP(VID_BC);
	115	DBGFS_DUMP(VID_TINT);
	116	DBGFS_DUMP(VID_CSAT);
	117	seq_puts(s, "\n");
	118
90dffef5 VA	119	return 0;
	120	}
	121
	122	static struct drm_info_list vid_debugfs_files[] = {
	123	{ "vid", vid_dbg_show, 0, NULL },
	124	};
	125
83af0a48	126	int vid_debugfs_init(struct sti_vid vid, struct drm_minor minor)
90dffef5 VA	127	{
	128	unsigned int i;
	129
	130	for (i = 0; i < ARRAY_SIZE(vid_debugfs_files); i++)
	131	vid_debugfs_files[i].data = vid;
	132
	133	return drm_debugfs_create_files(vid_debugfs_files,
	134	ARRAY_SIZE(vid_debugfs_files),
	135	minor->debugfs_root, minor);
	136	}
	137
29d1dc62 VA	138	void sti_vid_commit(struct sti_vid *vid,
29d1dc62 VA	139	struct drm_plane_state *state)
cfd8d744	140	{
29d1dc62 VA	141	struct drm_crtc *crtc = state->crtc;
	142	struct drm_display_mode *mode = &crtc->mode;
	143	int dst_x = state->crtc_x;
	144	int dst_y = state->crtc_y;
	145	int dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
	146	int dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
05a142c2	147	int src_h = state->src_h >> 16;
871bcdfe	148	u32 val, ydo, xdo, yds, xds;
cfd8d744	149
29d1dc62 VA	150	/* Input / output size
	151	* Align to upper even value */
	152	dst_w = ALIGN(dst_w, 2);
	153	dst_h = ALIGN(dst_h, 2);
	154
cfd8d744 BG	155	/* Unmask */
	156	val = readl(vid->regs + VID_CTL);
	157	val &= ~VID_CTL_IGNORE;
	158	writel(val, vid->regs + VID_CTL);
	159
29d1dc62 VA	160	ydo = sti_vtg_get_line_number(*mode, dst_y);
	161	yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
	162	xdo = sti_vtg_get_pixel_number(*mode, dst_x);
	163	xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
cfd8d744 BG	164
	165	writel((ydo << 16) \| xdo, vid->regs + VID_VPO);
	166	writel((yds << 16) \| xds, vid->regs + VID_VPS);
05a142c2 BH	167
	168	/* Color conversion parameters */
	169	if (src_h >= VID_MIN_HD_HEIGHT) {
	170	writel(VID_MPR0_BT709, vid->regs + VID_MPR0);
	171	writel(VID_MPR1_BT709, vid->regs + VID_MPR1);
	172	writel(VID_MPR2_BT709, vid->regs + VID_MPR2);
	173	writel(VID_MPR3_BT709, vid->regs + VID_MPR3);
	174	} else {
	175	writel(VID_MPR0_BT601, vid->regs + VID_MPR0);
	176	writel(VID_MPR1_BT601, vid->regs + VID_MPR1);
	177	writel(VID_MPR2_BT601, vid->regs + VID_MPR2);
	178	writel(VID_MPR3_BT601, vid->regs + VID_MPR3);
	179	}
cfd8d744 BG	180	}
cfd8d744 BG	181
29d1dc62	182	void sti_vid_disable(struct sti_vid *vid)
cfd8d744 BG	183	{
	184	u32 val;
	185
	186	/* Mask */
	187	val = readl(vid->regs + VID_CTL);
	188	val \|= VID_CTL_IGNORE;
	189	writel(val, vid->regs + VID_CTL);
cfd8d744 BG	190	}
cfd8d744 BG	191
871bcdfe	192	static void sti_vid_init(struct sti_vid *vid)
cfd8d744 BG	193	{
	194	/* Enable PSI, Mask layer */
	195	writel(VID_CTL_PSI_ENABLE \| VID_CTL_IGNORE, vid->regs + VID_CTL);
	196
	197	/* Opaque */
	198	writel(VID_ALP_OPAQUE, vid->regs + VID_ALP);
	199
cfd8d744 BG	200	/* Brightness, contrast, tint, saturation */
	201	writel(VID_BC_DFLT, vid->regs + VID_BC);
	202	writel(VID_TINT_DFLT, vid->regs + VID_TINT);
	203	writel(VID_CSAT_DFLT, vid->regs + VID_CSAT);
	204	}
	205
90dffef5 VA	206	struct sti_vid sti_vid_create(struct device dev, struct drm_device *drm_dev,
90dffef5 VA	207	int id, void __iomem *baseaddr)
cfd8d744	208	{
871bcdfe	209	struct sti_vid *vid;
cfd8d744 BG	210
	211	vid = devm_kzalloc(dev, sizeof(*vid), GFP_KERNEL);
	212	if (!vid) {
	213	DRM_ERROR("Failed to allocate memory for VID\n");
	214	return NULL;
	215	}
	216
871bcdfe VA	217	vid->dev = dev;
	218	vid->regs = baseaddr;
	219	vid->id = id;
	220
	221	sti_vid_init(vid);
cfd8d744 BG	222
	223	return vid;
	224	}