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drm/tegra: dc: Do not needlessly deassert reset
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
ca48080a 13#include <linux/reset.h>
d8f4a9ed 14
9c012700
TR		 15#include <soc/tegra/pmc.h>
16
de2ba664
AM		 17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
d8f4a9ed 20
3cb9ae4f
DV		 21#include <drm/drm_plane_helper.h>
22
8620fc62 23struct tegra_dc_soc_info {
42d0659b 24 bool supports_border_color;
8620fc62 25 bool supports_interlacing;
e687651b 26 bool supports_cursor;
c134f019 27 bool supports_block_linear;
d1f3e1e0 28 unsigned int pitch_align;
9c012700 29 bool has_powergate;
8620fc62
TR		 30};
31
f34bc787
TR		 32struct tegra_plane {
33 struct drm_plane base;
34 unsigned int index;
d8f4a9ed
TR		 35};
36
f34bc787
TR		 37static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
38{
39 return container_of(plane, struct tegra_plane, base);
40}
41
205d48ed
TR		 42static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index)
43{
44 u32 value = WIN_A_ACT_REQ << index;
45
46 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
47 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
48}
49
50static void tegra_dc_cursor_commit(struct tegra_dc *dc)
51{
52 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
53 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
54}
55
86df256f
TR		 56/*
57 * Reads the active copy of a register. This takes the dc->lock spinlock to
58 * prevent races with the VBLANK processing which also needs access to the
59 * active copy of some registers.
60 */
61static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
62{
63 unsigned long flags;
64 u32 value;
65
66 spin_lock_irqsave(&dc->lock, flags);
67
68 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
69 value = tegra_dc_readl(dc, offset);
70 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
71
72 spin_unlock_irqrestore(&dc->lock, flags);
73 return value;
74}
75
d700ba7a
TR		 76/*
77 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
78 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
79 * Latching happens mmediately if the display controller is in STOP mode or
80 * on the next frame boundary otherwise.
81 *
82 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
83 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
84 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
85 * into the ACTIVE copy, either immediately if the display controller is in
86 * STOP mode, or at the next frame boundary otherwise.
87 */
62b9e063 88void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 89{
90 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
91 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
92}
93
10288eea
TR		 94static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
95{
96 /* assume no swapping of fetched data */
97 if (swap)
98 *swap = BYTE_SWAP_NOSWAP;
99
100 switch (format) {
101 case DRM_FORMAT_XBGR8888:
102 return WIN_COLOR_DEPTH_R8G8B8A8;
103
104 case DRM_FORMAT_XRGB8888:
105 return WIN_COLOR_DEPTH_B8G8R8A8;
106
107 case DRM_FORMAT_RGB565:
108 return WIN_COLOR_DEPTH_B5G6R5;
109
110 case DRM_FORMAT_UYVY:
111 return WIN_COLOR_DEPTH_YCbCr422;
112
113 case DRM_FORMAT_YUYV:
114 if (swap)
115 *swap = BYTE_SWAP_SWAP2;
116
117 return WIN_COLOR_DEPTH_YCbCr422;
118
119 case DRM_FORMAT_YUV420:
120 return WIN_COLOR_DEPTH_YCbCr420P;
121
122 case DRM_FORMAT_YUV422:
123 return WIN_COLOR_DEPTH_YCbCr422P;
124
125 default:
126 break;
127 }
128
129 WARN(1, "unsupported pixel format %u, using default\n", format);
130 return WIN_COLOR_DEPTH_B8G8R8A8;
131}
132
133static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
134{
135 switch (format) {
136 case WIN_COLOR_DEPTH_YCbCr422:
137 case WIN_COLOR_DEPTH_YUV422:
138 if (planar)
139 *planar = false;
140
141 return true;
142
143 case WIN_COLOR_DEPTH_YCbCr420P:
144 case WIN_COLOR_DEPTH_YUV420P:
145 case WIN_COLOR_DEPTH_YCbCr422P:
146 case WIN_COLOR_DEPTH_YUV422P:
147 case WIN_COLOR_DEPTH_YCbCr422R:
148 case WIN_COLOR_DEPTH_YUV422R:
149 case WIN_COLOR_DEPTH_YCbCr422RA:
150 case WIN_COLOR_DEPTH_YUV422RA:
151 if (planar)
152 *planar = true;
153
154 return true;
155 }
156
fb35c6b6
TR		 157 if (planar)
158 *planar = false;
159
10288eea
TR		 160 return false;
161}
162
163static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
164 unsigned int bpp)
165{
166 fixed20_12 outf = dfixed_init(out);
167 fixed20_12 inf = dfixed_init(in);
168 u32 dda_inc;
169 int max;
170
171 if (v)
172 max = 15;
173 else {
174 switch (bpp) {
175 case 2:
176 max = 8;
177 break;
178
179 default:
180 WARN_ON_ONCE(1);
181 /* fallthrough */
182 case 4:
183 max = 4;
184 break;
185 }
186 }
187
188 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
189 inf.full -= dfixed_const(1);
190
191 dda_inc = dfixed_div(inf, outf);
192 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
193
194 return dda_inc;
195}
196
197static inline u32 compute_initial_dda(unsigned int in)
198{
199 fixed20_12 inf = dfixed_init(in);
200 return dfixed_frac(inf);
201}
202
203static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
204 const struct tegra_dc_window *window)
205{
206 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 207 unsigned long value, flags;
10288eea
TR		 208 bool yuv, planar;
209
210 /*
211 * For YUV planar modes, the number of bytes per pixel takes into
212 * account only the luma component and therefore is 1.
213 */
214 yuv = tegra_dc_format_is_yuv(window->format, &planar);
215 if (!yuv)
216 bpp = window->bits_per_pixel / 8;
217 else
218 bpp = planar ? 1 : 2;
219
93396d0f
SP		 220 spin_lock_irqsave(&dc->lock, flags);
221
10288eea
TR		 222 value = WINDOW_A_SELECT << index;
223 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
224
225 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
226 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
227
228 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
229 tegra_dc_writel(dc, value, DC_WIN_POSITION);
230
231 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
232 tegra_dc_writel(dc, value, DC_WIN_SIZE);
233
234 h_offset = window->src.x * bpp;
235 v_offset = window->src.y;
236 h_size = window->src.w * bpp;
237 v_size = window->src.h;
238
239 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
240 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
241
242 /*
243 * For DDA computations the number of bytes per pixel for YUV planar
244 * modes needs to take into account all Y, U and V components.
245 */
246 if (yuv && planar)
247 bpp = 2;
248
249 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
250 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
251
252 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
253 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
254
255 h_dda = compute_initial_dda(window->src.x);
256 v_dda = compute_initial_dda(window->src.y);
257
258 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
259 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
260
261 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
262 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
263
264 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
265
266 if (yuv && planar) {
267 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
268 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
269 value = window->stride[1] << 16 | window->stride[0];
270 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
271 } else {
272 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
273 }
274
275 if (window->bottom_up)
276 v_offset += window->src.h - 1;
277
278 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
279 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
280
c134f019
TR		 281 if (dc->soc->supports_block_linear) {
282 unsigned long height = window->tiling.value;
283
284 switch (window->tiling.mode) {
285 case TEGRA_BO_TILING_MODE_PITCH:
286 value = DC_WINBUF_SURFACE_KIND_PITCH;
287 break;
288
289 case TEGRA_BO_TILING_MODE_TILED:
290 value = DC_WINBUF_SURFACE_KIND_TILED;
291 break;
292
293 case TEGRA_BO_TILING_MODE_BLOCK:
294 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
295 DC_WINBUF_SURFACE_KIND_BLOCK;
296 break;
297 }
298
299 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 300 } else {
c134f019
TR		 301 switch (window->tiling.mode) {
302 case TEGRA_BO_TILING_MODE_PITCH:
303 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
304 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
305 break;
10288eea 306
c134f019
TR		 307 case TEGRA_BO_TILING_MODE_TILED:
308 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
309 DC_WIN_BUFFER_ADDR_MODE_TILE;
310 break;
311
312 case TEGRA_BO_TILING_MODE_BLOCK:
313 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 314 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 315 return -EINVAL;
316 }
317
318 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
319 }
10288eea
TR		 320
321 value = WIN_ENABLE;
322
323 if (yuv) {
324 /* setup default colorspace conversion coefficients */
325 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
326 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
327 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
328 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
329 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
330 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
331 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
332 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
333
334 value |= CSC_ENABLE;
335 } else if (window->bits_per_pixel < 24) {
336 value |= COLOR_EXPAND;
337 }
338
339 if (window->bottom_up)
340 value |= V_DIRECTION;
341
342 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
343
344 /*
345 * Disable blending and assume Window A is the bottom-most window,
346 * Window C is the top-most window and Window B is in the middle.
347 */
348 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
349 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
350
351 switch (index) {
352 case 0:
353 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
354 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
355 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
356 break;
357
358 case 1:
359 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
360 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
361 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
362 break;
363
364 case 2:
365 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
366 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
367 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
368 break;
369 }
370
205d48ed 371 tegra_dc_window_commit(dc, index);
10288eea 372
93396d0f
SP		 373 spin_unlock_irqrestore(&dc->lock, flags);
374
10288eea
TR		 375 return 0;
376}
377
c7679306
TR		 378static int tegra_window_plane_disable(struct drm_plane *plane)
379{
380 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
381 struct tegra_plane *p = to_tegra_plane(plane);
93396d0f 382 unsigned long flags;
c7679306
TR		 383 u32 value;
384
385 if (!plane->crtc)
386 return 0;
387
93396d0f
SP		 388 spin_lock_irqsave(&dc->lock, flags);
389
c7679306
TR		 390 value = WINDOW_A_SELECT << p->index;
391 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
392
393 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
394 value &= ~WIN_ENABLE;
395 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
396
397 tegra_dc_window_commit(dc, p->index);
398
93396d0f
SP		 399 spin_unlock_irqrestore(&dc->lock, flags);
400
c7679306
TR		 401 return 0;
402}
403
404static void tegra_plane_destroy(struct drm_plane *plane)
405{
406 struct tegra_plane *p = to_tegra_plane(plane);
407
408 drm_plane_cleanup(plane);
409 kfree(p);
410}
411
412static const u32 tegra_primary_plane_formats[] = {
413 DRM_FORMAT_XBGR8888,
414 DRM_FORMAT_XRGB8888,
415 DRM_FORMAT_RGB565,
416};
417
418static int tegra_primary_plane_update(struct drm_plane *plane,
419 struct drm_crtc *crtc,
420 struct drm_framebuffer *fb, int crtc_x,
421 int crtc_y, unsigned int crtc_w,
422 unsigned int crtc_h, uint32_t src_x,
423 uint32_t src_y, uint32_t src_w,
424 uint32_t src_h)
425{
426 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
427 struct tegra_plane *p = to_tegra_plane(plane);
428 struct tegra_dc *dc = to_tegra_dc(crtc);
429 struct tegra_dc_window window;
430 int err;
431
432 memset(&window, 0, sizeof(window));
433 window.src.x = src_x >> 16;
434 window.src.y = src_y >> 16;
435 window.src.w = src_w >> 16;
436 window.src.h = src_h >> 16;
437 window.dst.x = crtc_x;
438 window.dst.y = crtc_y;
439 window.dst.w = crtc_w;
440 window.dst.h = crtc_h;
441 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
442 window.bits_per_pixel = fb->bits_per_pixel;
443 window.bottom_up = tegra_fb_is_bottom_up(fb);
444
445 err = tegra_fb_get_tiling(fb, &window.tiling);
446 if (err < 0)
447 return err;
448
449 window.base[0] = bo->paddr + fb->offsets[0];
450 window.stride[0] = fb->pitches[0];
451
452 err = tegra_dc_setup_window(dc, p->index, &window);
453 if (err < 0)
454 return err;
10288eea
TR		 455
456 return 0;
457}
458
c7679306
TR		 459static void tegra_primary_plane_destroy(struct drm_plane *plane)
460{
461 tegra_window_plane_disable(plane);
462 tegra_plane_destroy(plane);
463}
464
465static const struct drm_plane_funcs tegra_primary_plane_funcs = {
466 .update_plane = tegra_primary_plane_update,
467 .disable_plane = tegra_window_plane_disable,
468 .destroy = tegra_primary_plane_destroy,
469};
470
471static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
472 struct tegra_dc *dc)
473{
518e6227
TR		 474 /*
475 * Ideally this would use drm_crtc_mask(), but that would require the
476 * CRTC to already be in the mode_config's list of CRTCs. However, it
477 * will only be added to that list in the drm_crtc_init_with_planes()
478 * (in tegra_dc_init()), which in turn requires registration of these
479 * planes. So we have ourselves a nice little chicken and egg problem
480 * here.
481 *
482 * We work around this by manually creating the mask from the number
483 * of CRTCs that have been registered, and should therefore always be
484 * the same as drm_crtc_index() after registration.
485 */
486 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 487 struct tegra_plane *plane;
488 unsigned int num_formats;
489 const u32 *formats;
490 int err;
491
492 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
493 if (!plane)
494 return ERR_PTR(-ENOMEM);
495
496 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
497 formats = tegra_primary_plane_formats;
498
518e6227 499 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306
TR		 500 &tegra_primary_plane_funcs, formats,
501 num_formats, DRM_PLANE_TYPE_PRIMARY);
502 if (err < 0) {
503 kfree(plane);
504 return ERR_PTR(err);
505 }
506
507 return &plane->base;
508}
509
510static const u32 tegra_cursor_plane_formats[] = {
511 DRM_FORMAT_RGBA8888,
512};
513
514static int tegra_cursor_plane_update(struct drm_plane *plane,
515 struct drm_crtc *crtc,
516 struct drm_framebuffer *fb, int crtc_x,
517 int crtc_y, unsigned int crtc_w,
518 unsigned int crtc_h, uint32_t src_x,
519 uint32_t src_y, uint32_t src_w,
520 uint32_t src_h)
521{
522 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
523 struct tegra_dc *dc = to_tegra_dc(crtc);
524 u32 value = CURSOR_CLIP_DISPLAY;
525
526 /* scaling not supported for cursor */
527 if ((src_w >> 16 != crtc_w) || (src_h >> 16 != crtc_h))
528 return -EINVAL;
529
530 /* only square cursors supported */
531 if (src_w != src_h)
532 return -EINVAL;
533
534 switch (crtc_w) {
535 case 32:
536 value |= CURSOR_SIZE_32x32;
537 break;
538
539 case 64:
540 value |= CURSOR_SIZE_64x64;
541 break;
542
543 case 128:
544 value |= CURSOR_SIZE_128x128;
545 break;
546
547 case 256:
548 value |= CURSOR_SIZE_256x256;
549 break;
550
551 default:
552 return -EINVAL;
553 }
554
555 value |= (bo->paddr >> 10) & 0x3fffff;
556 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
557
558#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
559 value = (bo->paddr >> 32) & 0x3;
560 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
561#endif
562
563 /* enable cursor and set blend mode */
564 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
565 value |= CURSOR_ENABLE;
566 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
567
568 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
569 value &= ~CURSOR_DST_BLEND_MASK;
570 value &= ~CURSOR_SRC_BLEND_MASK;
571 value |= CURSOR_MODE_NORMAL;
572 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
573 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
574 value |= CURSOR_ALPHA;
575 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
576
577 /* position the cursor */
578 value = (crtc_y & 0x3fff) << 16 | (crtc_x & 0x3fff);
579 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
580
581 /* apply changes */
582 tegra_dc_cursor_commit(dc);
583 tegra_dc_commit(dc);
584
585 return 0;
586}
587
588static int tegra_cursor_plane_disable(struct drm_plane *plane)
589{
590 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
591 u32 value;
592
593 if (!plane->crtc)
594 return 0;
595
596 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
597 value &= ~CURSOR_ENABLE;
598 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
599
600 tegra_dc_cursor_commit(dc);
601 tegra_dc_commit(dc);
602
603 return 0;
604}
605
606static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
607 .update_plane = tegra_cursor_plane_update,
608 .disable_plane = tegra_cursor_plane_disable,
609 .destroy = tegra_plane_destroy,
610};
611
612static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
613 struct tegra_dc *dc)
614{
615 struct tegra_plane *plane;
616 unsigned int num_formats;
617 const u32 *formats;
618 int err;
619
620 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
621 if (!plane)
622 return ERR_PTR(-ENOMEM);
623
624 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
625 formats = tegra_cursor_plane_formats;
626
627 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
628 &tegra_cursor_plane_funcs, formats,
629 num_formats, DRM_PLANE_TYPE_CURSOR);
630 if (err < 0) {
631 kfree(plane);
632 return ERR_PTR(err);
633 }
634
635 return &plane->base;
636}
637
638static int tegra_overlay_plane_update(struct drm_plane *plane,
639 struct drm_crtc *crtc,
640 struct drm_framebuffer *fb, int crtc_x,
641 int crtc_y, unsigned int crtc_w,
642 unsigned int crtc_h, uint32_t src_x,
643 uint32_t src_y, uint32_t src_w,
644 uint32_t src_h)
f34bc787
TR		 645{
646 struct tegra_plane *p = to_tegra_plane(plane);
647 struct tegra_dc *dc = to_tegra_dc(crtc);
648 struct tegra_dc_window window;
649 unsigned int i;
c134f019 650 int err;
f34bc787
TR		 651
652 memset(&window, 0, sizeof(window));
653 window.src.x = src_x >> 16;
654 window.src.y = src_y >> 16;
655 window.src.w = src_w >> 16;
656 window.src.h = src_h >> 16;
657 window.dst.x = crtc_x;
658 window.dst.y = crtc_y;
659 window.dst.w = crtc_w;
660 window.dst.h = crtc_h;
f925390e 661 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
f34bc787 662 window.bits_per_pixel = fb->bits_per_pixel;
db7fbdfd 663 window.bottom_up = tegra_fb_is_bottom_up(fb);
c134f019
TR		 664
665 err = tegra_fb_get_tiling(fb, &window.tiling);
666 if (err < 0)
667 return err;
f34bc787
TR		 668
669 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 670 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 671
de2ba664 672 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 673
674 /*
675 * Tegra doesn't support different strides for U and V planes
676 * so we display a warning if the user tries to display a
677 * framebuffer with such a configuration.
678 */
679 if (i >= 2) {
680 if (fb->pitches[i] != window.stride[1])
681 DRM_ERROR("unsupported UV-plane configuration\n");
682 } else {
683 window.stride[i] = fb->pitches[i];
684 }
685 }
686
687 return tegra_dc_setup_window(dc, p->index, &window);
688}
689
c7679306 690static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 691{
c7679306
TR		 692 tegra_window_plane_disable(plane);
693 tegra_plane_destroy(plane);
f34bc787
TR		 694}
695
c7679306
TR		 696static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
697 .update_plane = tegra_overlay_plane_update,
698 .disable_plane = tegra_window_plane_disable,
699 .destroy = tegra_overlay_plane_destroy,
f34bc787
TR		 700};
701
c7679306 702static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 703 DRM_FORMAT_XBGR8888,
f34bc787 704 DRM_FORMAT_XRGB8888,
dbe4d9a7 705 DRM_FORMAT_RGB565,
f34bc787 706 DRM_FORMAT_UYVY,
f925390e 707 DRM_FORMAT_YUYV,
f34bc787
TR		 708 DRM_FORMAT_YUV420,
709 DRM_FORMAT_YUV422,
710};
711
c7679306
TR		 712static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
713 struct tegra_dc *dc,
714 unsigned int index)
f34bc787 715{
c7679306
TR		 716 struct tegra_plane *plane;
717 unsigned int num_formats;
718 const u32 *formats;
719 int err;
f34bc787 720
c7679306
TR		 721 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
722 if (!plane)
723 return ERR_PTR(-ENOMEM);
f34bc787 724
c7679306 725 plane->index = index;
f34bc787 726
c7679306
TR		 727 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
728 formats = tegra_overlay_plane_formats;
f34bc787 729
c7679306
TR		 730 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
731 &tegra_overlay_plane_funcs, formats,
732 num_formats, DRM_PLANE_TYPE_OVERLAY);
733 if (err < 0) {
734 kfree(plane);
735 return ERR_PTR(err);
736 }
737
738 return &plane->base;
739}
740
741static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
742{
743 struct drm_plane *plane;
744 unsigned int i;
745
746 for (i = 0; i < 2; i++) {
747 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
748 if (IS_ERR(plane))
749 return PTR_ERR(plane);
f34bc787
TR		 750 }
751
752 return 0;
753}
754
23fb4740
TR		 755static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
756 struct drm_framebuffer *fb)
757{
de2ba664 758 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
db7fbdfd 759 unsigned int h_offset = 0, v_offset = 0;
c134f019 760 struct tegra_bo_tiling tiling;
93396d0f 761 unsigned long value, flags;
f925390e 762 unsigned int format, swap;
c134f019
TR		 763 int err;
764
765 err = tegra_fb_get_tiling(fb, &tiling);
766 if (err < 0)
767 return err;
23fb4740 768
93396d0f
SP		 769 spin_lock_irqsave(&dc->lock, flags);
770
23fb4740
TR		 771 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
772
773 value = fb->offsets[0] + y * fb->pitches[0] +
774 x * fb->bits_per_pixel / 8;
775
de2ba664 776 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 777 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
f925390e
TR		 778
779 format = tegra_dc_format(fb->pixel_format, &swap);
ed683aea 780 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
f925390e 781 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
23fb4740 782
c134f019
TR		 783 if (dc->soc->supports_block_linear) {
784 unsigned long height = tiling.value;
785
786 switch (tiling.mode) {
787 case TEGRA_BO_TILING_MODE_PITCH:
788 value = DC_WINBUF_SURFACE_KIND_PITCH;
789 break;
790
791 case TEGRA_BO_TILING_MODE_TILED:
792 value = DC_WINBUF_SURFACE_KIND_TILED;
793 break;
794
795 case TEGRA_BO_TILING_MODE_BLOCK:
796 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
797 DC_WINBUF_SURFACE_KIND_BLOCK;
798 break;
799 }
800
801 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
773af77f 802 } else {
c134f019
TR		 803 switch (tiling.mode) {
804 case TEGRA_BO_TILING_MODE_PITCH:
805 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
806 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
807 break;
773af77f 808
c134f019
TR		 809 case TEGRA_BO_TILING_MODE_TILED:
810 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
811 DC_WIN_BUFFER_ADDR_MODE_TILE;
812 break;
813
814 case TEGRA_BO_TILING_MODE_BLOCK:
815 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 816 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 817 return -EINVAL;
818 }
819
820 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
821 }
773af77f 822
db7fbdfd
TR		 823 /* make sure bottom-up buffers are properly displayed */
824 if (tegra_fb_is_bottom_up(fb)) {
825 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 826 value |= V_DIRECTION;
db7fbdfd
TR		 827 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
828
829 v_offset += fb->height - 1;
830 } else {
831 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 832 value &= ~V_DIRECTION;
db7fbdfd
TR		 833 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
834 }
835
836 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
837 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
838
23fb4740 839 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
205d48ed 840 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
23fb4740
TR		 841 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
842
93396d0f
SP		 843 spin_unlock_irqrestore(&dc->lock, flags);
844
23fb4740
TR		 845 return 0;
846}
847
6e5ff998
TR		 848void tegra_dc_enable_vblank(struct tegra_dc *dc)
849{
850 unsigned long value, flags;
851
852 spin_lock_irqsave(&dc->lock, flags);
853
854 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
855 value |= VBLANK_INT;
856 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
857
858 spin_unlock_irqrestore(&dc->lock, flags);
859}
860
861void tegra_dc_disable_vblank(struct tegra_dc *dc)
862{
863 unsigned long value, flags;
864
865 spin_lock_irqsave(&dc->lock, flags);
866
867 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
868 value &= ~VBLANK_INT;
869 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
870
871 spin_unlock_irqrestore(&dc->lock, flags);
872}
873
3c03c46a
TR		 874static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
875{
876 struct drm_device *drm = dc->base.dev;
877 struct drm_crtc *crtc = &dc->base;
3c03c46a 878 unsigned long flags, base;
de2ba664 879 struct tegra_bo *bo;
3c03c46a 880
6b59cc1c
TR		 881 spin_lock_irqsave(&drm->event_lock, flags);
882
883 if (!dc->event) {
884 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 885 return;
6b59cc1c 886 }
3c03c46a 887
f4510a27 888 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 889
8643bc6d 890 spin_lock(&dc->lock);
93396d0f 891
3c03c46a 892 /* check if new start address has been latched */
93396d0f 893 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 894 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
895 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
896 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
897
8643bc6d 898 spin_unlock(&dc->lock);
93396d0f 899
f4510a27 900 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 901 drm_crtc_send_vblank_event(crtc, dc->event);
902 drm_crtc_vblank_put(crtc);
3c03c46a 903 dc->event = NULL;
3c03c46a 904 }
6b59cc1c
TR		 905
906 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 907}
908
909void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
910{
911 struct tegra_dc *dc = to_tegra_dc(crtc);
912 struct drm_device *drm = crtc->dev;
913 unsigned long flags;
914
915 spin_lock_irqsave(&drm->event_lock, flags);
916
917 if (dc->event && dc->event->base.file_priv == file) {
918 dc->event->base.destroy(&dc->event->base);
ed7dae58 919 drm_crtc_vblank_put(crtc);
3c03c46a
TR		 920 dc->event = NULL;
921 }
922
923 spin_unlock_irqrestore(&drm->event_lock, flags);
924}
925
926static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 927 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a 928{
ed7dae58 929 unsigned int pipe = drm_crtc_index(crtc);
3c03c46a 930 struct tegra_dc *dc = to_tegra_dc(crtc);
3c03c46a
TR		 931
932 if (dc->event)
933 return -EBUSY;
934
935 if (event) {
ed7dae58 936 event->pipe = pipe;
3c03c46a 937 dc->event = event;
ed7dae58 938 drm_crtc_vblank_get(crtc);
3c03c46a
TR		 939 }
940
941 tegra_dc_set_base(dc, 0, 0, fb);
f4510a27 942 crtc->primary->fb = fb;
3c03c46a
TR		 943
944 return 0;
945}
946
f002abc1
TR		 947static void tegra_dc_destroy(struct drm_crtc *crtc)
948{
949 drm_crtc_cleanup(crtc);
f002abc1
TR		 950}
951
d8f4a9ed 952static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 953 .page_flip = tegra_dc_page_flip,
d8f4a9ed 954 .set_config = drm_crtc_helper_set_config,
f002abc1 955 .destroy = tegra_dc_destroy,
d8f4a9ed
TR		 956};
957
86df256f
TR		 958static void tegra_dc_stop(struct tegra_dc *dc)
959{
960 u32 value;
961
962 /* stop the display controller */
963 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
964 value &= ~DISP_CTRL_MODE_MASK;
965 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
966
967 tegra_dc_commit(dc);
968}
969
970static bool tegra_dc_idle(struct tegra_dc *dc)
971{
972 u32 value;
973
974 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
975
976 return (value & DISP_CTRL_MODE_MASK) == 0;
977}
978
979static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
980{
981 timeout = jiffies + msecs_to_jiffies(timeout);
982
983 while (time_before(jiffies, timeout)) {
984 if (tegra_dc_idle(dc))
985 return 0;
986
987 usleep_range(1000, 2000);
988 }
989
990 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
991 return -ETIMEDOUT;
992}
993
f34bc787 994static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 995{
f002abc1 996 struct tegra_dc *dc = to_tegra_dc(crtc);
3b0e5855 997 u32 value;
f002abc1 998
86df256f
TR		 999 if (!tegra_dc_idle(dc)) {
1000 tegra_dc_stop(dc);
1001
1002 /*
1003 * Ignore the return value, there isn't anything useful to do
1004 * in case this fails.
1005 */
1006 tegra_dc_wait_idle(dc, 100);
1007 }
36904adf 1008
3b0e5855
TR		 1009 /*
1010 * This should really be part of the RGB encoder driver, but clearing
1011 * these bits has the side-effect of stopping the display controller.
1012 * When that happens no VBLANK interrupts will be raised. At the same
1013 * time the encoder is disabled before the display controller, so the
1014 * above code is always going to timeout waiting for the controller
1015 * to go idle.
1016 *
1017 * Given the close coupling between the RGB encoder and the display
1018 * controller doing it here is still kind of okay. None of the other
1019 * encoder drivers require these bits to be cleared.
1020 *
1021 * XXX: Perhaps given that the display controller is switched off at
1022 * this point anyway maybe clearing these bits isn't even useful for
1023 * the RGB encoder?
1024 */
1025 if (dc->rgb) {
1026 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1027 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1028 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1029 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1030 }
1031
8ff64c17 1032 drm_crtc_vblank_off(crtc);
c7679306 1033 tegra_dc_commit(dc);
d8f4a9ed
TR		 1034}
1035
1036static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
1037 const struct drm_display_mode *mode,
1038 struct drm_display_mode *adjusted)
1039{
1040 return true;
1041}
1042
d8f4a9ed
TR		 1043static int tegra_dc_set_timings(struct tegra_dc *dc,
1044 struct drm_display_mode *mode)
1045{
0444c0ff
TR		 1046 unsigned int h_ref_to_sync = 1;
1047 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 1048 unsigned long value;
1049
1050 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1051
1052 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1053 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1054
1055 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1056 ((mode->hsync_end - mode->hsync_start) << 0);
1057 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1058
d8f4a9ed
TR		 1059 value = ((mode->vtotal - mode->vsync_end) << 16) |
1060 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 1061 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1062
1063 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1064 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 1065 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1066
1067 value = (mode->vdisplay << 16) | mode->hdisplay;
1068 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1069
1070 return 0;
1071}
1072
c5a107d3
TR		 1073int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent,
1074 unsigned long pclk, unsigned int div)
1075{
1076 u32 value;
1077 int err;
1078
1079 err = clk_set_parent(dc->clk, parent);
1080 if (err < 0) {
1081 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1082 return err;
1083 }
1084
1085 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
1086
1087 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
1088 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1089
1090 return 0;
1091}
1092
d8f4a9ed
TR		 1093static int tegra_crtc_mode_set(struct drm_crtc *crtc,
1094 struct drm_display_mode *mode,
1095 struct drm_display_mode *adjusted,
1096 int x, int y, struct drm_framebuffer *old_fb)
1097{
f4510a27 1098 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
d8f4a9ed 1099 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 1100 struct tegra_dc_window window;
dbb3f2f7 1101 u32 value;
d8f4a9ed
TR		 1102 int err;
1103
d8f4a9ed
TR		 1104 /* program display mode */
1105 tegra_dc_set_timings(dc, mode);
1106
42d0659b
TR		 1107 if (dc->soc->supports_border_color)
1108 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1109
8620fc62
TR		 1110 /* interlacing isn't supported yet, so disable it */
1111 if (dc->soc->supports_interlacing) {
1112 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1113 value &= ~INTERLACE_ENABLE;
1114 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1115 }
1116
d8f4a9ed 1117 /* setup window parameters */
f34bc787
TR		 1118 memset(&window, 0, sizeof(window));
1119 window.src.x = 0;
1120 window.src.y = 0;
1121 window.src.w = mode->hdisplay;
1122 window.src.h = mode->vdisplay;
1123 window.dst.x = 0;
1124 window.dst.y = 0;
1125 window.dst.w = mode->hdisplay;
1126 window.dst.h = mode->vdisplay;
f925390e
TR		 1127 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
1128 &window.swap);
f4510a27
MR		 1129 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
1130 window.stride[0] = crtc->primary->fb->pitches[0];
de2ba664 1131 window.base[0] = bo->paddr;
f34bc787
TR		 1132
1133 err = tegra_dc_setup_window(dc, 0, &window);
1134 if (err < 0)
1135 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 1136
d8f4a9ed
TR		 1137 return 0;
1138}
d8f4a9ed 1139
23fb4740
TR		 1140static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1141 struct drm_framebuffer *old_fb)
1142{
1143 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1144
f4510a27 1145 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
d8f4a9ed
TR		 1146}
1147
1148static void tegra_crtc_prepare(struct drm_crtc *crtc)
1149{
1150 struct tegra_dc *dc = to_tegra_dc(crtc);
1151 unsigned int syncpt;
1152 unsigned long value;
1153
8ff64c17
TR		 1154 drm_crtc_vblank_off(crtc);
1155
d8f4a9ed
TR		 1156 if (dc->pipe)
1157 syncpt = SYNCPT_VBLANK1;
1158 else
1159 syncpt = SYNCPT_VBLANK0;
1160
1161 /* initialize display controller */
1162 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1163 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1164
1165 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1166 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1167
1168 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1169 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1170 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1171
d8f4a9ed
TR		 1172 /* initialize timer */
1173 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1174 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1175 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1176
1177 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1178 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1179 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1180
d8f4a9ed
TR		 1181 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1182 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 1183
1184 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1185 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 1186}
1187
1188static void tegra_crtc_commit(struct drm_crtc *crtc)
1189{
1190 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1191
8ff64c17 1192 drm_crtc_vblank_on(crtc);
205d48ed 1193 tegra_dc_commit(dc);
d8f4a9ed
TR		 1194}
1195
d8f4a9ed 1196static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1197 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 1198 .mode_fixup = tegra_crtc_mode_fixup,
1199 .mode_set = tegra_crtc_mode_set,
23fb4740 1200 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 1201 .prepare = tegra_crtc_prepare,
1202 .commit = tegra_crtc_commit,
d8f4a9ed
TR		 1203};
1204
6e5ff998 1205static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1206{
1207 struct tegra_dc *dc = data;
1208 unsigned long status;
1209
1210 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1211 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1212
1213 if (status & FRAME_END_INT) {
1214 /*
1215 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1216 */
1217 }
1218
1219 if (status & VBLANK_INT) {
1220 /*
1221 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1222 */
ed7dae58 1223 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1224 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 1225 }
1226
1227 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1228 /*
1229 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1230 */
1231 }
1232
1233 return IRQ_HANDLED;
1234}
1235
1236static int tegra_dc_show_regs(struct seq_file *s, void *data)
1237{
1238 struct drm_info_node *node = s->private;
1239 struct tegra_dc *dc = node->info_ent->data;
1240
1241#define DUMP_REG(name) \
03a60569 1242 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1243 tegra_dc_readl(dc, name))
1244
1245 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1246 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1247 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1248 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1249 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1250 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1251 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1252 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1253 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1254 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1255 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1256 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1257 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1258 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1259 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1260 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1261 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1262 DUMP_REG(DC_CMD_INT_STATUS);
1263 DUMP_REG(DC_CMD_INT_MASK);
1264 DUMP_REG(DC_CMD_INT_ENABLE);
1265 DUMP_REG(DC_CMD_INT_TYPE);
1266 DUMP_REG(DC_CMD_INT_POLARITY);
1267 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1268 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1269 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1270 DUMP_REG(DC_CMD_STATE_ACCESS);
1271 DUMP_REG(DC_CMD_STATE_CONTROL);
1272 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1273 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1274 DUMP_REG(DC_COM_CRC_CONTROL);
1275 DUMP_REG(DC_COM_CRC_CHECKSUM);
1276 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1277 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1278 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1279 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1280 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1281 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1282 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1283 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1284 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1285 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1286 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1287 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1288 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1289 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1290 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1291 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1292 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1293 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1294 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1295 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1296 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1297 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1298 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1299 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1300 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1301 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1302 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1303 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1304 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1305 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1306 DUMP_REG(DC_COM_SPI_CONTROL);
1307 DUMP_REG(DC_COM_SPI_START_BYTE);
1308 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1309 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1310 DUMP_REG(DC_COM_HSPI_CS_DC);
1311 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1312 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1313 DUMP_REG(DC_COM_GPIO_CTRL);
1314 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1315 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1316 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1317 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1318 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1319 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1320 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1321 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1322 DUMP_REG(DC_DISP_REF_TO_SYNC);
1323 DUMP_REG(DC_DISP_SYNC_WIDTH);
1324 DUMP_REG(DC_DISP_BACK_PORCH);
1325 DUMP_REG(DC_DISP_ACTIVE);
1326 DUMP_REG(DC_DISP_FRONT_PORCH);
1327 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1328 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1329 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1330 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1331 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1332 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1333 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1334 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1335 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1336 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1337 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1338 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1339 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1340 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1341 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1342 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1343 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1344 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1345 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1346 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1347 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1348 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1349 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1350 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1351 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1352 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1353 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1354 DUMP_REG(DC_DISP_M0_CONTROL);
1355 DUMP_REG(DC_DISP_M1_CONTROL);
1356 DUMP_REG(DC_DISP_DI_CONTROL);
1357 DUMP_REG(DC_DISP_PP_CONTROL);
1358 DUMP_REG(DC_DISP_PP_SELECT_A);
1359 DUMP_REG(DC_DISP_PP_SELECT_B);
1360 DUMP_REG(DC_DISP_PP_SELECT_C);
1361 DUMP_REG(DC_DISP_PP_SELECT_D);
1362 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1363 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1364 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1365 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1366 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1367 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1368 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1369 DUMP_REG(DC_DISP_BORDER_COLOR);
1370 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1371 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1372 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1373 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1374 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1375 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1376 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1377 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1378 DUMP_REG(DC_DISP_CURSOR_POSITION);
1379 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1380 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1381 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1382 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1383 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1384 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1385 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1386 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1387 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1388 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1389 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1390 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1391 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1392 DUMP_REG(DC_DISP_SD_CONTROL);
1393 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1394 DUMP_REG(DC_DISP_SD_LUT(0));
1395 DUMP_REG(DC_DISP_SD_LUT(1));
1396 DUMP_REG(DC_DISP_SD_LUT(2));
1397 DUMP_REG(DC_DISP_SD_LUT(3));
1398 DUMP_REG(DC_DISP_SD_LUT(4));
1399 DUMP_REG(DC_DISP_SD_LUT(5));
1400 DUMP_REG(DC_DISP_SD_LUT(6));
1401 DUMP_REG(DC_DISP_SD_LUT(7));
1402 DUMP_REG(DC_DISP_SD_LUT(8));
1403 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1404 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1405 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1406 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1407 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1408 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1409 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1410 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1411 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1412 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1413 DUMP_REG(DC_DISP_SD_BL_TF(0));
1414 DUMP_REG(DC_DISP_SD_BL_TF(1));
1415 DUMP_REG(DC_DISP_SD_BL_TF(2));
1416 DUMP_REG(DC_DISP_SD_BL_TF(3));
1417 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1418 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1419 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1420 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1421 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1422 DUMP_REG(DC_WIN_WIN_OPTIONS);
1423 DUMP_REG(DC_WIN_BYTE_SWAP);
1424 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1425 DUMP_REG(DC_WIN_COLOR_DEPTH);
1426 DUMP_REG(DC_WIN_POSITION);
1427 DUMP_REG(DC_WIN_SIZE);
1428 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1429 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1430 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1431 DUMP_REG(DC_WIN_DDA_INC);
1432 DUMP_REG(DC_WIN_LINE_STRIDE);
1433 DUMP_REG(DC_WIN_BUF_STRIDE);
1434 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1435 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1436 DUMP_REG(DC_WIN_DV_CONTROL);
1437 DUMP_REG(DC_WIN_BLEND_NOKEY);
1438 DUMP_REG(DC_WIN_BLEND_1WIN);
1439 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1440 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1441 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1442 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1443 DUMP_REG(DC_WINBUF_START_ADDR);
1444 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1445 DUMP_REG(DC_WINBUF_START_ADDR_U);
1446 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1447 DUMP_REG(DC_WINBUF_START_ADDR_V);
1448 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1449 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1450 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1451 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1452 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1453 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1454 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1455 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1456 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1457
1458#undef DUMP_REG
1459
1460 return 0;
1461}
1462
1463static struct drm_info_list debugfs_files[] = {
1464 { "regs", tegra_dc_show_regs, 0, NULL },
1465};
1466
1467static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1468{
1469 unsigned int i;
1470 char *name;
1471 int err;
1472
1473 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1474 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1475 kfree(name);
1476
1477 if (!dc->debugfs)
1478 return -ENOMEM;
1479
1480 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1481 GFP_KERNEL);
1482 if (!dc->debugfs_files) {
1483 err = -ENOMEM;
1484 goto remove;
1485 }
1486
1487 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1488 dc->debugfs_files[i].data = dc;
1489
1490 err = drm_debugfs_create_files(dc->debugfs_files,
1491 ARRAY_SIZE(debugfs_files),
1492 dc->debugfs, minor);
1493 if (err < 0)
1494 goto free;
1495
1496 dc->minor = minor;
1497
1498 return 0;
1499
1500free:
1501 kfree(dc->debugfs_files);
1502 dc->debugfs_files = NULL;
1503remove:
1504 debugfs_remove(dc->debugfs);
1505 dc->debugfs = NULL;
1506
1507 return err;
1508}
1509
1510static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1511{
1512 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1513 dc->minor);
1514 dc->minor = NULL;
1515
1516 kfree(dc->debugfs_files);
1517 dc->debugfs_files = NULL;
1518
1519 debugfs_remove(dc->debugfs);
1520 dc->debugfs = NULL;
1521
1522 return 0;
1523}
1524
53fa7f72 1525static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1526{
9910f5c4 1527 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1528 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1529 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1530 struct drm_plane *primary = NULL;
1531 struct drm_plane *cursor = NULL;
d8f4a9ed
TR		 1532 int err;
1533
df06b759
TR		 1534 if (tegra->domain) {
1535 err = iommu_attach_device(tegra->domain, dc->dev);
1536 if (err < 0) {
1537 dev_err(dc->dev, "failed to attach to domain: %d\n",
1538 err);
1539 return err;
1540 }
1541
1542 dc->domain = tegra->domain;
1543 }
1544
c7679306
TR		 1545 primary = tegra_dc_primary_plane_create(drm, dc);
1546 if (IS_ERR(primary)) {
1547 err = PTR_ERR(primary);
1548 goto cleanup;
1549 }
1550
1551 if (dc->soc->supports_cursor) {
1552 cursor = tegra_dc_cursor_plane_create(drm, dc);
1553 if (IS_ERR(cursor)) {
1554 err = PTR_ERR(cursor);
1555 goto cleanup;
1556 }
1557 }
1558
1559 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1560 &tegra_crtc_funcs);
1561 if (err < 0)
1562 goto cleanup;
1563
d8f4a9ed
TR		 1564 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1565 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1566
d1f3e1e0
TR		 1567 /*
1568 * Keep track of the minimum pitch alignment across all display
1569 * controllers.
1570 */
1571 if (dc->soc->pitch_align > tegra->pitch_align)
1572 tegra->pitch_align = dc->soc->pitch_align;
1573
9910f5c4 1574 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1575 if (err < 0 && err != -ENODEV) {
1576 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1577 goto cleanup;
d8f4a9ed
TR		 1578 }
1579
9910f5c4 1580 err = tegra_dc_add_planes(drm, dc);
f34bc787 1581 if (err < 0)
c7679306 1582 goto cleanup;
f34bc787 1583
d8f4a9ed 1584 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1585 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1586 if (err < 0)
1587 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1588 }
1589
6e5ff998 1590 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1591 dev_name(dc->dev), dc);
1592 if (err < 0) {
1593 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1594 err);
c7679306 1595 goto cleanup;
d8f4a9ed
TR		 1596 }
1597
1598 return 0;
c7679306
TR		 1599
1600cleanup:
1601 if (cursor)
1602 drm_plane_cleanup(cursor);
1603
1604 if (primary)
1605 drm_plane_cleanup(primary);
1606
1607 if (tegra->domain) {
1608 iommu_detach_device(tegra->domain, dc->dev);
1609 dc->domain = NULL;
1610 }
1611
1612 return err;
d8f4a9ed
TR		 1613}
1614
53fa7f72 1615static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1616{
776dc384 1617 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1618 int err;
1619
1620 devm_free_irq(dc->dev, dc->irq, dc);
1621
1622 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1623 err = tegra_dc_debugfs_exit(dc);
1624 if (err < 0)
1625 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1626 }
1627
1628 err = tegra_dc_rgb_exit(dc);
1629 if (err) {
1630 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1631 return err;
1632 }
1633
df06b759
TR		 1634 if (dc->domain) {
1635 iommu_detach_device(dc->domain, dc->dev);
1636 dc->domain = NULL;
1637 }
1638
d8f4a9ed
TR		 1639 return 0;
1640}
1641
1642static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1643 .init = tegra_dc_init,
1644 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1645};
1646
8620fc62 1647static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1648 .supports_border_color = true,
8620fc62 1649 .supports_interlacing = false,
e687651b 1650 .supports_cursor = false,
c134f019 1651 .supports_block_linear = false,
d1f3e1e0 1652 .pitch_align = 8,
9c012700 1653 .has_powergate = false,
8620fc62
TR		 1654};
1655
1656static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1657 .supports_border_color = true,
8620fc62 1658 .supports_interlacing = false,
e687651b 1659 .supports_cursor = false,
c134f019 1660 .supports_block_linear = false,
d1f3e1e0 1661 .pitch_align = 8,
9c012700 1662 .has_powergate = false,
d1f3e1e0
TR		 1663};
1664
1665static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1666 .supports_border_color = true,
d1f3e1e0
TR		 1667 .supports_interlacing = false,
1668 .supports_cursor = false,
1669 .supports_block_linear = false,
1670 .pitch_align = 64,
9c012700 1671 .has_powergate = true,
8620fc62
TR		 1672};
1673
1674static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1675 .supports_border_color = false,
8620fc62 1676 .supports_interlacing = true,
e687651b 1677 .supports_cursor = true,
c134f019 1678 .supports_block_linear = true,
d1f3e1e0 1679 .pitch_align = 64,
9c012700 1680 .has_powergate = true,
8620fc62
TR		 1681};
1682
1683static const struct of_device_id tegra_dc_of_match[] = {
1684 {
1685 .compatible = "nvidia,tegra124-dc",
1686 .data = &tegra124_dc_soc_info,
9c012700
TR		 1687 }, {
1688 .compatible = "nvidia,tegra114-dc",
1689 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1690 }, {
1691 .compatible = "nvidia,tegra30-dc",
1692 .data = &tegra30_dc_soc_info,
1693 }, {
1694 .compatible = "nvidia,tegra20-dc",
1695 .data = &tegra20_dc_soc_info,
1696 }, {
1697 /* sentinel */
1698 }
1699};
ef70728c 1700MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1701
13411ddd
TR		 1702static int tegra_dc_parse_dt(struct tegra_dc *dc)
1703{
1704 struct device_node *np;
1705 u32 value = 0;
1706 int err;
1707
1708 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1709 if (err < 0) {
1710 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1711
1712 /*
1713 * If the nvidia,head property isn't present, try to find the
1714 * correct head number by looking up the position of this
1715 * display controller's node within the device tree. Assuming
1716 * that the nodes are ordered properly in the DTS file and
1717 * that the translation into a flattened device tree blob
1718 * preserves that ordering this will actually yield the right
1719 * head number.
1720 *
1721 * If those assumptions don't hold, this will still work for
1722 * cases where only a single display controller is used.
1723 */
1724 for_each_matching_node(np, tegra_dc_of_match) {
1725 if (np == dc->dev->of_node)
1726 break;
1727
1728 value++;
1729 }
1730 }
1731
1732 dc->pipe = value;
1733
1734 return 0;
1735}
1736
d8f4a9ed
TR		 1737static int tegra_dc_probe(struct platform_device *pdev)
1738{
8620fc62 1739 const struct of_device_id *id;
d8f4a9ed
TR		 1740 struct resource *regs;
1741 struct tegra_dc *dc;
1742 int err;
1743
1744 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1745 if (!dc)
1746 return -ENOMEM;
1747
8620fc62
TR		 1748 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1749 if (!id)
1750 return -ENODEV;
1751
6e5ff998 1752 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1753 INIT_LIST_HEAD(&dc->list);
1754 dc->dev = &pdev->dev;
8620fc62 1755 dc->soc = id->data;
d8f4a9ed 1756
13411ddd
TR		 1757 err = tegra_dc_parse_dt(dc);
1758 if (err < 0)
1759 return err;
1760
d8f4a9ed
TR		 1761 dc->clk = devm_clk_get(&pdev->dev, NULL);
1762 if (IS_ERR(dc->clk)) {
1763 dev_err(&pdev->dev, "failed to get clock\n");
1764 return PTR_ERR(dc->clk);
1765 }
1766
ca48080a
SW		 1767 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1768 if (IS_ERR(dc->rst)) {
1769 dev_err(&pdev->dev, "failed to get reset\n");
1770 return PTR_ERR(dc->rst);
1771 }
1772
9c012700
TR		 1773 if (dc->soc->has_powergate) {
1774 if (dc->pipe == 0)
1775 dc->powergate = TEGRA_POWERGATE_DIS;
1776 else
1777 dc->powergate = TEGRA_POWERGATE_DISB;
1778
1779 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1780 dc->rst);
1781 if (err < 0) {
1782 dev_err(&pdev->dev, "failed to power partition: %d\n",
1783 err);
1784 return err;
1785 }
1786 } else {
1787 err = clk_prepare_enable(dc->clk);
1788 if (err < 0) {
1789 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1790 err);
1791 return err;
1792 }
1793
1794 err = reset_control_deassert(dc->rst);
1795 if (err < 0) {
1796 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1797 err);
1798 return err;
1799 }
1800 }
d8f4a9ed
TR		 1801
1802 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1803 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1804 if (IS_ERR(dc->regs))
1805 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1806
1807 dc->irq = platform_get_irq(pdev, 0);
1808 if (dc->irq < 0) {
1809 dev_err(&pdev->dev, "failed to get IRQ\n");
1810 return -ENXIO;
1811 }
1812
776dc384
TR		 1813 INIT_LIST_HEAD(&dc->client.list);
1814 dc->client.ops = &dc_client_ops;
1815 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1816
1817 err = tegra_dc_rgb_probe(dc);
1818 if (err < 0 && err != -ENODEV) {
1819 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1820 return err;
1821 }
1822
776dc384 1823 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1824 if (err < 0) {
1825 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1826 err);
1827 return err;
1828 }
1829
1830 platform_set_drvdata(pdev, dc);
1831
1832 return 0;
1833}
1834
1835static int tegra_dc_remove(struct platform_device *pdev)
1836{
d8f4a9ed
TR		 1837 struct tegra_dc *dc = platform_get_drvdata(pdev);
1838 int err;
1839
776dc384 1840 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1841 if (err < 0) {
1842 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1843 err);
1844 return err;
1845 }
1846
59d29c0e
TR		 1847 err = tegra_dc_rgb_remove(dc);
1848 if (err < 0) {
1849 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1850 return err;
1851 }
1852
5482d75a 1853 reset_control_assert(dc->rst);
9c012700
TR		 1854
1855 if (dc->soc->has_powergate)
1856 tegra_powergate_power_off(dc->powergate);
1857
d8f4a9ed
TR		 1858 clk_disable_unprepare(dc->clk);
1859
1860 return 0;
1861}
1862
d8f4a9ed
TR		 1863struct platform_driver tegra_dc_driver = {
1864 .driver = {
1865 .name = "tegra-dc",
1866 .owner = THIS_MODULE,
1867 .of_match_table = tegra_dc_of_match,
1868 },
1869 .probe = tegra_dc_probe,
1870 .remove = tegra_dc_remove,
1871};
Linux kernel - Deliverables
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