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Linux 4.0-rc2
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
ca48080a 13#include <linux/reset.h>
d8f4a9ed 14
9c012700
TR		 15#include <soc/tegra/pmc.h>
16
de2ba664
AM		 17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
d8f4a9ed 20
9d44189f 21#include <drm/drm_atomic.h>
4aa3df71 22#include <drm/drm_atomic_helper.h>
3cb9ae4f
DV		 23#include <drm/drm_plane_helper.h>
24
8620fc62 25struct tegra_dc_soc_info {
42d0659b 26 bool supports_border_color;
8620fc62 27 bool supports_interlacing;
e687651b 28 bool supports_cursor;
c134f019 29 bool supports_block_linear;
d1f3e1e0 30 unsigned int pitch_align;
9c012700 31 bool has_powergate;
8620fc62
TR		 32};
33
f34bc787
TR		 34struct tegra_plane {
35 struct drm_plane base;
36 unsigned int index;
d8f4a9ed
TR		 37};
38
f34bc787
TR		 39static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
40{
41 return container_of(plane, struct tegra_plane, base);
42}
43
ca915b10
TR		 44struct tegra_dc_state {
45 struct drm_crtc_state base;
46
47 struct clk *clk;
48 unsigned long pclk;
49 unsigned int div;
47802b09
TR		 50
51 u32 planes;
ca915b10
TR		 52};
53
54static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
55{
56 if (state)
57 return container_of(state, struct tegra_dc_state, base);
58
59 return NULL;
60}
61
8f604f8c
TR		 62struct tegra_plane_state {
63 struct drm_plane_state base;
64
65 struct tegra_bo_tiling tiling;
66 u32 format;
67 u32 swap;
68};
69
70static inline struct tegra_plane_state *
71to_tegra_plane_state(struct drm_plane_state *state)
72{
73 if (state)
74 return container_of(state, struct tegra_plane_state, base);
75
76 return NULL;
77}
78
86df256f
TR		 79/*
80 * Reads the active copy of a register. This takes the dc->lock spinlock to
81 * prevent races with the VBLANK processing which also needs access to the
82 * active copy of some registers.
83 */
84static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
85{
86 unsigned long flags;
87 u32 value;
88
89 spin_lock_irqsave(&dc->lock, flags);
90
91 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
92 value = tegra_dc_readl(dc, offset);
93 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
94
95 spin_unlock_irqrestore(&dc->lock, flags);
96 return value;
97}
98
d700ba7a
TR		 99/*
100 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
101 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
102 * Latching happens mmediately if the display controller is in STOP mode or
103 * on the next frame boundary otherwise.
104 *
105 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
106 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
107 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
108 * into the ACTIVE copy, either immediately if the display controller is in
109 * STOP mode, or at the next frame boundary otherwise.
110 */
62b9e063 111void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 112{
113 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
114 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
115}
116
8f604f8c 117static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
10288eea
TR		 118{
119 /* assume no swapping of fetched data */
120 if (swap)
121 *swap = BYTE_SWAP_NOSWAP;
122
8f604f8c 123 switch (fourcc) {
10288eea 124 case DRM_FORMAT_XBGR8888:
8f604f8c
TR		 125 *format = WIN_COLOR_DEPTH_R8G8B8A8;
126 break;
10288eea
TR		 127
128 case DRM_FORMAT_XRGB8888:
8f604f8c
TR		 129 *format = WIN_COLOR_DEPTH_B8G8R8A8;
130 break;
10288eea
TR		 131
132 case DRM_FORMAT_RGB565:
8f604f8c
TR		 133 *format = WIN_COLOR_DEPTH_B5G6R5;
134 break;
10288eea
TR		 135
136 case DRM_FORMAT_UYVY:
8f604f8c
TR		 137 *format = WIN_COLOR_DEPTH_YCbCr422;
138 break;
10288eea
TR		 139
140 case DRM_FORMAT_YUYV:
141 if (swap)
142 *swap = BYTE_SWAP_SWAP2;
143
8f604f8c
TR		 144 *format = WIN_COLOR_DEPTH_YCbCr422;
145 break;
10288eea
TR		 146
147 case DRM_FORMAT_YUV420:
8f604f8c
TR		 148 *format = WIN_COLOR_DEPTH_YCbCr420P;
149 break;
10288eea
TR		 150
151 case DRM_FORMAT_YUV422:
8f604f8c
TR		 152 *format = WIN_COLOR_DEPTH_YCbCr422P;
153 break;
10288eea
TR		 154
155 default:
8f604f8c 156 return -EINVAL;
10288eea
TR		 157 }
158
8f604f8c 159 return 0;
10288eea
TR		 160}
161
162static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
163{
164 switch (format) {
165 case WIN_COLOR_DEPTH_YCbCr422:
166 case WIN_COLOR_DEPTH_YUV422:
167 if (planar)
168 *planar = false;
169
170 return true;
171
172 case WIN_COLOR_DEPTH_YCbCr420P:
173 case WIN_COLOR_DEPTH_YUV420P:
174 case WIN_COLOR_DEPTH_YCbCr422P:
175 case WIN_COLOR_DEPTH_YUV422P:
176 case WIN_COLOR_DEPTH_YCbCr422R:
177 case WIN_COLOR_DEPTH_YUV422R:
178 case WIN_COLOR_DEPTH_YCbCr422RA:
179 case WIN_COLOR_DEPTH_YUV422RA:
180 if (planar)
181 *planar = true;
182
183 return true;
184 }
185
fb35c6b6
TR		 186 if (planar)
187 *planar = false;
188
10288eea
TR		 189 return false;
190}
191
192static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
193 unsigned int bpp)
194{
195 fixed20_12 outf = dfixed_init(out);
196 fixed20_12 inf = dfixed_init(in);
197 u32 dda_inc;
198 int max;
199
200 if (v)
201 max = 15;
202 else {
203 switch (bpp) {
204 case 2:
205 max = 8;
206 break;
207
208 default:
209 WARN_ON_ONCE(1);
210 /* fallthrough */
211 case 4:
212 max = 4;
213 break;
214 }
215 }
216
217 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
218 inf.full -= dfixed_const(1);
219
220 dda_inc = dfixed_div(inf, outf);
221 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
222
223 return dda_inc;
224}
225
226static inline u32 compute_initial_dda(unsigned int in)
227{
228 fixed20_12 inf = dfixed_init(in);
229 return dfixed_frac(inf);
230}
231
4aa3df71
TR		 232static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
233 const struct tegra_dc_window *window)
10288eea
TR		 234{
235 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 236 unsigned long value, flags;
10288eea
TR		 237 bool yuv, planar;
238
239 /*
240 * For YUV planar modes, the number of bytes per pixel takes into
241 * account only the luma component and therefore is 1.
242 */
243 yuv = tegra_dc_format_is_yuv(window->format, &planar);
244 if (!yuv)
245 bpp = window->bits_per_pixel / 8;
246 else
247 bpp = planar ? 1 : 2;
248
93396d0f
SP		 249 spin_lock_irqsave(&dc->lock, flags);
250
10288eea
TR		 251 value = WINDOW_A_SELECT << index;
252 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
253
254 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
255 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
256
257 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
258 tegra_dc_writel(dc, value, DC_WIN_POSITION);
259
260 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
261 tegra_dc_writel(dc, value, DC_WIN_SIZE);
262
263 h_offset = window->src.x * bpp;
264 v_offset = window->src.y;
265 h_size = window->src.w * bpp;
266 v_size = window->src.h;
267
268 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
269 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
270
271 /*
272 * For DDA computations the number of bytes per pixel for YUV planar
273 * modes needs to take into account all Y, U and V components.
274 */
275 if (yuv && planar)
276 bpp = 2;
277
278 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
279 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
280
281 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
282 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
283
284 h_dda = compute_initial_dda(window->src.x);
285 v_dda = compute_initial_dda(window->src.y);
286
287 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
288 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
289
290 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
291 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
292
293 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
294
295 if (yuv && planar) {
296 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
297 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
298 value = window->stride[1] << 16 | window->stride[0];
299 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
300 } else {
301 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
302 }
303
304 if (window->bottom_up)
305 v_offset += window->src.h - 1;
306
307 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
308 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
309
c134f019
TR		 310 if (dc->soc->supports_block_linear) {
311 unsigned long height = window->tiling.value;
312
313 switch (window->tiling.mode) {
314 case TEGRA_BO_TILING_MODE_PITCH:
315 value = DC_WINBUF_SURFACE_KIND_PITCH;
316 break;
317
318 case TEGRA_BO_TILING_MODE_TILED:
319 value = DC_WINBUF_SURFACE_KIND_TILED;
320 break;
321
322 case TEGRA_BO_TILING_MODE_BLOCK:
323 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
324 DC_WINBUF_SURFACE_KIND_BLOCK;
325 break;
326 }
327
328 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 329 } else {
c134f019
TR		 330 switch (window->tiling.mode) {
331 case TEGRA_BO_TILING_MODE_PITCH:
332 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
333 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
334 break;
10288eea 335
c134f019
TR		 336 case TEGRA_BO_TILING_MODE_TILED:
337 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
338 DC_WIN_BUFFER_ADDR_MODE_TILE;
339 break;
340
341 case TEGRA_BO_TILING_MODE_BLOCK:
4aa3df71
TR		 342 /*
343 * No need to handle this here because ->atomic_check
344 * will already have filtered it out.
345 */
346 break;
c134f019
TR		 347 }
348
349 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
350 }
10288eea
TR		 351
352 value = WIN_ENABLE;
353
354 if (yuv) {
355 /* setup default colorspace conversion coefficients */
356 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
357 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
358 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
359 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
360 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
361 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
362 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
363 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
364
365 value |= CSC_ENABLE;
366 } else if (window->bits_per_pixel < 24) {
367 value |= COLOR_EXPAND;
368 }
369
370 if (window->bottom_up)
371 value |= V_DIRECTION;
372
373 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
374
375 /*
376 * Disable blending and assume Window A is the bottom-most window,
377 * Window C is the top-most window and Window B is in the middle.
378 */
379 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
380 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
381
382 switch (index) {
383 case 0:
384 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
385 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
386 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
387 break;
388
389 case 1:
390 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
391 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
393 break;
394
395 case 2:
396 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
397 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
399 break;
400 }
401
93396d0f 402 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 403}
404
405static void tegra_plane_destroy(struct drm_plane *plane)
406{
407 struct tegra_plane *p = to_tegra_plane(plane);
408
409 drm_plane_cleanup(plane);
410 kfree(p);
411}
412
413static const u32 tegra_primary_plane_formats[] = {
414 DRM_FORMAT_XBGR8888,
415 DRM_FORMAT_XRGB8888,
416 DRM_FORMAT_RGB565,
417};
418
4aa3df71 419static void tegra_primary_plane_destroy(struct drm_plane *plane)
c7679306 420{
4aa3df71
TR		 421 tegra_plane_destroy(plane);
422}
423
8f604f8c
TR		 424static void tegra_plane_reset(struct drm_plane *plane)
425{
426 struct tegra_plane_state *state;
427
428 if (plane->state && plane->state->fb)
429 drm_framebuffer_unreference(plane->state->fb);
430
431 kfree(plane->state);
432 plane->state = NULL;
433
434 state = kzalloc(sizeof(*state), GFP_KERNEL);
435 if (state) {
436 plane->state = &state->base;
437 plane->state->plane = plane;
438 }
439}
440
441static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
442{
443 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
444 struct tegra_plane_state *copy;
445
446 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
447 if (!copy)
448 return NULL;
449
450 if (copy->base.fb)
451 drm_framebuffer_reference(copy->base.fb);
452
453 return &copy->base;
454}
455
456static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
457 struct drm_plane_state *state)
458{
459 if (state->fb)
460 drm_framebuffer_unreference(state->fb);
461
462 kfree(state);
463}
464
4aa3df71 465static const struct drm_plane_funcs tegra_primary_plane_funcs = {
07866963
TR		 466 .update_plane = drm_atomic_helper_update_plane,
467 .disable_plane = drm_atomic_helper_disable_plane,
4aa3df71 468 .destroy = tegra_primary_plane_destroy,
8f604f8c
TR		 469 .reset = tegra_plane_reset,
470 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
471 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 472};
473
474static int tegra_plane_prepare_fb(struct drm_plane *plane,
475 struct drm_framebuffer *fb)
476{
477 return 0;
478}
479
480static void tegra_plane_cleanup_fb(struct drm_plane *plane,
481 struct drm_framebuffer *fb)
482{
483}
484
47802b09
TR		 485static int tegra_plane_state_add(struct tegra_plane *plane,
486 struct drm_plane_state *state)
487{
488 struct drm_crtc_state *crtc_state;
489 struct tegra_dc_state *tegra;
490
491 /* Propagate errors from allocation or locking failures. */
492 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
493 if (IS_ERR(crtc_state))
494 return PTR_ERR(crtc_state);
495
496 tegra = to_dc_state(crtc_state);
497
498 tegra->planes |= WIN_A_ACT_REQ << plane->index;
499
500 return 0;
501}
502
4aa3df71
TR		 503static int tegra_plane_atomic_check(struct drm_plane *plane,
504 struct drm_plane_state *state)
505{
8f604f8c
TR		 506 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
507 struct tegra_bo_tiling *tiling = &plane_state->tiling;
47802b09 508 struct tegra_plane *tegra = to_tegra_plane(plane);
4aa3df71 509 struct tegra_dc *dc = to_tegra_dc(state->crtc);
4aa3df71
TR		 510 int err;
511
512 /* no need for further checks if the plane is being disabled */
513 if (!state->crtc)
514 return 0;
515
8f604f8c
TR		 516 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
517 &plane_state->swap);
4aa3df71
TR		 518 if (err < 0)
519 return err;
520
8f604f8c
TR		 521 err = tegra_fb_get_tiling(state->fb, tiling);
522 if (err < 0)
523 return err;
524
525 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
4aa3df71
TR		 526 !dc->soc->supports_block_linear) {
527 DRM_ERROR("hardware doesn't support block linear mode\n");
528 return -EINVAL;
529 }
530
531 /*
532 * Tegra doesn't support different strides for U and V planes so we
533 * error out if the user tries to display a framebuffer with such a
534 * configuration.
535 */
536 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
537 if (state->fb->pitches[2] != state->fb->pitches[1]) {
538 DRM_ERROR("unsupported UV-plane configuration\n");
539 return -EINVAL;
540 }
541 }
542
47802b09
TR		 543 err = tegra_plane_state_add(tegra, state);
544 if (err < 0)
545 return err;
546
4aa3df71
TR		 547 return 0;
548}
549
550static void tegra_plane_atomic_update(struct drm_plane *plane,
551 struct drm_plane_state *old_state)
552{
8f604f8c 553 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
4aa3df71
TR		 554 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
555 struct drm_framebuffer *fb = plane->state->fb;
c7679306 556 struct tegra_plane *p = to_tegra_plane(plane);
c7679306 557 struct tegra_dc_window window;
4aa3df71 558 unsigned int i;
c7679306 559
4aa3df71
TR		 560 /* rien ne va plus */
561 if (!plane->state->crtc || !plane->state->fb)
562 return;
563
c7679306 564 memset(&window, 0, sizeof(window));
4aa3df71
TR		 565 window.src.x = plane->state->src_x >> 16;
566 window.src.y = plane->state->src_y >> 16;
567 window.src.w = plane->state->src_w >> 16;
568 window.src.h = plane->state->src_h >> 16;
569 window.dst.x = plane->state->crtc_x;
570 window.dst.y = plane->state->crtc_y;
571 window.dst.w = plane->state->crtc_w;
572 window.dst.h = plane->state->crtc_h;
c7679306
TR		 573 window.bits_per_pixel = fb->bits_per_pixel;
574 window.bottom_up = tegra_fb_is_bottom_up(fb);
575
8f604f8c
TR		 576 /* copy from state */
577 window.tiling = state->tiling;
578 window.format = state->format;
579 window.swap = state->swap;
c7679306 580
4aa3df71
TR		 581 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
582 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
c7679306 583
4aa3df71
TR		 584 window.base[i] = bo->paddr + fb->offsets[i];
585 window.stride[i] = fb->pitches[i];
586 }
10288eea 587
4aa3df71 588 tegra_dc_setup_window(dc, p->index, &window);
10288eea
TR		 589}
590
4aa3df71
TR		 591static void tegra_plane_atomic_disable(struct drm_plane *plane,
592 struct drm_plane_state *old_state)
c7679306 593{
4aa3df71
TR		 594 struct tegra_plane *p = to_tegra_plane(plane);
595 struct tegra_dc *dc;
596 unsigned long flags;
597 u32 value;
598
599 /* rien ne va plus */
600 if (!old_state || !old_state->crtc)
601 return;
602
603 dc = to_tegra_dc(old_state->crtc);
604
605 spin_lock_irqsave(&dc->lock, flags);
606
607 value = WINDOW_A_SELECT << p->index;
608 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
609
610 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
611 value &= ~WIN_ENABLE;
612 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
613
4aa3df71 614 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 615}
616
4aa3df71
TR		 617static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
618 .prepare_fb = tegra_plane_prepare_fb,
619 .cleanup_fb = tegra_plane_cleanup_fb,
620 .atomic_check = tegra_plane_atomic_check,
621 .atomic_update = tegra_plane_atomic_update,
622 .atomic_disable = tegra_plane_atomic_disable,
c7679306
TR		 623};
624
625static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
626 struct tegra_dc *dc)
627{
518e6227
TR		 628 /*
629 * Ideally this would use drm_crtc_mask(), but that would require the
630 * CRTC to already be in the mode_config's list of CRTCs. However, it
631 * will only be added to that list in the drm_crtc_init_with_planes()
632 * (in tegra_dc_init()), which in turn requires registration of these
633 * planes. So we have ourselves a nice little chicken and egg problem
634 * here.
635 *
636 * We work around this by manually creating the mask from the number
637 * of CRTCs that have been registered, and should therefore always be
638 * the same as drm_crtc_index() after registration.
639 */
640 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 641 struct tegra_plane *plane;
642 unsigned int num_formats;
643 const u32 *formats;
644 int err;
645
646 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
647 if (!plane)
648 return ERR_PTR(-ENOMEM);
649
650 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
651 formats = tegra_primary_plane_formats;
652
518e6227 653 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306
TR		 654 &tegra_primary_plane_funcs, formats,
655 num_formats, DRM_PLANE_TYPE_PRIMARY);
656 if (err < 0) {
657 kfree(plane);
658 return ERR_PTR(err);
659 }
660
4aa3df71
TR		 661 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
662
c7679306
TR		 663 return &plane->base;
664}
665
666static const u32 tegra_cursor_plane_formats[] = {
667 DRM_FORMAT_RGBA8888,
668};
669
4aa3df71
TR		 670static int tegra_cursor_atomic_check(struct drm_plane *plane,
671 struct drm_plane_state *state)
c7679306 672{
47802b09
TR		 673 struct tegra_plane *tegra = to_tegra_plane(plane);
674 int err;
675
4aa3df71
TR		 676 /* no need for further checks if the plane is being disabled */
677 if (!state->crtc)
678 return 0;
c7679306
TR		 679
680 /* scaling not supported for cursor */
4aa3df71
TR		 681 if ((state->src_w >> 16 != state->crtc_w) ||
682 (state->src_h >> 16 != state->crtc_h))
c7679306
TR		 683 return -EINVAL;
684
685 /* only square cursors supported */
4aa3df71
TR		 686 if (state->src_w != state->src_h)
687 return -EINVAL;
688
689 if (state->crtc_w != 32 && state->crtc_w != 64 &&
690 state->crtc_w != 128 && state->crtc_w != 256)
c7679306
TR		 691 return -EINVAL;
692
47802b09
TR		 693 err = tegra_plane_state_add(tegra, state);
694 if (err < 0)
695 return err;
696
4aa3df71
TR		 697 return 0;
698}
699
700static void tegra_cursor_atomic_update(struct drm_plane *plane,
701 struct drm_plane_state *old_state)
702{
703 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
704 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
705 struct drm_plane_state *state = plane->state;
706 u32 value = CURSOR_CLIP_DISPLAY;
707
708 /* rien ne va plus */
709 if (!plane->state->crtc || !plane->state->fb)
710 return;
711
712 switch (state->crtc_w) {
c7679306
TR		 713 case 32:
714 value |= CURSOR_SIZE_32x32;
715 break;
716
717 case 64:
718 value |= CURSOR_SIZE_64x64;
719 break;
720
721 case 128:
722 value |= CURSOR_SIZE_128x128;
723 break;
724
725 case 256:
726 value |= CURSOR_SIZE_256x256;
727 break;
728
729 default:
4aa3df71
TR		 730 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
731 state->crtc_h);
732 return;
c7679306
TR		 733 }
734
735 value |= (bo->paddr >> 10) & 0x3fffff;
736 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
737
738#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
739 value = (bo->paddr >> 32) & 0x3;
740 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
741#endif
742
743 /* enable cursor and set blend mode */
744 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
745 value |= CURSOR_ENABLE;
746 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
747
748 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
749 value &= ~CURSOR_DST_BLEND_MASK;
750 value &= ~CURSOR_SRC_BLEND_MASK;
751 value |= CURSOR_MODE_NORMAL;
752 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
753 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
754 value |= CURSOR_ALPHA;
755 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
756
757 /* position the cursor */
4aa3df71 758 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
c7679306
TR		 759 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
760
c7679306
TR		 761}
762
4aa3df71
TR		 763static void tegra_cursor_atomic_disable(struct drm_plane *plane,
764 struct drm_plane_state *old_state)
c7679306 765{
4aa3df71 766 struct tegra_dc *dc;
c7679306
TR		 767 u32 value;
768
4aa3df71
TR		 769 /* rien ne va plus */
770 if (!old_state || !old_state->crtc)
771 return;
772
773 dc = to_tegra_dc(old_state->crtc);
c7679306
TR		 774
775 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
776 value &= ~CURSOR_ENABLE;
777 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
c7679306
TR		 778}
779
780static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
07866963
TR		 781 .update_plane = drm_atomic_helper_update_plane,
782 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 783 .destroy = tegra_plane_destroy,
8f604f8c
TR		 784 .reset = tegra_plane_reset,
785 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
786 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 787};
788
789static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
790 .prepare_fb = tegra_plane_prepare_fb,
791 .cleanup_fb = tegra_plane_cleanup_fb,
792 .atomic_check = tegra_cursor_atomic_check,
793 .atomic_update = tegra_cursor_atomic_update,
794 .atomic_disable = tegra_cursor_atomic_disable,
c7679306
TR		 795};
796
797static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
798 struct tegra_dc *dc)
799{
800 struct tegra_plane *plane;
801 unsigned int num_formats;
802 const u32 *formats;
803 int err;
804
805 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
806 if (!plane)
807 return ERR_PTR(-ENOMEM);
808
47802b09
TR		 809 /*
810 * We'll treat the cursor as an overlay plane with index 6 here so
811 * that the update and activation request bits in DC_CMD_STATE_CONTROL
812 * match up.
813 */
814 plane->index = 6;
815
c7679306
TR		 816 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
817 formats = tegra_cursor_plane_formats;
818
819 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
820 &tegra_cursor_plane_funcs, formats,
821 num_formats, DRM_PLANE_TYPE_CURSOR);
822 if (err < 0) {
823 kfree(plane);
824 return ERR_PTR(err);
825 }
826
4aa3df71 827 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
f34bc787 828
4aa3df71 829 return &plane->base;
f34bc787
TR		 830}
831
c7679306 832static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 833{
c7679306 834 tegra_plane_destroy(plane);
f34bc787
TR		 835}
836
c7679306 837static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
07866963
TR		 838 .update_plane = drm_atomic_helper_update_plane,
839 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 840 .destroy = tegra_overlay_plane_destroy,
8f604f8c
TR		 841 .reset = tegra_plane_reset,
842 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
843 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
f34bc787
TR		 844};
845
c7679306 846static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 847 DRM_FORMAT_XBGR8888,
f34bc787 848 DRM_FORMAT_XRGB8888,
dbe4d9a7 849 DRM_FORMAT_RGB565,
f34bc787 850 DRM_FORMAT_UYVY,
f925390e 851 DRM_FORMAT_YUYV,
f34bc787
TR		 852 DRM_FORMAT_YUV420,
853 DRM_FORMAT_YUV422,
854};
855
4aa3df71
TR		 856static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
857 .prepare_fb = tegra_plane_prepare_fb,
858 .cleanup_fb = tegra_plane_cleanup_fb,
859 .atomic_check = tegra_plane_atomic_check,
860 .atomic_update = tegra_plane_atomic_update,
861 .atomic_disable = tegra_plane_atomic_disable,
862};
863
c7679306
TR		 864static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
865 struct tegra_dc *dc,
866 unsigned int index)
f34bc787 867{
c7679306
TR		 868 struct tegra_plane *plane;
869 unsigned int num_formats;
870 const u32 *formats;
871 int err;
f34bc787 872
c7679306
TR		 873 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
874 if (!plane)
875 return ERR_PTR(-ENOMEM);
f34bc787 876
c7679306 877 plane->index = index;
f34bc787 878
c7679306
TR		 879 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
880 formats = tegra_overlay_plane_formats;
f34bc787 881
c7679306
TR		 882 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
883 &tegra_overlay_plane_funcs, formats,
884 num_formats, DRM_PLANE_TYPE_OVERLAY);
885 if (err < 0) {
886 kfree(plane);
887 return ERR_PTR(err);
888 }
889
4aa3df71
TR		 890 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
891
c7679306
TR		 892 return &plane->base;
893}
894
895static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
896{
897 struct drm_plane *plane;
898 unsigned int i;
899
900 for (i = 0; i < 2; i++) {
901 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
902 if (IS_ERR(plane))
903 return PTR_ERR(plane);
f34bc787
TR		 904 }
905
906 return 0;
907}
908
6e5ff998
TR		 909void tegra_dc_enable_vblank(struct tegra_dc *dc)
910{
911 unsigned long value, flags;
912
913 spin_lock_irqsave(&dc->lock, flags);
914
915 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
916 value |= VBLANK_INT;
917 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
918
919 spin_unlock_irqrestore(&dc->lock, flags);
920}
921
922void tegra_dc_disable_vblank(struct tegra_dc *dc)
923{
924 unsigned long value, flags;
925
926 spin_lock_irqsave(&dc->lock, flags);
927
928 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
929 value &= ~VBLANK_INT;
930 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
931
932 spin_unlock_irqrestore(&dc->lock, flags);
933}
934
3c03c46a
TR		 935static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
936{
937 struct drm_device *drm = dc->base.dev;
938 struct drm_crtc *crtc = &dc->base;
3c03c46a 939 unsigned long flags, base;
de2ba664 940 struct tegra_bo *bo;
3c03c46a 941
6b59cc1c
TR		 942 spin_lock_irqsave(&drm->event_lock, flags);
943
944 if (!dc->event) {
945 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 946 return;
6b59cc1c 947 }
3c03c46a 948
f4510a27 949 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 950
8643bc6d 951 spin_lock(&dc->lock);
93396d0f 952
3c03c46a 953 /* check if new start address has been latched */
93396d0f 954 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 955 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
956 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
957 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
958
8643bc6d 959 spin_unlock(&dc->lock);
93396d0f 960
f4510a27 961 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 962 drm_crtc_send_vblank_event(crtc, dc->event);
963 drm_crtc_vblank_put(crtc);
3c03c46a 964 dc->event = NULL;
3c03c46a 965 }
6b59cc1c
TR		 966
967 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 968}
969
970void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
971{
972 struct tegra_dc *dc = to_tegra_dc(crtc);
973 struct drm_device *drm = crtc->dev;
974 unsigned long flags;
975
976 spin_lock_irqsave(&drm->event_lock, flags);
977
978 if (dc->event && dc->event->base.file_priv == file) {
979 dc->event->base.destroy(&dc->event->base);
ed7dae58 980 drm_crtc_vblank_put(crtc);
3c03c46a
TR		 981 dc->event = NULL;
982 }
983
984 spin_unlock_irqrestore(&drm->event_lock, flags);
985}
986
f002abc1
TR		 987static void tegra_dc_destroy(struct drm_crtc *crtc)
988{
989 drm_crtc_cleanup(crtc);
f002abc1
TR		 990}
991
ca915b10
TR		 992static void tegra_crtc_reset(struct drm_crtc *crtc)
993{
994 struct tegra_dc_state *state;
995
996 kfree(crtc->state);
997 crtc->state = NULL;
998
999 state = kzalloc(sizeof(*state), GFP_KERNEL);
332bbe70 1000 if (state) {
ca915b10 1001 crtc->state = &state->base;
332bbe70
TR		 1002 crtc->state->crtc = crtc;
1003 }
ca915b10
TR		 1004}
1005
1006static struct drm_crtc_state *
1007tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1008{
1009 struct tegra_dc_state *state = to_dc_state(crtc->state);
1010 struct tegra_dc_state *copy;
1011
1012 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1013 if (!copy)
1014 return NULL;
1015
1016 copy->base.mode_changed = false;
567a3cd1 1017 copy->base.active_changed = false;
ca915b10
TR		 1018 copy->base.planes_changed = false;
1019 copy->base.event = NULL;
1020
1021 return &copy->base;
1022}
1023
1024static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1025 struct drm_crtc_state *state)
1026{
1027 kfree(state);
1028}
1029
d8f4a9ed 1030static const struct drm_crtc_funcs tegra_crtc_funcs = {
1503ca47 1031 .page_flip = drm_atomic_helper_page_flip,
74f48791 1032 .set_config = drm_atomic_helper_set_config,
f002abc1 1033 .destroy = tegra_dc_destroy,
ca915b10
TR		 1034 .reset = tegra_crtc_reset,
1035 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1036 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
d8f4a9ed
TR		 1037};
1038
86df256f
TR		 1039static void tegra_dc_stop(struct tegra_dc *dc)
1040{
1041 u32 value;
1042
1043 /* stop the display controller */
1044 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1045 value &= ~DISP_CTRL_MODE_MASK;
1046 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1047
1048 tegra_dc_commit(dc);
1049}
1050
1051static bool tegra_dc_idle(struct tegra_dc *dc)
1052{
1053 u32 value;
1054
1055 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1056
1057 return (value & DISP_CTRL_MODE_MASK) == 0;
1058}
1059
1060static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1061{
1062 timeout = jiffies + msecs_to_jiffies(timeout);
1063
1064 while (time_before(jiffies, timeout)) {
1065 if (tegra_dc_idle(dc))
1066 return 0;
1067
1068 usleep_range(1000, 2000);
1069 }
1070
1071 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1072 return -ETIMEDOUT;
1073}
1074
f34bc787 1075static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 1076{
f002abc1 1077 struct tegra_dc *dc = to_tegra_dc(crtc);
3b0e5855 1078 u32 value;
f002abc1 1079
86df256f
TR		 1080 if (!tegra_dc_idle(dc)) {
1081 tegra_dc_stop(dc);
1082
1083 /*
1084 * Ignore the return value, there isn't anything useful to do
1085 * in case this fails.
1086 */
1087 tegra_dc_wait_idle(dc, 100);
1088 }
36904adf 1089
3b0e5855
TR		 1090 /*
1091 * This should really be part of the RGB encoder driver, but clearing
1092 * these bits has the side-effect of stopping the display controller.
1093 * When that happens no VBLANK interrupts will be raised. At the same
1094 * time the encoder is disabled before the display controller, so the
1095 * above code is always going to timeout waiting for the controller
1096 * to go idle.
1097 *
1098 * Given the close coupling between the RGB encoder and the display
1099 * controller doing it here is still kind of okay. None of the other
1100 * encoder drivers require these bits to be cleared.
1101 *
1102 * XXX: Perhaps given that the display controller is switched off at
1103 * this point anyway maybe clearing these bits isn't even useful for
1104 * the RGB encoder?
1105 */
1106 if (dc->rgb) {
1107 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1108 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1109 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1110 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1111 }
1112
8ff64c17 1113 drm_crtc_vblank_off(crtc);
d8f4a9ed
TR		 1114}
1115
1116static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
1117 const struct drm_display_mode *mode,
1118 struct drm_display_mode *adjusted)
1119{
1120 return true;
1121}
1122
d8f4a9ed
TR		 1123static int tegra_dc_set_timings(struct tegra_dc *dc,
1124 struct drm_display_mode *mode)
1125{
0444c0ff
TR		 1126 unsigned int h_ref_to_sync = 1;
1127 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 1128 unsigned long value;
1129
1130 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1131
1132 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1133 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1134
1135 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1136 ((mode->hsync_end - mode->hsync_start) << 0);
1137 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1138
d8f4a9ed
TR		 1139 value = ((mode->vtotal - mode->vsync_end) << 16) |
1140 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 1141 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1142
1143 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1144 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 1145 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1146
1147 value = (mode->vdisplay << 16) | mode->hdisplay;
1148 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1149
1150 return 0;
1151}
1152
c5a107d3
TR		 1153int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent,
1154 unsigned long pclk, unsigned int div)
1155{
1156 u32 value;
1157 int err;
1158
1159 err = clk_set_parent(dc->clk, parent);
1160 if (err < 0) {
1161 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1162 return err;
1163 }
1164
1165 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
1166
1167 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
1168 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1169
1170 return 0;
1171}
1172
ca915b10
TR		 1173int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1174 struct drm_crtc_state *crtc_state,
1175 struct clk *clk, unsigned long pclk,
1176 unsigned int div)
1177{
1178 struct tegra_dc_state *state = to_dc_state(crtc_state);
1179
1180 state->clk = clk;
1181 state->pclk = pclk;
1182 state->div = div;
1183
1184 return 0;
1185}
1186
76d59ed0
TR		 1187static void tegra_dc_commit_state(struct tegra_dc *dc,
1188 struct tegra_dc_state *state)
1189{
1190 u32 value;
1191 int err;
1192
1193 err = clk_set_parent(dc->clk, state->clk);
1194 if (err < 0)
1195 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1196
1197 /*
1198 * Outputs may not want to change the parent clock rate. This is only
1199 * relevant to Tegra20 where only a single display PLL is available.
1200 * Since that PLL would typically be used for HDMI, an internal LVDS
1201 * panel would need to be driven by some other clock such as PLL_P
1202 * which is shared with other peripherals. Changing the clock rate
1203 * should therefore be avoided.
1204 */
1205 if (state->pclk > 0) {
1206 err = clk_set_rate(state->clk, state->pclk);
1207 if (err < 0)
1208 dev_err(dc->dev,
1209 "failed to set clock rate to %lu Hz\n",
1210 state->pclk);
1211 }
1212
1213 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1214 state->div);
1215 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1216
1217 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1218 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1219}
1220
4aa3df71 1221static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
d8f4a9ed 1222{
4aa3df71 1223 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
76d59ed0 1224 struct tegra_dc_state *state = to_dc_state(crtc->state);
d8f4a9ed 1225 struct tegra_dc *dc = to_tegra_dc(crtc);
dbb3f2f7 1226 u32 value;
d8f4a9ed 1227
76d59ed0
TR		 1228 tegra_dc_commit_state(dc, state);
1229
d8f4a9ed
TR		 1230 /* program display mode */
1231 tegra_dc_set_timings(dc, mode);
1232
8620fc62
TR		 1233 /* interlacing isn't supported yet, so disable it */
1234 if (dc->soc->supports_interlacing) {
1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1236 value &= ~INTERLACE_ENABLE;
1237 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1238 }
666cb873
TR		 1239
1240 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1241 value &= ~DISP_CTRL_MODE_MASK;
1242 value |= DISP_CTRL_MODE_C_DISPLAY;
1243 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1244
1245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1246 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1247 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1249
1250 tegra_dc_commit(dc);
d8f4a9ed
TR		 1251}
1252
1253static void tegra_crtc_prepare(struct drm_crtc *crtc)
1254{
8ff64c17 1255 drm_crtc_vblank_off(crtc);
d8f4a9ed
TR		 1256}
1257
1258static void tegra_crtc_commit(struct drm_crtc *crtc)
1259{
8ff64c17 1260 drm_crtc_vblank_on(crtc);
d8f4a9ed
TR		 1261}
1262
4aa3df71
TR		 1263static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1264 struct drm_crtc_state *state)
1265{
1266 return 0;
1267}
1268
1269static void tegra_crtc_atomic_begin(struct drm_crtc *crtc)
1270{
1503ca47
TR		 1271 struct tegra_dc *dc = to_tegra_dc(crtc);
1272
1273 if (crtc->state->event) {
1274 crtc->state->event->pipe = drm_crtc_index(crtc);
1275
1276 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1277
1278 dc->event = crtc->state->event;
1279 crtc->state->event = NULL;
1280 }
4aa3df71
TR		 1281}
1282
1283static void tegra_crtc_atomic_flush(struct drm_crtc *crtc)
1284{
47802b09
TR		 1285 struct tegra_dc_state *state = to_dc_state(crtc->state);
1286 struct tegra_dc *dc = to_tegra_dc(crtc);
1287
1288 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1289 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
4aa3df71
TR		 1290}
1291
d8f4a9ed 1292static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1293 .disable = tegra_crtc_disable,
d8f4a9ed 1294 .mode_fixup = tegra_crtc_mode_fixup,
4aa3df71
TR		 1295 .mode_set = drm_helper_crtc_mode_set,
1296 .mode_set_nofb = tegra_crtc_mode_set_nofb,
1297 .mode_set_base = drm_helper_crtc_mode_set_base,
d8f4a9ed
TR		 1298 .prepare = tegra_crtc_prepare,
1299 .commit = tegra_crtc_commit,
4aa3df71
TR		 1300 .atomic_check = tegra_crtc_atomic_check,
1301 .atomic_begin = tegra_crtc_atomic_begin,
1302 .atomic_flush = tegra_crtc_atomic_flush,
d8f4a9ed
TR		 1303};
1304
6e5ff998 1305static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1306{
1307 struct tegra_dc *dc = data;
1308 unsigned long status;
1309
1310 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1311 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1312
1313 if (status & FRAME_END_INT) {
1314 /*
1315 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1316 */
1317 }
1318
1319 if (status & VBLANK_INT) {
1320 /*
1321 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1322 */
ed7dae58 1323 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1324 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 1325 }
1326
1327 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1328 /*
1329 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1330 */
1331 }
1332
1333 return IRQ_HANDLED;
1334}
1335
1336static int tegra_dc_show_regs(struct seq_file *s, void *data)
1337{
1338 struct drm_info_node *node = s->private;
1339 struct tegra_dc *dc = node->info_ent->data;
1340
1341#define DUMP_REG(name) \
03a60569 1342 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1343 tegra_dc_readl(dc, name))
1344
1345 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1346 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1347 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1348 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1349 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1350 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1351 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1352 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1353 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1354 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1355 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1356 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1357 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1358 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1359 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1360 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1361 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1362 DUMP_REG(DC_CMD_INT_STATUS);
1363 DUMP_REG(DC_CMD_INT_MASK);
1364 DUMP_REG(DC_CMD_INT_ENABLE);
1365 DUMP_REG(DC_CMD_INT_TYPE);
1366 DUMP_REG(DC_CMD_INT_POLARITY);
1367 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1368 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1369 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1370 DUMP_REG(DC_CMD_STATE_ACCESS);
1371 DUMP_REG(DC_CMD_STATE_CONTROL);
1372 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1373 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1374 DUMP_REG(DC_COM_CRC_CONTROL);
1375 DUMP_REG(DC_COM_CRC_CHECKSUM);
1376 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1377 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1378 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1379 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1380 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1381 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1382 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1383 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1384 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1385 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1386 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1387 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1388 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1389 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1390 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1391 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1392 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1393 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1394 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1395 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1396 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1397 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1398 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1399 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1400 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1401 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1402 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1403 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1404 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1405 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1406 DUMP_REG(DC_COM_SPI_CONTROL);
1407 DUMP_REG(DC_COM_SPI_START_BYTE);
1408 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1409 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1410 DUMP_REG(DC_COM_HSPI_CS_DC);
1411 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1412 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1413 DUMP_REG(DC_COM_GPIO_CTRL);
1414 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1415 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1416 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1417 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1418 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1419 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1420 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1421 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1422 DUMP_REG(DC_DISP_REF_TO_SYNC);
1423 DUMP_REG(DC_DISP_SYNC_WIDTH);
1424 DUMP_REG(DC_DISP_BACK_PORCH);
1425 DUMP_REG(DC_DISP_ACTIVE);
1426 DUMP_REG(DC_DISP_FRONT_PORCH);
1427 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1428 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1429 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1430 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1431 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1432 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1433 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1434 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1435 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1436 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1437 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1438 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1439 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1440 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1441 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1442 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1443 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1444 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1445 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1446 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1447 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1448 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1449 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1450 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1451 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1452 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1453 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1454 DUMP_REG(DC_DISP_M0_CONTROL);
1455 DUMP_REG(DC_DISP_M1_CONTROL);
1456 DUMP_REG(DC_DISP_DI_CONTROL);
1457 DUMP_REG(DC_DISP_PP_CONTROL);
1458 DUMP_REG(DC_DISP_PP_SELECT_A);
1459 DUMP_REG(DC_DISP_PP_SELECT_B);
1460 DUMP_REG(DC_DISP_PP_SELECT_C);
1461 DUMP_REG(DC_DISP_PP_SELECT_D);
1462 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1463 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1464 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1465 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1466 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1467 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1468 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1469 DUMP_REG(DC_DISP_BORDER_COLOR);
1470 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1471 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1472 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1473 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1474 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1475 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1476 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1477 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1478 DUMP_REG(DC_DISP_CURSOR_POSITION);
1479 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1480 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1481 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1482 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1483 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1484 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1485 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1486 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1487 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1488 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1489 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1490 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1491 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1492 DUMP_REG(DC_DISP_SD_CONTROL);
1493 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1494 DUMP_REG(DC_DISP_SD_LUT(0));
1495 DUMP_REG(DC_DISP_SD_LUT(1));
1496 DUMP_REG(DC_DISP_SD_LUT(2));
1497 DUMP_REG(DC_DISP_SD_LUT(3));
1498 DUMP_REG(DC_DISP_SD_LUT(4));
1499 DUMP_REG(DC_DISP_SD_LUT(5));
1500 DUMP_REG(DC_DISP_SD_LUT(6));
1501 DUMP_REG(DC_DISP_SD_LUT(7));
1502 DUMP_REG(DC_DISP_SD_LUT(8));
1503 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1504 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1505 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1506 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1507 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1508 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1509 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1510 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1511 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1512 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1513 DUMP_REG(DC_DISP_SD_BL_TF(0));
1514 DUMP_REG(DC_DISP_SD_BL_TF(1));
1515 DUMP_REG(DC_DISP_SD_BL_TF(2));
1516 DUMP_REG(DC_DISP_SD_BL_TF(3));
1517 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1518 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1519 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1520 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1521 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1522 DUMP_REG(DC_WIN_WIN_OPTIONS);
1523 DUMP_REG(DC_WIN_BYTE_SWAP);
1524 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1525 DUMP_REG(DC_WIN_COLOR_DEPTH);
1526 DUMP_REG(DC_WIN_POSITION);
1527 DUMP_REG(DC_WIN_SIZE);
1528 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1529 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1530 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1531 DUMP_REG(DC_WIN_DDA_INC);
1532 DUMP_REG(DC_WIN_LINE_STRIDE);
1533 DUMP_REG(DC_WIN_BUF_STRIDE);
1534 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1535 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1536 DUMP_REG(DC_WIN_DV_CONTROL);
1537 DUMP_REG(DC_WIN_BLEND_NOKEY);
1538 DUMP_REG(DC_WIN_BLEND_1WIN);
1539 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1540 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1541 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1542 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1543 DUMP_REG(DC_WINBUF_START_ADDR);
1544 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1545 DUMP_REG(DC_WINBUF_START_ADDR_U);
1546 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1547 DUMP_REG(DC_WINBUF_START_ADDR_V);
1548 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1549 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1550 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1551 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1552 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1553 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1554 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1555 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1556 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1557
1558#undef DUMP_REG
1559
1560 return 0;
1561}
1562
1563static struct drm_info_list debugfs_files[] = {
1564 { "regs", tegra_dc_show_regs, 0, NULL },
1565};
1566
1567static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1568{
1569 unsigned int i;
1570 char *name;
1571 int err;
1572
1573 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1574 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1575 kfree(name);
1576
1577 if (!dc->debugfs)
1578 return -ENOMEM;
1579
1580 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1581 GFP_KERNEL);
1582 if (!dc->debugfs_files) {
1583 err = -ENOMEM;
1584 goto remove;
1585 }
1586
1587 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1588 dc->debugfs_files[i].data = dc;
1589
1590 err = drm_debugfs_create_files(dc->debugfs_files,
1591 ARRAY_SIZE(debugfs_files),
1592 dc->debugfs, minor);
1593 if (err < 0)
1594 goto free;
1595
1596 dc->minor = minor;
1597
1598 return 0;
1599
1600free:
1601 kfree(dc->debugfs_files);
1602 dc->debugfs_files = NULL;
1603remove:
1604 debugfs_remove(dc->debugfs);
1605 dc->debugfs = NULL;
1606
1607 return err;
1608}
1609
1610static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1611{
1612 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1613 dc->minor);
1614 dc->minor = NULL;
1615
1616 kfree(dc->debugfs_files);
1617 dc->debugfs_files = NULL;
1618
1619 debugfs_remove(dc->debugfs);
1620 dc->debugfs = NULL;
1621
1622 return 0;
1623}
1624
53fa7f72 1625static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1626{
9910f5c4 1627 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1628 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1629 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1630 struct drm_plane *primary = NULL;
1631 struct drm_plane *cursor = NULL;
07d05cbf
TR		 1632 unsigned int syncpt;
1633 u32 value;
d8f4a9ed
TR		 1634 int err;
1635
df06b759
TR		 1636 if (tegra->domain) {
1637 err = iommu_attach_device(tegra->domain, dc->dev);
1638 if (err < 0) {
1639 dev_err(dc->dev, "failed to attach to domain: %d\n",
1640 err);
1641 return err;
1642 }
1643
1644 dc->domain = tegra->domain;
1645 }
1646
c7679306
TR		 1647 primary = tegra_dc_primary_plane_create(drm, dc);
1648 if (IS_ERR(primary)) {
1649 err = PTR_ERR(primary);
1650 goto cleanup;
1651 }
1652
1653 if (dc->soc->supports_cursor) {
1654 cursor = tegra_dc_cursor_plane_create(drm, dc);
1655 if (IS_ERR(cursor)) {
1656 err = PTR_ERR(cursor);
1657 goto cleanup;
1658 }
1659 }
1660
1661 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1662 &tegra_crtc_funcs);
1663 if (err < 0)
1664 goto cleanup;
1665
d8f4a9ed
TR		 1666 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1667 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1668
d1f3e1e0
TR		 1669 /*
1670 * Keep track of the minimum pitch alignment across all display
1671 * controllers.
1672 */
1673 if (dc->soc->pitch_align > tegra->pitch_align)
1674 tegra->pitch_align = dc->soc->pitch_align;
1675
9910f5c4 1676 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1677 if (err < 0 && err != -ENODEV) {
1678 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1679 goto cleanup;
d8f4a9ed
TR		 1680 }
1681
9910f5c4 1682 err = tegra_dc_add_planes(drm, dc);
f34bc787 1683 if (err < 0)
c7679306 1684 goto cleanup;
f34bc787 1685
d8f4a9ed 1686 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1687 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1688 if (err < 0)
1689 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1690 }
1691
6e5ff998 1692 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1693 dev_name(dc->dev), dc);
1694 if (err < 0) {
1695 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1696 err);
c7679306 1697 goto cleanup;
d8f4a9ed
TR		 1698 }
1699
07d05cbf
TR		 1700 /* initialize display controller */
1701 if (dc->pipe)
1702 syncpt = SYNCPT_VBLANK1;
1703 else
1704 syncpt = SYNCPT_VBLANK0;
1705
1706 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1707 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1708
1709 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1710 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1711
1712 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1713 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1714 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1715
1716 /* initialize timer */
1717 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1718 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1719 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1720
1721 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1722 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1723 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1724
1725 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1726 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1727
1728 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1729 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1730
1731 if (dc->soc->supports_border_color)
1732 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1733
d8f4a9ed 1734 return 0;
c7679306
TR		 1735
1736cleanup:
1737 if (cursor)
1738 drm_plane_cleanup(cursor);
1739
1740 if (primary)
1741 drm_plane_cleanup(primary);
1742
1743 if (tegra->domain) {
1744 iommu_detach_device(tegra->domain, dc->dev);
1745 dc->domain = NULL;
1746 }
1747
1748 return err;
d8f4a9ed
TR		 1749}
1750
53fa7f72 1751static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1752{
776dc384 1753 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1754 int err;
1755
1756 devm_free_irq(dc->dev, dc->irq, dc);
1757
1758 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1759 err = tegra_dc_debugfs_exit(dc);
1760 if (err < 0)
1761 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1762 }
1763
1764 err = tegra_dc_rgb_exit(dc);
1765 if (err) {
1766 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1767 return err;
1768 }
1769
df06b759
TR		 1770 if (dc->domain) {
1771 iommu_detach_device(dc->domain, dc->dev);
1772 dc->domain = NULL;
1773 }
1774
d8f4a9ed
TR		 1775 return 0;
1776}
1777
1778static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1779 .init = tegra_dc_init,
1780 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1781};
1782
8620fc62 1783static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1784 .supports_border_color = true,
8620fc62 1785 .supports_interlacing = false,
e687651b 1786 .supports_cursor = false,
c134f019 1787 .supports_block_linear = false,
d1f3e1e0 1788 .pitch_align = 8,
9c012700 1789 .has_powergate = false,
8620fc62
TR		 1790};
1791
1792static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1793 .supports_border_color = true,
8620fc62 1794 .supports_interlacing = false,
e687651b 1795 .supports_cursor = false,
c134f019 1796 .supports_block_linear = false,
d1f3e1e0 1797 .pitch_align = 8,
9c012700 1798 .has_powergate = false,
d1f3e1e0
TR		 1799};
1800
1801static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1802 .supports_border_color = true,
d1f3e1e0
TR		 1803 .supports_interlacing = false,
1804 .supports_cursor = false,
1805 .supports_block_linear = false,
1806 .pitch_align = 64,
9c012700 1807 .has_powergate = true,
8620fc62
TR		 1808};
1809
1810static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1811 .supports_border_color = false,
8620fc62 1812 .supports_interlacing = true,
e687651b 1813 .supports_cursor = true,
c134f019 1814 .supports_block_linear = true,
d1f3e1e0 1815 .pitch_align = 64,
9c012700 1816 .has_powergate = true,
8620fc62
TR		 1817};
1818
1819static const struct of_device_id tegra_dc_of_match[] = {
1820 {
1821 .compatible = "nvidia,tegra124-dc",
1822 .data = &tegra124_dc_soc_info,
9c012700
TR		 1823 }, {
1824 .compatible = "nvidia,tegra114-dc",
1825 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1826 }, {
1827 .compatible = "nvidia,tegra30-dc",
1828 .data = &tegra30_dc_soc_info,
1829 }, {
1830 .compatible = "nvidia,tegra20-dc",
1831 .data = &tegra20_dc_soc_info,
1832 }, {
1833 /* sentinel */
1834 }
1835};
ef70728c 1836MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1837
13411ddd
TR		 1838static int tegra_dc_parse_dt(struct tegra_dc *dc)
1839{
1840 struct device_node *np;
1841 u32 value = 0;
1842 int err;
1843
1844 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1845 if (err < 0) {
1846 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1847
1848 /*
1849 * If the nvidia,head property isn't present, try to find the
1850 * correct head number by looking up the position of this
1851 * display controller's node within the device tree. Assuming
1852 * that the nodes are ordered properly in the DTS file and
1853 * that the translation into a flattened device tree blob
1854 * preserves that ordering this will actually yield the right
1855 * head number.
1856 *
1857 * If those assumptions don't hold, this will still work for
1858 * cases where only a single display controller is used.
1859 */
1860 for_each_matching_node(np, tegra_dc_of_match) {
1861 if (np == dc->dev->of_node)
1862 break;
1863
1864 value++;
1865 }
1866 }
1867
1868 dc->pipe = value;
1869
1870 return 0;
1871}
1872
d8f4a9ed
TR		 1873static int tegra_dc_probe(struct platform_device *pdev)
1874{
8620fc62 1875 const struct of_device_id *id;
d8f4a9ed
TR		 1876 struct resource *regs;
1877 struct tegra_dc *dc;
1878 int err;
1879
1880 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1881 if (!dc)
1882 return -ENOMEM;
1883
8620fc62
TR		 1884 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1885 if (!id)
1886 return -ENODEV;
1887
6e5ff998 1888 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1889 INIT_LIST_HEAD(&dc->list);
1890 dc->dev = &pdev->dev;
8620fc62 1891 dc->soc = id->data;
d8f4a9ed 1892
13411ddd
TR		 1893 err = tegra_dc_parse_dt(dc);
1894 if (err < 0)
1895 return err;
1896
d8f4a9ed
TR		 1897 dc->clk = devm_clk_get(&pdev->dev, NULL);
1898 if (IS_ERR(dc->clk)) {
1899 dev_err(&pdev->dev, "failed to get clock\n");
1900 return PTR_ERR(dc->clk);
1901 }
1902
ca48080a
SW		 1903 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1904 if (IS_ERR(dc->rst)) {
1905 dev_err(&pdev->dev, "failed to get reset\n");
1906 return PTR_ERR(dc->rst);
1907 }
1908
9c012700
TR		 1909 if (dc->soc->has_powergate) {
1910 if (dc->pipe == 0)
1911 dc->powergate = TEGRA_POWERGATE_DIS;
1912 else
1913 dc->powergate = TEGRA_POWERGATE_DISB;
1914
1915 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1916 dc->rst);
1917 if (err < 0) {
1918 dev_err(&pdev->dev, "failed to power partition: %d\n",
1919 err);
1920 return err;
1921 }
1922 } else {
1923 err = clk_prepare_enable(dc->clk);
1924 if (err < 0) {
1925 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1926 err);
1927 return err;
1928 }
1929
1930 err = reset_control_deassert(dc->rst);
1931 if (err < 0) {
1932 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1933 err);
1934 return err;
1935 }
1936 }
d8f4a9ed
TR		 1937
1938 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1939 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1940 if (IS_ERR(dc->regs))
1941 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1942
1943 dc->irq = platform_get_irq(pdev, 0);
1944 if (dc->irq < 0) {
1945 dev_err(&pdev->dev, "failed to get IRQ\n");
1946 return -ENXIO;
1947 }
1948
776dc384
TR		 1949 INIT_LIST_HEAD(&dc->client.list);
1950 dc->client.ops = &dc_client_ops;
1951 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1952
1953 err = tegra_dc_rgb_probe(dc);
1954 if (err < 0 && err != -ENODEV) {
1955 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1956 return err;
1957 }
1958
776dc384 1959 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1960 if (err < 0) {
1961 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1962 err);
1963 return err;
1964 }
1965
1966 platform_set_drvdata(pdev, dc);
1967
1968 return 0;
1969}
1970
1971static int tegra_dc_remove(struct platform_device *pdev)
1972{
d8f4a9ed
TR		 1973 struct tegra_dc *dc = platform_get_drvdata(pdev);
1974 int err;
1975
776dc384 1976 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1977 if (err < 0) {
1978 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1979 err);
1980 return err;
1981 }
1982
59d29c0e
TR		 1983 err = tegra_dc_rgb_remove(dc);
1984 if (err < 0) {
1985 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1986 return err;
1987 }
1988
5482d75a 1989 reset_control_assert(dc->rst);
9c012700
TR		 1990
1991 if (dc->soc->has_powergate)
1992 tegra_powergate_power_off(dc->powergate);
1993
d8f4a9ed
TR		 1994 clk_disable_unprepare(dc->clk);
1995
1996 return 0;
1997}
1998
d8f4a9ed
TR		 1999struct platform_driver tegra_dc_driver = {
2000 .driver = {
2001 .name = "tegra-dc",
2002 .owner = THIS_MODULE,
2003 .of_match_table = tegra_dc_of_match,
2004 },
2005 .probe = tegra_dc_probe,
2006 .remove = tegra_dc_remove,
2007};
Linux kernel - Deliverables
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