Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
9eb9b220 | 11 | #include <linux/debugfs.h> |
ca48080a | 12 | #include <linux/reset.h> |
d8f4a9ed | 13 | |
9c012700 TR |
14 | #include <soc/tegra/pmc.h> |
15 | ||
de2ba664 AM |
16 | #include "dc.h" |
17 | #include "drm.h" | |
18 | #include "gem.h" | |
d8f4a9ed | 19 | |
8620fc62 TR |
20 | struct tegra_dc_soc_info { |
21 | bool supports_interlacing; | |
e687651b | 22 | bool supports_cursor; |
c134f019 | 23 | bool supports_block_linear; |
d1f3e1e0 | 24 | unsigned int pitch_align; |
9c012700 | 25 | bool has_powergate; |
8620fc62 TR |
26 | }; |
27 | ||
f34bc787 TR |
28 | struct tegra_plane { |
29 | struct drm_plane base; | |
30 | unsigned int index; | |
d8f4a9ed TR |
31 | }; |
32 | ||
f34bc787 TR |
33 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
34 | { | |
35 | return container_of(plane, struct tegra_plane, base); | |
36 | } | |
37 | ||
10288eea TR |
38 | static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap) |
39 | { | |
40 | /* assume no swapping of fetched data */ | |
41 | if (swap) | |
42 | *swap = BYTE_SWAP_NOSWAP; | |
43 | ||
44 | switch (format) { | |
45 | case DRM_FORMAT_XBGR8888: | |
46 | return WIN_COLOR_DEPTH_R8G8B8A8; | |
47 | ||
48 | case DRM_FORMAT_XRGB8888: | |
49 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
50 | ||
51 | case DRM_FORMAT_RGB565: | |
52 | return WIN_COLOR_DEPTH_B5G6R5; | |
53 | ||
54 | case DRM_FORMAT_UYVY: | |
55 | return WIN_COLOR_DEPTH_YCbCr422; | |
56 | ||
57 | case DRM_FORMAT_YUYV: | |
58 | if (swap) | |
59 | *swap = BYTE_SWAP_SWAP2; | |
60 | ||
61 | return WIN_COLOR_DEPTH_YCbCr422; | |
62 | ||
63 | case DRM_FORMAT_YUV420: | |
64 | return WIN_COLOR_DEPTH_YCbCr420P; | |
65 | ||
66 | case DRM_FORMAT_YUV422: | |
67 | return WIN_COLOR_DEPTH_YCbCr422P; | |
68 | ||
69 | default: | |
70 | break; | |
71 | } | |
72 | ||
73 | WARN(1, "unsupported pixel format %u, using default\n", format); | |
74 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
75 | } | |
76 | ||
77 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) | |
78 | { | |
79 | switch (format) { | |
80 | case WIN_COLOR_DEPTH_YCbCr422: | |
81 | case WIN_COLOR_DEPTH_YUV422: | |
82 | if (planar) | |
83 | *planar = false; | |
84 | ||
85 | return true; | |
86 | ||
87 | case WIN_COLOR_DEPTH_YCbCr420P: | |
88 | case WIN_COLOR_DEPTH_YUV420P: | |
89 | case WIN_COLOR_DEPTH_YCbCr422P: | |
90 | case WIN_COLOR_DEPTH_YUV422P: | |
91 | case WIN_COLOR_DEPTH_YCbCr422R: | |
92 | case WIN_COLOR_DEPTH_YUV422R: | |
93 | case WIN_COLOR_DEPTH_YCbCr422RA: | |
94 | case WIN_COLOR_DEPTH_YUV422RA: | |
95 | if (planar) | |
96 | *planar = true; | |
97 | ||
98 | return true; | |
99 | } | |
100 | ||
101 | return false; | |
102 | } | |
103 | ||
104 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, | |
105 | unsigned int bpp) | |
106 | { | |
107 | fixed20_12 outf = dfixed_init(out); | |
108 | fixed20_12 inf = dfixed_init(in); | |
109 | u32 dda_inc; | |
110 | int max; | |
111 | ||
112 | if (v) | |
113 | max = 15; | |
114 | else { | |
115 | switch (bpp) { | |
116 | case 2: | |
117 | max = 8; | |
118 | break; | |
119 | ||
120 | default: | |
121 | WARN_ON_ONCE(1); | |
122 | /* fallthrough */ | |
123 | case 4: | |
124 | max = 4; | |
125 | break; | |
126 | } | |
127 | } | |
128 | ||
129 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); | |
130 | inf.full -= dfixed_const(1); | |
131 | ||
132 | dda_inc = dfixed_div(inf, outf); | |
133 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); | |
134 | ||
135 | return dda_inc; | |
136 | } | |
137 | ||
138 | static inline u32 compute_initial_dda(unsigned int in) | |
139 | { | |
140 | fixed20_12 inf = dfixed_init(in); | |
141 | return dfixed_frac(inf); | |
142 | } | |
143 | ||
144 | static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |
145 | const struct tegra_dc_window *window) | |
146 | { | |
147 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | |
148 | unsigned long value; | |
149 | bool yuv, planar; | |
150 | ||
151 | /* | |
152 | * For YUV planar modes, the number of bytes per pixel takes into | |
153 | * account only the luma component and therefore is 1. | |
154 | */ | |
155 | yuv = tegra_dc_format_is_yuv(window->format, &planar); | |
156 | if (!yuv) | |
157 | bpp = window->bits_per_pixel / 8; | |
158 | else | |
159 | bpp = planar ? 1 : 2; | |
160 | ||
161 | value = WINDOW_A_SELECT << index; | |
162 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
163 | ||
164 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); | |
165 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); | |
166 | ||
167 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); | |
168 | tegra_dc_writel(dc, value, DC_WIN_POSITION); | |
169 | ||
170 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); | |
171 | tegra_dc_writel(dc, value, DC_WIN_SIZE); | |
172 | ||
173 | h_offset = window->src.x * bpp; | |
174 | v_offset = window->src.y; | |
175 | h_size = window->src.w * bpp; | |
176 | v_size = window->src.h; | |
177 | ||
178 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); | |
179 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); | |
180 | ||
181 | /* | |
182 | * For DDA computations the number of bytes per pixel for YUV planar | |
183 | * modes needs to take into account all Y, U and V components. | |
184 | */ | |
185 | if (yuv && planar) | |
186 | bpp = 2; | |
187 | ||
188 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); | |
189 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); | |
190 | ||
191 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); | |
192 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); | |
193 | ||
194 | h_dda = compute_initial_dda(window->src.x); | |
195 | v_dda = compute_initial_dda(window->src.y); | |
196 | ||
197 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); | |
198 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); | |
199 | ||
200 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); | |
201 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); | |
202 | ||
203 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); | |
204 | ||
205 | if (yuv && planar) { | |
206 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); | |
207 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); | |
208 | value = window->stride[1] << 16 | window->stride[0]; | |
209 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); | |
210 | } else { | |
211 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); | |
212 | } | |
213 | ||
214 | if (window->bottom_up) | |
215 | v_offset += window->src.h - 1; | |
216 | ||
217 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
218 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
219 | ||
c134f019 TR |
220 | if (dc->soc->supports_block_linear) { |
221 | unsigned long height = window->tiling.value; | |
222 | ||
223 | switch (window->tiling.mode) { | |
224 | case TEGRA_BO_TILING_MODE_PITCH: | |
225 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
226 | break; | |
227 | ||
228 | case TEGRA_BO_TILING_MODE_TILED: | |
229 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
230 | break; | |
231 | ||
232 | case TEGRA_BO_TILING_MODE_BLOCK: | |
233 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
234 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
235 | break; | |
236 | } | |
237 | ||
238 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
10288eea | 239 | } else { |
c134f019 TR |
240 | switch (window->tiling.mode) { |
241 | case TEGRA_BO_TILING_MODE_PITCH: | |
242 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
243 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
244 | break; | |
10288eea | 245 | |
c134f019 TR |
246 | case TEGRA_BO_TILING_MODE_TILED: |
247 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
248 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
249 | break; | |
250 | ||
251 | case TEGRA_BO_TILING_MODE_BLOCK: | |
252 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
253 | return -EINVAL; | |
254 | } | |
255 | ||
256 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
257 | } | |
10288eea TR |
258 | |
259 | value = WIN_ENABLE; | |
260 | ||
261 | if (yuv) { | |
262 | /* setup default colorspace conversion coefficients */ | |
263 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); | |
264 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); | |
265 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); | |
266 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); | |
267 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); | |
268 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); | |
269 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); | |
270 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); | |
271 | ||
272 | value |= CSC_ENABLE; | |
273 | } else if (window->bits_per_pixel < 24) { | |
274 | value |= COLOR_EXPAND; | |
275 | } | |
276 | ||
277 | if (window->bottom_up) | |
278 | value |= V_DIRECTION; | |
279 | ||
280 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
281 | ||
282 | /* | |
283 | * Disable blending and assume Window A is the bottom-most window, | |
284 | * Window C is the top-most window and Window B is in the middle. | |
285 | */ | |
286 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); | |
287 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); | |
288 | ||
289 | switch (index) { | |
290 | case 0: | |
291 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); | |
292 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
293 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
294 | break; | |
295 | ||
296 | case 1: | |
297 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
298 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
299 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
300 | break; | |
301 | ||
302 | case 2: | |
303 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
304 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); | |
305 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); | |
306 | break; | |
307 | } | |
308 | ||
309 | tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL); | |
310 | tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
f34bc787 TR |
315 | static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, |
316 | struct drm_framebuffer *fb, int crtc_x, | |
317 | int crtc_y, unsigned int crtc_w, | |
318 | unsigned int crtc_h, uint32_t src_x, | |
319 | uint32_t src_y, uint32_t src_w, uint32_t src_h) | |
320 | { | |
321 | struct tegra_plane *p = to_tegra_plane(plane); | |
322 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
323 | struct tegra_dc_window window; | |
324 | unsigned int i; | |
c134f019 | 325 | int err; |
f34bc787 TR |
326 | |
327 | memset(&window, 0, sizeof(window)); | |
328 | window.src.x = src_x >> 16; | |
329 | window.src.y = src_y >> 16; | |
330 | window.src.w = src_w >> 16; | |
331 | window.src.h = src_h >> 16; | |
332 | window.dst.x = crtc_x; | |
333 | window.dst.y = crtc_y; | |
334 | window.dst.w = crtc_w; | |
335 | window.dst.h = crtc_h; | |
f925390e | 336 | window.format = tegra_dc_format(fb->pixel_format, &window.swap); |
f34bc787 | 337 | window.bits_per_pixel = fb->bits_per_pixel; |
db7fbdfd | 338 | window.bottom_up = tegra_fb_is_bottom_up(fb); |
c134f019 TR |
339 | |
340 | err = tegra_fb_get_tiling(fb, &window.tiling); | |
341 | if (err < 0) | |
342 | return err; | |
f34bc787 TR |
343 | |
344 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { | |
de2ba664 | 345 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); |
f34bc787 | 346 | |
de2ba664 | 347 | window.base[i] = bo->paddr + fb->offsets[i]; |
f34bc787 TR |
348 | |
349 | /* | |
350 | * Tegra doesn't support different strides for U and V planes | |
351 | * so we display a warning if the user tries to display a | |
352 | * framebuffer with such a configuration. | |
353 | */ | |
354 | if (i >= 2) { | |
355 | if (fb->pitches[i] != window.stride[1]) | |
356 | DRM_ERROR("unsupported UV-plane configuration\n"); | |
357 | } else { | |
358 | window.stride[i] = fb->pitches[i]; | |
359 | } | |
360 | } | |
361 | ||
362 | return tegra_dc_setup_window(dc, p->index, &window); | |
363 | } | |
364 | ||
365 | static int tegra_plane_disable(struct drm_plane *plane) | |
366 | { | |
367 | struct tegra_dc *dc = to_tegra_dc(plane->crtc); | |
368 | struct tegra_plane *p = to_tegra_plane(plane); | |
369 | unsigned long value; | |
370 | ||
2678aeba TR |
371 | if (!plane->crtc) |
372 | return 0; | |
373 | ||
f34bc787 TR |
374 | value = WINDOW_A_SELECT << p->index; |
375 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
376 | ||
377 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
378 | value &= ~WIN_ENABLE; | |
379 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
380 | ||
381 | tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL); | |
382 | tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | static void tegra_plane_destroy(struct drm_plane *plane) | |
388 | { | |
f002abc1 TR |
389 | struct tegra_plane *p = to_tegra_plane(plane); |
390 | ||
f34bc787 TR |
391 | tegra_plane_disable(plane); |
392 | drm_plane_cleanup(plane); | |
f002abc1 | 393 | kfree(p); |
f34bc787 TR |
394 | } |
395 | ||
396 | static const struct drm_plane_funcs tegra_plane_funcs = { | |
397 | .update_plane = tegra_plane_update, | |
398 | .disable_plane = tegra_plane_disable, | |
399 | .destroy = tegra_plane_destroy, | |
400 | }; | |
401 | ||
402 | static const uint32_t plane_formats[] = { | |
dbe4d9a7 | 403 | DRM_FORMAT_XBGR8888, |
f34bc787 | 404 | DRM_FORMAT_XRGB8888, |
dbe4d9a7 | 405 | DRM_FORMAT_RGB565, |
f34bc787 | 406 | DRM_FORMAT_UYVY, |
f925390e | 407 | DRM_FORMAT_YUYV, |
f34bc787 TR |
408 | DRM_FORMAT_YUV420, |
409 | DRM_FORMAT_YUV422, | |
410 | }; | |
411 | ||
412 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) | |
413 | { | |
414 | unsigned int i; | |
415 | int err = 0; | |
416 | ||
417 | for (i = 0; i < 2; i++) { | |
418 | struct tegra_plane *plane; | |
419 | ||
f002abc1 | 420 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
f34bc787 TR |
421 | if (!plane) |
422 | return -ENOMEM; | |
423 | ||
424 | plane->index = 1 + i; | |
425 | ||
426 | err = drm_plane_init(drm, &plane->base, 1 << dc->pipe, | |
427 | &tegra_plane_funcs, plane_formats, | |
428 | ARRAY_SIZE(plane_formats), false); | |
f002abc1 TR |
429 | if (err < 0) { |
430 | kfree(plane); | |
f34bc787 | 431 | return err; |
f002abc1 | 432 | } |
f34bc787 TR |
433 | } |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
23fb4740 TR |
438 | static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, |
439 | struct drm_framebuffer *fb) | |
440 | { | |
de2ba664 | 441 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); |
db7fbdfd | 442 | unsigned int h_offset = 0, v_offset = 0; |
c134f019 | 443 | struct tegra_bo_tiling tiling; |
f925390e | 444 | unsigned int format, swap; |
23fb4740 | 445 | unsigned long value; |
c134f019 TR |
446 | int err; |
447 | ||
448 | err = tegra_fb_get_tiling(fb, &tiling); | |
449 | if (err < 0) | |
450 | return err; | |
23fb4740 TR |
451 | |
452 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); | |
453 | ||
454 | value = fb->offsets[0] + y * fb->pitches[0] + | |
455 | x * fb->bits_per_pixel / 8; | |
456 | ||
de2ba664 | 457 | tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); |
23fb4740 | 458 | tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); |
f925390e TR |
459 | |
460 | format = tegra_dc_format(fb->pixel_format, &swap); | |
ed683aea | 461 | tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); |
f925390e | 462 | tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP); |
23fb4740 | 463 | |
c134f019 TR |
464 | if (dc->soc->supports_block_linear) { |
465 | unsigned long height = tiling.value; | |
466 | ||
467 | switch (tiling.mode) { | |
468 | case TEGRA_BO_TILING_MODE_PITCH: | |
469 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
470 | break; | |
471 | ||
472 | case TEGRA_BO_TILING_MODE_TILED: | |
473 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
474 | break; | |
475 | ||
476 | case TEGRA_BO_TILING_MODE_BLOCK: | |
477 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
478 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
479 | break; | |
480 | } | |
481 | ||
482 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
773af77f | 483 | } else { |
c134f019 TR |
484 | switch (tiling.mode) { |
485 | case TEGRA_BO_TILING_MODE_PITCH: | |
486 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
487 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
488 | break; | |
773af77f | 489 | |
c134f019 TR |
490 | case TEGRA_BO_TILING_MODE_TILED: |
491 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
492 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
493 | break; | |
494 | ||
495 | case TEGRA_BO_TILING_MODE_BLOCK: | |
496 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
497 | return -EINVAL; | |
498 | } | |
499 | ||
500 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
501 | } | |
773af77f | 502 | |
db7fbdfd TR |
503 | /* make sure bottom-up buffers are properly displayed */ |
504 | if (tegra_fb_is_bottom_up(fb)) { | |
505 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 506 | value |= V_DIRECTION; |
db7fbdfd TR |
507 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
508 | ||
509 | v_offset += fb->height - 1; | |
510 | } else { | |
511 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 512 | value &= ~V_DIRECTION; |
db7fbdfd TR |
513 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
514 | } | |
515 | ||
516 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
517 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
518 | ||
23fb4740 TR |
519 | value = GENERAL_UPDATE | WIN_A_UPDATE; |
520 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); | |
521 | ||
522 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; | |
523 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
6e5ff998 TR |
528 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
529 | { | |
530 | unsigned long value, flags; | |
531 | ||
532 | spin_lock_irqsave(&dc->lock, flags); | |
533 | ||
534 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
535 | value |= VBLANK_INT; | |
536 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
537 | ||
538 | spin_unlock_irqrestore(&dc->lock, flags); | |
539 | } | |
540 | ||
541 | void tegra_dc_disable_vblank(struct tegra_dc *dc) | |
542 | { | |
543 | unsigned long value, flags; | |
544 | ||
545 | spin_lock_irqsave(&dc->lock, flags); | |
546 | ||
547 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
548 | value &= ~VBLANK_INT; | |
549 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
550 | ||
551 | spin_unlock_irqrestore(&dc->lock, flags); | |
552 | } | |
553 | ||
e687651b TR |
554 | static int tegra_dc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file, |
555 | uint32_t handle, uint32_t width, | |
556 | uint32_t height, int32_t hot_x, int32_t hot_y) | |
557 | { | |
558 | unsigned long value = CURSOR_CLIP_DISPLAY; | |
559 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
560 | struct drm_gem_object *gem; | |
561 | struct tegra_bo *bo = NULL; | |
562 | ||
563 | if (!dc->soc->supports_cursor) | |
564 | return -ENXIO; | |
565 | ||
566 | if (width != height) | |
567 | return -EINVAL; | |
568 | ||
569 | switch (width) { | |
570 | case 32: | |
571 | value |= CURSOR_SIZE_32x32; | |
572 | break; | |
573 | ||
574 | case 64: | |
575 | value |= CURSOR_SIZE_64x64; | |
576 | break; | |
577 | ||
578 | case 128: | |
579 | value |= CURSOR_SIZE_128x128; | |
580 | ||
581 | case 256: | |
582 | value |= CURSOR_SIZE_256x256; | |
583 | break; | |
584 | ||
585 | default: | |
586 | return -EINVAL; | |
587 | } | |
588 | ||
589 | if (handle) { | |
590 | gem = drm_gem_object_lookup(crtc->dev, file, handle); | |
591 | if (!gem) | |
592 | return -ENOENT; | |
593 | ||
594 | bo = to_tegra_bo(gem); | |
595 | } | |
596 | ||
597 | if (bo) { | |
598 | unsigned long addr = (bo->paddr & 0xfffffc00) >> 10; | |
599 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
600 | unsigned long high = (bo->paddr & 0xfffffffc) >> 32; | |
601 | #endif | |
602 | ||
603 | tegra_dc_writel(dc, value | addr, DC_DISP_CURSOR_START_ADDR); | |
604 | ||
605 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
606 | tegra_dc_writel(dc, high, DC_DISP_CURSOR_START_ADDR_HI); | |
607 | #endif | |
608 | ||
609 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
610 | value |= CURSOR_ENABLE; | |
611 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
612 | ||
613 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); | |
614 | value &= ~CURSOR_DST_BLEND_MASK; | |
615 | value &= ~CURSOR_SRC_BLEND_MASK; | |
616 | value |= CURSOR_MODE_NORMAL; | |
617 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; | |
618 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; | |
619 | value |= CURSOR_ALPHA; | |
620 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); | |
621 | } else { | |
622 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
623 | value &= ~CURSOR_ENABLE; | |
624 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
625 | } | |
626 | ||
627 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
628 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); | |
629 | ||
630 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
631 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static int tegra_dc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
637 | { | |
638 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
639 | unsigned long value; | |
640 | ||
641 | if (!dc->soc->supports_cursor) | |
642 | return -ENXIO; | |
643 | ||
644 | value = ((y & 0x3fff) << 16) | (x & 0x3fff); | |
645 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); | |
646 | ||
647 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
648 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); | |
649 | ||
650 | /* XXX: only required on generations earlier than Tegra124? */ | |
651 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
652 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
3c03c46a TR |
657 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
658 | { | |
659 | struct drm_device *drm = dc->base.dev; | |
660 | struct drm_crtc *crtc = &dc->base; | |
3c03c46a | 661 | unsigned long flags, base; |
de2ba664 | 662 | struct tegra_bo *bo; |
3c03c46a TR |
663 | |
664 | if (!dc->event) | |
665 | return; | |
666 | ||
f4510a27 | 667 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
3c03c46a TR |
668 | |
669 | /* check if new start address has been latched */ | |
670 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | |
671 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | |
672 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
673 | ||
f4510a27 | 674 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
3c03c46a TR |
675 | spin_lock_irqsave(&drm->event_lock, flags); |
676 | drm_send_vblank_event(drm, dc->pipe, dc->event); | |
677 | drm_vblank_put(drm, dc->pipe); | |
678 | dc->event = NULL; | |
679 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
680 | } | |
681 | } | |
682 | ||
683 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | |
684 | { | |
685 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
686 | struct drm_device *drm = crtc->dev; | |
687 | unsigned long flags; | |
688 | ||
689 | spin_lock_irqsave(&drm->event_lock, flags); | |
690 | ||
691 | if (dc->event && dc->event->base.file_priv == file) { | |
692 | dc->event->base.destroy(&dc->event->base); | |
693 | drm_vblank_put(drm, dc->pipe); | |
694 | dc->event = NULL; | |
695 | } | |
696 | ||
697 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
698 | } | |
699 | ||
700 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
a5b6f74e | 701 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
3c03c46a TR |
702 | { |
703 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
704 | struct drm_device *drm = crtc->dev; | |
705 | ||
706 | if (dc->event) | |
707 | return -EBUSY; | |
708 | ||
709 | if (event) { | |
710 | event->pipe = dc->pipe; | |
711 | dc->event = event; | |
712 | drm_vblank_get(drm, dc->pipe); | |
713 | } | |
714 | ||
715 | tegra_dc_set_base(dc, 0, 0, fb); | |
f4510a27 | 716 | crtc->primary->fb = fb; |
3c03c46a TR |
717 | |
718 | return 0; | |
719 | } | |
720 | ||
f002abc1 TR |
721 | static void drm_crtc_clear(struct drm_crtc *crtc) |
722 | { | |
723 | memset(crtc, 0, sizeof(*crtc)); | |
724 | } | |
725 | ||
726 | static void tegra_dc_destroy(struct drm_crtc *crtc) | |
727 | { | |
728 | drm_crtc_cleanup(crtc); | |
729 | drm_crtc_clear(crtc); | |
730 | } | |
731 | ||
d8f4a9ed | 732 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
e687651b TR |
733 | .cursor_set2 = tegra_dc_cursor_set2, |
734 | .cursor_move = tegra_dc_cursor_move, | |
3c03c46a | 735 | .page_flip = tegra_dc_page_flip, |
d8f4a9ed | 736 | .set_config = drm_crtc_helper_set_config, |
f002abc1 | 737 | .destroy = tegra_dc_destroy, |
d8f4a9ed TR |
738 | }; |
739 | ||
f34bc787 | 740 | static void tegra_crtc_disable(struct drm_crtc *crtc) |
d8f4a9ed | 741 | { |
f002abc1 | 742 | struct tegra_dc *dc = to_tegra_dc(crtc); |
f34bc787 TR |
743 | struct drm_device *drm = crtc->dev; |
744 | struct drm_plane *plane; | |
745 | ||
2b4c3661 | 746 | drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) { |
f34bc787 TR |
747 | if (plane->crtc == crtc) { |
748 | tegra_plane_disable(plane); | |
749 | plane->crtc = NULL; | |
750 | ||
751 | if (plane->fb) { | |
752 | drm_framebuffer_unreference(plane->fb); | |
753 | plane->fb = NULL; | |
754 | } | |
755 | } | |
756 | } | |
f002abc1 TR |
757 | |
758 | drm_vblank_off(drm, dc->pipe); | |
d8f4a9ed TR |
759 | } |
760 | ||
761 | static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, | |
762 | const struct drm_display_mode *mode, | |
763 | struct drm_display_mode *adjusted) | |
764 | { | |
765 | return true; | |
766 | } | |
767 | ||
d8f4a9ed TR |
768 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
769 | struct drm_display_mode *mode) | |
770 | { | |
0444c0ff TR |
771 | unsigned int h_ref_to_sync = 1; |
772 | unsigned int v_ref_to_sync = 1; | |
d8f4a9ed TR |
773 | unsigned long value; |
774 | ||
775 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); | |
776 | ||
777 | value = (v_ref_to_sync << 16) | h_ref_to_sync; | |
778 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); | |
779 | ||
780 | value = ((mode->vsync_end - mode->vsync_start) << 16) | | |
781 | ((mode->hsync_end - mode->hsync_start) << 0); | |
782 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); | |
783 | ||
d8f4a9ed TR |
784 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
785 | ((mode->htotal - mode->hsync_end) << 0); | |
40495089 LS |
786 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
787 | ||
788 | value = ((mode->vsync_start - mode->vdisplay) << 16) | | |
789 | ((mode->hsync_start - mode->hdisplay) << 0); | |
d8f4a9ed TR |
790 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
791 | ||
792 | value = (mode->vdisplay << 16) | mode->hdisplay; | |
793 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | static int tegra_crtc_setup_clk(struct drm_crtc *crtc, | |
dbb3f2f7 | 799 | struct drm_display_mode *mode) |
d8f4a9ed | 800 | { |
91eded9b | 801 | unsigned long pclk = mode->clock * 1000; |
d8f4a9ed TR |
802 | struct tegra_dc *dc = to_tegra_dc(crtc); |
803 | struct tegra_output *output = NULL; | |
804 | struct drm_encoder *encoder; | |
dbb3f2f7 TR |
805 | unsigned int div; |
806 | u32 value; | |
d8f4a9ed TR |
807 | long err; |
808 | ||
809 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head) | |
810 | if (encoder->crtc == crtc) { | |
811 | output = encoder_to_output(encoder); | |
812 | break; | |
813 | } | |
814 | ||
815 | if (!output) | |
816 | return -ENODEV; | |
817 | ||
818 | /* | |
91eded9b TR |
819 | * This assumes that the parent clock is pll_d_out0 or pll_d2_out |
820 | * respectively, each of which divides the base pll_d by 2. | |
d8f4a9ed | 821 | */ |
91eded9b | 822 | err = tegra_output_setup_clock(output, dc->clk, pclk, &div); |
d8f4a9ed TR |
823 | if (err < 0) { |
824 | dev_err(dc->dev, "failed to setup clock: %ld\n", err); | |
825 | return err; | |
826 | } | |
827 | ||
91eded9b | 828 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); |
d8f4a9ed | 829 | |
dbb3f2f7 TR |
830 | value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; |
831 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); | |
d8f4a9ed TR |
832 | |
833 | return 0; | |
834 | } | |
835 | ||
836 | static int tegra_crtc_mode_set(struct drm_crtc *crtc, | |
837 | struct drm_display_mode *mode, | |
838 | struct drm_display_mode *adjusted, | |
839 | int x, int y, struct drm_framebuffer *old_fb) | |
840 | { | |
f4510a27 | 841 | struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
d8f4a9ed | 842 | struct tegra_dc *dc = to_tegra_dc(crtc); |
f34bc787 | 843 | struct tegra_dc_window window; |
dbb3f2f7 | 844 | u32 value; |
d8f4a9ed TR |
845 | int err; |
846 | ||
6e5ff998 TR |
847 | drm_vblank_pre_modeset(crtc->dev, dc->pipe); |
848 | ||
dbb3f2f7 | 849 | err = tegra_crtc_setup_clk(crtc, mode); |
d8f4a9ed TR |
850 | if (err) { |
851 | dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err); | |
852 | return err; | |
853 | } | |
854 | ||
855 | /* program display mode */ | |
856 | tegra_dc_set_timings(dc, mode); | |
857 | ||
8620fc62 TR |
858 | /* interlacing isn't supported yet, so disable it */ |
859 | if (dc->soc->supports_interlacing) { | |
860 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); | |
861 | value &= ~INTERLACE_ENABLE; | |
862 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); | |
863 | } | |
864 | ||
d8f4a9ed | 865 | /* setup window parameters */ |
f34bc787 TR |
866 | memset(&window, 0, sizeof(window)); |
867 | window.src.x = 0; | |
868 | window.src.y = 0; | |
869 | window.src.w = mode->hdisplay; | |
870 | window.src.h = mode->vdisplay; | |
871 | window.dst.x = 0; | |
872 | window.dst.y = 0; | |
873 | window.dst.w = mode->hdisplay; | |
874 | window.dst.h = mode->vdisplay; | |
f925390e TR |
875 | window.format = tegra_dc_format(crtc->primary->fb->pixel_format, |
876 | &window.swap); | |
f4510a27 MR |
877 | window.bits_per_pixel = crtc->primary->fb->bits_per_pixel; |
878 | window.stride[0] = crtc->primary->fb->pitches[0]; | |
de2ba664 | 879 | window.base[0] = bo->paddr; |
f34bc787 TR |
880 | |
881 | err = tegra_dc_setup_window(dc, 0, &window); | |
882 | if (err < 0) | |
883 | dev_err(dc->dev, "failed to enable root plane\n"); | |
d8f4a9ed | 884 | |
d8f4a9ed TR |
885 | return 0; |
886 | } | |
d8f4a9ed | 887 | |
23fb4740 TR |
888 | static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
889 | struct drm_framebuffer *old_fb) | |
890 | { | |
891 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
d8f4a9ed | 892 | |
f4510a27 | 893 | return tegra_dc_set_base(dc, x, y, crtc->primary->fb); |
d8f4a9ed TR |
894 | } |
895 | ||
896 | static void tegra_crtc_prepare(struct drm_crtc *crtc) | |
897 | { | |
898 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
899 | unsigned int syncpt; | |
900 | unsigned long value; | |
901 | ||
902 | /* hardware initialization */ | |
ca48080a | 903 | reset_control_deassert(dc->rst); |
d8f4a9ed TR |
904 | usleep_range(10000, 20000); |
905 | ||
906 | if (dc->pipe) | |
907 | syncpt = SYNCPT_VBLANK1; | |
908 | else | |
909 | syncpt = SYNCPT_VBLANK0; | |
910 | ||
911 | /* initialize display controller */ | |
912 | tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
913 | tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); | |
914 | ||
915 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; | |
916 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); | |
917 | ||
918 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
919 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
920 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); | |
921 | ||
d8f4a9ed TR |
922 | /* initialize timer */ |
923 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | | |
924 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); | |
925 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
926 | ||
927 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | | |
928 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); | |
929 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
930 | ||
d8f4a9ed TR |
931 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
932 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); | |
6e5ff998 TR |
933 | |
934 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; | |
935 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
d8f4a9ed TR |
936 | } |
937 | ||
938 | static void tegra_crtc_commit(struct drm_crtc *crtc) | |
939 | { | |
940 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
d8f4a9ed TR |
941 | unsigned long value; |
942 | ||
3b9e71ea TR |
943 | value = GENERAL_UPDATE | WIN_A_UPDATE; |
944 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); | |
d8f4a9ed | 945 | |
3b9e71ea | 946 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
6e5ff998 | 947 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
d8f4a9ed | 948 | |
6e5ff998 | 949 | drm_vblank_post_modeset(crtc->dev, dc->pipe); |
d8f4a9ed TR |
950 | } |
951 | ||
952 | static void tegra_crtc_load_lut(struct drm_crtc *crtc) | |
953 | { | |
954 | } | |
955 | ||
956 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { | |
f34bc787 | 957 | .disable = tegra_crtc_disable, |
d8f4a9ed TR |
958 | .mode_fixup = tegra_crtc_mode_fixup, |
959 | .mode_set = tegra_crtc_mode_set, | |
23fb4740 | 960 | .mode_set_base = tegra_crtc_mode_set_base, |
d8f4a9ed TR |
961 | .prepare = tegra_crtc_prepare, |
962 | .commit = tegra_crtc_commit, | |
963 | .load_lut = tegra_crtc_load_lut, | |
964 | }; | |
965 | ||
6e5ff998 | 966 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
d8f4a9ed TR |
967 | { |
968 | struct tegra_dc *dc = data; | |
969 | unsigned long status; | |
970 | ||
971 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); | |
972 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); | |
973 | ||
974 | if (status & FRAME_END_INT) { | |
975 | /* | |
976 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); | |
977 | */ | |
978 | } | |
979 | ||
980 | if (status & VBLANK_INT) { | |
981 | /* | |
982 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | |
983 | */ | |
984 | drm_handle_vblank(dc->base.dev, dc->pipe); | |
3c03c46a | 985 | tegra_dc_finish_page_flip(dc); |
d8f4a9ed TR |
986 | } |
987 | ||
988 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { | |
989 | /* | |
990 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); | |
991 | */ | |
992 | } | |
993 | ||
994 | return IRQ_HANDLED; | |
995 | } | |
996 | ||
997 | static int tegra_dc_show_regs(struct seq_file *s, void *data) | |
998 | { | |
999 | struct drm_info_node *node = s->private; | |
1000 | struct tegra_dc *dc = node->info_ent->data; | |
1001 | ||
1002 | #define DUMP_REG(name) \ | |
1003 | seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \ | |
1004 | tegra_dc_readl(dc, name)) | |
1005 | ||
1006 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); | |
1007 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1008 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); | |
1009 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); | |
1010 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); | |
1011 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); | |
1012 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); | |
1013 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); | |
1014 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); | |
1015 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); | |
1016 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); | |
1017 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); | |
1018 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); | |
1019 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); | |
1020 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); | |
1021 | DUMP_REG(DC_CMD_SIGNAL_RAISE); | |
1022 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); | |
1023 | DUMP_REG(DC_CMD_INT_STATUS); | |
1024 | DUMP_REG(DC_CMD_INT_MASK); | |
1025 | DUMP_REG(DC_CMD_INT_ENABLE); | |
1026 | DUMP_REG(DC_CMD_INT_TYPE); | |
1027 | DUMP_REG(DC_CMD_INT_POLARITY); | |
1028 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); | |
1029 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); | |
1030 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); | |
1031 | DUMP_REG(DC_CMD_STATE_ACCESS); | |
1032 | DUMP_REG(DC_CMD_STATE_CONTROL); | |
1033 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); | |
1034 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); | |
1035 | DUMP_REG(DC_COM_CRC_CONTROL); | |
1036 | DUMP_REG(DC_COM_CRC_CHECKSUM); | |
1037 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); | |
1038 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); | |
1039 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); | |
1040 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); | |
1041 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); | |
1042 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); | |
1043 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); | |
1044 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); | |
1045 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); | |
1046 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); | |
1047 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); | |
1048 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); | |
1049 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); | |
1050 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); | |
1051 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); | |
1052 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); | |
1053 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); | |
1054 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); | |
1055 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); | |
1056 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); | |
1057 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); | |
1058 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); | |
1059 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); | |
1060 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); | |
1061 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); | |
1062 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); | |
1063 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); | |
1064 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); | |
1065 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); | |
1066 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); | |
1067 | DUMP_REG(DC_COM_SPI_CONTROL); | |
1068 | DUMP_REG(DC_COM_SPI_START_BYTE); | |
1069 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); | |
1070 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); | |
1071 | DUMP_REG(DC_COM_HSPI_CS_DC); | |
1072 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); | |
1073 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); | |
1074 | DUMP_REG(DC_COM_GPIO_CTRL); | |
1075 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); | |
1076 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); | |
1077 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); | |
1078 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); | |
1079 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); | |
1080 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1081 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1082 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); | |
1083 | DUMP_REG(DC_DISP_REF_TO_SYNC); | |
1084 | DUMP_REG(DC_DISP_SYNC_WIDTH); | |
1085 | DUMP_REG(DC_DISP_BACK_PORCH); | |
1086 | DUMP_REG(DC_DISP_ACTIVE); | |
1087 | DUMP_REG(DC_DISP_FRONT_PORCH); | |
1088 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); | |
1089 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); | |
1090 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); | |
1091 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); | |
1092 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); | |
1093 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); | |
1094 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); | |
1095 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); | |
1096 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); | |
1097 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); | |
1098 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); | |
1099 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); | |
1100 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); | |
1101 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); | |
1102 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); | |
1103 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); | |
1104 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); | |
1105 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); | |
1106 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); | |
1107 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); | |
1108 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); | |
1109 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); | |
1110 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); | |
1111 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); | |
1112 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); | |
1113 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); | |
1114 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); | |
1115 | DUMP_REG(DC_DISP_M0_CONTROL); | |
1116 | DUMP_REG(DC_DISP_M1_CONTROL); | |
1117 | DUMP_REG(DC_DISP_DI_CONTROL); | |
1118 | DUMP_REG(DC_DISP_PP_CONTROL); | |
1119 | DUMP_REG(DC_DISP_PP_SELECT_A); | |
1120 | DUMP_REG(DC_DISP_PP_SELECT_B); | |
1121 | DUMP_REG(DC_DISP_PP_SELECT_C); | |
1122 | DUMP_REG(DC_DISP_PP_SELECT_D); | |
1123 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); | |
1124 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); | |
1125 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); | |
1126 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); | |
1127 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); | |
1128 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); | |
1129 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); | |
1130 | DUMP_REG(DC_DISP_BORDER_COLOR); | |
1131 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); | |
1132 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); | |
1133 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); | |
1134 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); | |
1135 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); | |
1136 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); | |
1137 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); | |
1138 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); | |
1139 | DUMP_REG(DC_DISP_CURSOR_POSITION); | |
1140 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); | |
1141 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); | |
1142 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); | |
1143 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); | |
1144 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); | |
1145 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); | |
1146 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); | |
1147 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); | |
1148 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); | |
1149 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); | |
1150 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); | |
1151 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); | |
1152 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); | |
1153 | DUMP_REG(DC_DISP_SD_CONTROL); | |
1154 | DUMP_REG(DC_DISP_SD_CSC_COEFF); | |
1155 | DUMP_REG(DC_DISP_SD_LUT(0)); | |
1156 | DUMP_REG(DC_DISP_SD_LUT(1)); | |
1157 | DUMP_REG(DC_DISP_SD_LUT(2)); | |
1158 | DUMP_REG(DC_DISP_SD_LUT(3)); | |
1159 | DUMP_REG(DC_DISP_SD_LUT(4)); | |
1160 | DUMP_REG(DC_DISP_SD_LUT(5)); | |
1161 | DUMP_REG(DC_DISP_SD_LUT(6)); | |
1162 | DUMP_REG(DC_DISP_SD_LUT(7)); | |
1163 | DUMP_REG(DC_DISP_SD_LUT(8)); | |
1164 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); | |
1165 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); | |
1166 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); | |
1167 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); | |
1168 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); | |
1169 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); | |
1170 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); | |
1171 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); | |
1172 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); | |
1173 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); | |
1174 | DUMP_REG(DC_DISP_SD_BL_TF(0)); | |
1175 | DUMP_REG(DC_DISP_SD_BL_TF(1)); | |
1176 | DUMP_REG(DC_DISP_SD_BL_TF(2)); | |
1177 | DUMP_REG(DC_DISP_SD_BL_TF(3)); | |
1178 | DUMP_REG(DC_DISP_SD_BL_CONTROL); | |
1179 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); | |
1180 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); | |
e687651b TR |
1181 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
1182 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); | |
d8f4a9ed TR |
1183 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
1184 | DUMP_REG(DC_WIN_BYTE_SWAP); | |
1185 | DUMP_REG(DC_WIN_BUFFER_CONTROL); | |
1186 | DUMP_REG(DC_WIN_COLOR_DEPTH); | |
1187 | DUMP_REG(DC_WIN_POSITION); | |
1188 | DUMP_REG(DC_WIN_SIZE); | |
1189 | DUMP_REG(DC_WIN_PRESCALED_SIZE); | |
1190 | DUMP_REG(DC_WIN_H_INITIAL_DDA); | |
1191 | DUMP_REG(DC_WIN_V_INITIAL_DDA); | |
1192 | DUMP_REG(DC_WIN_DDA_INC); | |
1193 | DUMP_REG(DC_WIN_LINE_STRIDE); | |
1194 | DUMP_REG(DC_WIN_BUF_STRIDE); | |
1195 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); | |
1196 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); | |
1197 | DUMP_REG(DC_WIN_DV_CONTROL); | |
1198 | DUMP_REG(DC_WIN_BLEND_NOKEY); | |
1199 | DUMP_REG(DC_WIN_BLEND_1WIN); | |
1200 | DUMP_REG(DC_WIN_BLEND_2WIN_X); | |
1201 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); | |
f34bc787 | 1202 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
d8f4a9ed TR |
1203 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
1204 | DUMP_REG(DC_WINBUF_START_ADDR); | |
1205 | DUMP_REG(DC_WINBUF_START_ADDR_NS); | |
1206 | DUMP_REG(DC_WINBUF_START_ADDR_U); | |
1207 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); | |
1208 | DUMP_REG(DC_WINBUF_START_ADDR_V); | |
1209 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); | |
1210 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); | |
1211 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); | |
1212 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); | |
1213 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); | |
1214 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); | |
1215 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); | |
1216 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); | |
1217 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); | |
1218 | ||
1219 | #undef DUMP_REG | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | static struct drm_info_list debugfs_files[] = { | |
1225 | { "regs", tegra_dc_show_regs, 0, NULL }, | |
1226 | }; | |
1227 | ||
1228 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) | |
1229 | { | |
1230 | unsigned int i; | |
1231 | char *name; | |
1232 | int err; | |
1233 | ||
1234 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); | |
1235 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
1236 | kfree(name); | |
1237 | ||
1238 | if (!dc->debugfs) | |
1239 | return -ENOMEM; | |
1240 | ||
1241 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1242 | GFP_KERNEL); | |
1243 | if (!dc->debugfs_files) { | |
1244 | err = -ENOMEM; | |
1245 | goto remove; | |
1246 | } | |
1247 | ||
1248 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1249 | dc->debugfs_files[i].data = dc; | |
1250 | ||
1251 | err = drm_debugfs_create_files(dc->debugfs_files, | |
1252 | ARRAY_SIZE(debugfs_files), | |
1253 | dc->debugfs, minor); | |
1254 | if (err < 0) | |
1255 | goto free; | |
1256 | ||
1257 | dc->minor = minor; | |
1258 | ||
1259 | return 0; | |
1260 | ||
1261 | free: | |
1262 | kfree(dc->debugfs_files); | |
1263 | dc->debugfs_files = NULL; | |
1264 | remove: | |
1265 | debugfs_remove(dc->debugfs); | |
1266 | dc->debugfs = NULL; | |
1267 | ||
1268 | return err; | |
1269 | } | |
1270 | ||
1271 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) | |
1272 | { | |
1273 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1274 | dc->minor); | |
1275 | dc->minor = NULL; | |
1276 | ||
1277 | kfree(dc->debugfs_files); | |
1278 | dc->debugfs_files = NULL; | |
1279 | ||
1280 | debugfs_remove(dc->debugfs); | |
1281 | dc->debugfs = NULL; | |
1282 | ||
1283 | return 0; | |
1284 | } | |
1285 | ||
53fa7f72 | 1286 | static int tegra_dc_init(struct host1x_client *client) |
d8f4a9ed | 1287 | { |
9910f5c4 | 1288 | struct drm_device *drm = dev_get_drvdata(client->parent); |
776dc384 | 1289 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d1f3e1e0 | 1290 | struct tegra_drm *tegra = drm->dev_private; |
d8f4a9ed TR |
1291 | int err; |
1292 | ||
9910f5c4 | 1293 | drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs); |
d8f4a9ed TR |
1294 | drm_mode_crtc_set_gamma_size(&dc->base, 256); |
1295 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); | |
1296 | ||
d1f3e1e0 TR |
1297 | /* |
1298 | * Keep track of the minimum pitch alignment across all display | |
1299 | * controllers. | |
1300 | */ | |
1301 | if (dc->soc->pitch_align > tegra->pitch_align) | |
1302 | tegra->pitch_align = dc->soc->pitch_align; | |
1303 | ||
9910f5c4 | 1304 | err = tegra_dc_rgb_init(drm, dc); |
d8f4a9ed TR |
1305 | if (err < 0 && err != -ENODEV) { |
1306 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); | |
1307 | return err; | |
1308 | } | |
1309 | ||
9910f5c4 | 1310 | err = tegra_dc_add_planes(drm, dc); |
f34bc787 TR |
1311 | if (err < 0) |
1312 | return err; | |
1313 | ||
d8f4a9ed | 1314 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
9910f5c4 | 1315 | err = tegra_dc_debugfs_init(dc, drm->primary); |
d8f4a9ed TR |
1316 | if (err < 0) |
1317 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); | |
1318 | } | |
1319 | ||
6e5ff998 | 1320 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
d8f4a9ed TR |
1321 | dev_name(dc->dev), dc); |
1322 | if (err < 0) { | |
1323 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, | |
1324 | err); | |
1325 | return err; | |
1326 | } | |
1327 | ||
1328 | return 0; | |
1329 | } | |
1330 | ||
53fa7f72 | 1331 | static int tegra_dc_exit(struct host1x_client *client) |
d8f4a9ed | 1332 | { |
776dc384 | 1333 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d8f4a9ed TR |
1334 | int err; |
1335 | ||
1336 | devm_free_irq(dc->dev, dc->irq, dc); | |
1337 | ||
1338 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1339 | err = tegra_dc_debugfs_exit(dc); | |
1340 | if (err < 0) | |
1341 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); | |
1342 | } | |
1343 | ||
1344 | err = tegra_dc_rgb_exit(dc); | |
1345 | if (err) { | |
1346 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); | |
1347 | return err; | |
1348 | } | |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
1353 | static const struct host1x_client_ops dc_client_ops = { | |
53fa7f72 TR |
1354 | .init = tegra_dc_init, |
1355 | .exit = tegra_dc_exit, | |
d8f4a9ed TR |
1356 | }; |
1357 | ||
8620fc62 TR |
1358 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
1359 | .supports_interlacing = false, | |
e687651b | 1360 | .supports_cursor = false, |
c134f019 | 1361 | .supports_block_linear = false, |
d1f3e1e0 | 1362 | .pitch_align = 8, |
9c012700 | 1363 | .has_powergate = false, |
8620fc62 TR |
1364 | }; |
1365 | ||
1366 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { | |
1367 | .supports_interlacing = false, | |
e687651b | 1368 | .supports_cursor = false, |
c134f019 | 1369 | .supports_block_linear = false, |
d1f3e1e0 | 1370 | .pitch_align = 8, |
9c012700 | 1371 | .has_powergate = false, |
d1f3e1e0 TR |
1372 | }; |
1373 | ||
1374 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { | |
1375 | .supports_interlacing = false, | |
1376 | .supports_cursor = false, | |
1377 | .supports_block_linear = false, | |
1378 | .pitch_align = 64, | |
9c012700 | 1379 | .has_powergate = true, |
8620fc62 TR |
1380 | }; |
1381 | ||
1382 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { | |
1383 | .supports_interlacing = true, | |
e687651b | 1384 | .supports_cursor = true, |
c134f019 | 1385 | .supports_block_linear = true, |
d1f3e1e0 | 1386 | .pitch_align = 64, |
9c012700 | 1387 | .has_powergate = true, |
8620fc62 TR |
1388 | }; |
1389 | ||
1390 | static const struct of_device_id tegra_dc_of_match[] = { | |
1391 | { | |
1392 | .compatible = "nvidia,tegra124-dc", | |
1393 | .data = &tegra124_dc_soc_info, | |
9c012700 TR |
1394 | }, { |
1395 | .compatible = "nvidia,tegra114-dc", | |
1396 | .data = &tegra114_dc_soc_info, | |
8620fc62 TR |
1397 | }, { |
1398 | .compatible = "nvidia,tegra30-dc", | |
1399 | .data = &tegra30_dc_soc_info, | |
1400 | }, { | |
1401 | .compatible = "nvidia,tegra20-dc", | |
1402 | .data = &tegra20_dc_soc_info, | |
1403 | }, { | |
1404 | /* sentinel */ | |
1405 | } | |
1406 | }; | |
ef70728c | 1407 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
8620fc62 | 1408 | |
13411ddd TR |
1409 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
1410 | { | |
1411 | struct device_node *np; | |
1412 | u32 value = 0; | |
1413 | int err; | |
1414 | ||
1415 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); | |
1416 | if (err < 0) { | |
1417 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); | |
1418 | ||
1419 | /* | |
1420 | * If the nvidia,head property isn't present, try to find the | |
1421 | * correct head number by looking up the position of this | |
1422 | * display controller's node within the device tree. Assuming | |
1423 | * that the nodes are ordered properly in the DTS file and | |
1424 | * that the translation into a flattened device tree blob | |
1425 | * preserves that ordering this will actually yield the right | |
1426 | * head number. | |
1427 | * | |
1428 | * If those assumptions don't hold, this will still work for | |
1429 | * cases where only a single display controller is used. | |
1430 | */ | |
1431 | for_each_matching_node(np, tegra_dc_of_match) { | |
1432 | if (np == dc->dev->of_node) | |
1433 | break; | |
1434 | ||
1435 | value++; | |
1436 | } | |
1437 | } | |
1438 | ||
1439 | dc->pipe = value; | |
1440 | ||
1441 | return 0; | |
1442 | } | |
1443 | ||
d8f4a9ed TR |
1444 | static int tegra_dc_probe(struct platform_device *pdev) |
1445 | { | |
8620fc62 | 1446 | const struct of_device_id *id; |
d8f4a9ed TR |
1447 | struct resource *regs; |
1448 | struct tegra_dc *dc; | |
1449 | int err; | |
1450 | ||
1451 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); | |
1452 | if (!dc) | |
1453 | return -ENOMEM; | |
1454 | ||
8620fc62 TR |
1455 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
1456 | if (!id) | |
1457 | return -ENODEV; | |
1458 | ||
6e5ff998 | 1459 | spin_lock_init(&dc->lock); |
d8f4a9ed TR |
1460 | INIT_LIST_HEAD(&dc->list); |
1461 | dc->dev = &pdev->dev; | |
8620fc62 | 1462 | dc->soc = id->data; |
d8f4a9ed | 1463 | |
13411ddd TR |
1464 | err = tegra_dc_parse_dt(dc); |
1465 | if (err < 0) | |
1466 | return err; | |
1467 | ||
d8f4a9ed TR |
1468 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
1469 | if (IS_ERR(dc->clk)) { | |
1470 | dev_err(&pdev->dev, "failed to get clock\n"); | |
1471 | return PTR_ERR(dc->clk); | |
1472 | } | |
1473 | ||
ca48080a SW |
1474 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
1475 | if (IS_ERR(dc->rst)) { | |
1476 | dev_err(&pdev->dev, "failed to get reset\n"); | |
1477 | return PTR_ERR(dc->rst); | |
1478 | } | |
1479 | ||
9c012700 TR |
1480 | if (dc->soc->has_powergate) { |
1481 | if (dc->pipe == 0) | |
1482 | dc->powergate = TEGRA_POWERGATE_DIS; | |
1483 | else | |
1484 | dc->powergate = TEGRA_POWERGATE_DISB; | |
1485 | ||
1486 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, | |
1487 | dc->rst); | |
1488 | if (err < 0) { | |
1489 | dev_err(&pdev->dev, "failed to power partition: %d\n", | |
1490 | err); | |
1491 | return err; | |
1492 | } | |
1493 | } else { | |
1494 | err = clk_prepare_enable(dc->clk); | |
1495 | if (err < 0) { | |
1496 | dev_err(&pdev->dev, "failed to enable clock: %d\n", | |
1497 | err); | |
1498 | return err; | |
1499 | } | |
1500 | ||
1501 | err = reset_control_deassert(dc->rst); | |
1502 | if (err < 0) { | |
1503 | dev_err(&pdev->dev, "failed to deassert reset: %d\n", | |
1504 | err); | |
1505 | return err; | |
1506 | } | |
1507 | } | |
d8f4a9ed TR |
1508 | |
1509 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1510 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
1511 | if (IS_ERR(dc->regs)) | |
1512 | return PTR_ERR(dc->regs); | |
d8f4a9ed TR |
1513 | |
1514 | dc->irq = platform_get_irq(pdev, 0); | |
1515 | if (dc->irq < 0) { | |
1516 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
1517 | return -ENXIO; | |
1518 | } | |
1519 | ||
776dc384 TR |
1520 | INIT_LIST_HEAD(&dc->client.list); |
1521 | dc->client.ops = &dc_client_ops; | |
1522 | dc->client.dev = &pdev->dev; | |
d8f4a9ed TR |
1523 | |
1524 | err = tegra_dc_rgb_probe(dc); | |
1525 | if (err < 0 && err != -ENODEV) { | |
1526 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); | |
1527 | return err; | |
1528 | } | |
1529 | ||
776dc384 | 1530 | err = host1x_client_register(&dc->client); |
d8f4a9ed TR |
1531 | if (err < 0) { |
1532 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1533 | err); | |
1534 | return err; | |
1535 | } | |
1536 | ||
1537 | platform_set_drvdata(pdev, dc); | |
1538 | ||
1539 | return 0; | |
1540 | } | |
1541 | ||
1542 | static int tegra_dc_remove(struct platform_device *pdev) | |
1543 | { | |
d8f4a9ed TR |
1544 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
1545 | int err; | |
1546 | ||
776dc384 | 1547 | err = host1x_client_unregister(&dc->client); |
d8f4a9ed TR |
1548 | if (err < 0) { |
1549 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1550 | err); | |
1551 | return err; | |
1552 | } | |
1553 | ||
59d29c0e TR |
1554 | err = tegra_dc_rgb_remove(dc); |
1555 | if (err < 0) { | |
1556 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); | |
1557 | return err; | |
1558 | } | |
1559 | ||
5482d75a | 1560 | reset_control_assert(dc->rst); |
9c012700 TR |
1561 | |
1562 | if (dc->soc->has_powergate) | |
1563 | tegra_powergate_power_off(dc->powergate); | |
1564 | ||
d8f4a9ed TR |
1565 | clk_disable_unprepare(dc->clk); |
1566 | ||
1567 | return 0; | |
1568 | } | |
1569 | ||
d8f4a9ed TR |
1570 | struct platform_driver tegra_dc_driver = { |
1571 | .driver = { | |
1572 | .name = "tegra-dc", | |
1573 | .owner = THIS_MODULE, | |
1574 | .of_match_table = tegra_dc_of_match, | |
1575 | }, | |
1576 | .probe = tegra_dc_probe, | |
1577 | .remove = tegra_dc_remove, | |
1578 | }; |