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drm/tegra: Implement .mode_set_base()
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15
16#include <mach/clk.h>
17
18#include "drm.h"
19#include "dc.h"
20
f34bc787
TR		 21struct tegra_plane {
22 struct drm_plane base;
23 unsigned int index;
d8f4a9ed
TR		 24};
25
f34bc787
TR		 26static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
27{
28 return container_of(plane, struct tegra_plane, base);
29}
30
31static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
32 struct drm_framebuffer *fb, int crtc_x,
33 int crtc_y, unsigned int crtc_w,
34 unsigned int crtc_h, uint32_t src_x,
35 uint32_t src_y, uint32_t src_w, uint32_t src_h)
36{
37 struct tegra_plane *p = to_tegra_plane(plane);
38 struct tegra_dc *dc = to_tegra_dc(crtc);
39 struct tegra_dc_window window;
40 unsigned int i;
41
42 memset(&window, 0, sizeof(window));
43 window.src.x = src_x >> 16;
44 window.src.y = src_y >> 16;
45 window.src.w = src_w >> 16;
46 window.src.h = src_h >> 16;
47 window.dst.x = crtc_x;
48 window.dst.y = crtc_y;
49 window.dst.w = crtc_w;
50 window.dst.h = crtc_h;
51 window.format = tegra_dc_format(fb->pixel_format);
52 window.bits_per_pixel = fb->bits_per_pixel;
53
54 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
55 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
56
57 window.base[i] = gem->paddr + fb->offsets[i];
58
59 /*
60 * Tegra doesn't support different strides for U and V planes
61 * so we display a warning if the user tries to display a
62 * framebuffer with such a configuration.
63 */
64 if (i >= 2) {
65 if (fb->pitches[i] != window.stride[1])
66 DRM_ERROR("unsupported UV-plane configuration\n");
67 } else {
68 window.stride[i] = fb->pitches[i];
69 }
70 }
71
72 return tegra_dc_setup_window(dc, p->index, &window);
73}
74
75static int tegra_plane_disable(struct drm_plane *plane)
76{
77 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
78 struct tegra_plane *p = to_tegra_plane(plane);
79 unsigned long value;
80
81 value = WINDOW_A_SELECT << p->index;
82 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
83
84 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
85 value &= ~WIN_ENABLE;
86 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
87
88 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
89 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
90
91 return 0;
92}
93
94static void tegra_plane_destroy(struct drm_plane *plane)
95{
96 tegra_plane_disable(plane);
97 drm_plane_cleanup(plane);
98}
99
100static const struct drm_plane_funcs tegra_plane_funcs = {
101 .update_plane = tegra_plane_update,
102 .disable_plane = tegra_plane_disable,
103 .destroy = tegra_plane_destroy,
104};
105
106static const uint32_t plane_formats[] = {
107 DRM_FORMAT_XRGB8888,
108 DRM_FORMAT_UYVY,
109 DRM_FORMAT_YUV420,
110 DRM_FORMAT_YUV422,
111};
112
113static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
114{
115 unsigned int i;
116 int err = 0;
117
118 for (i = 0; i < 2; i++) {
119 struct tegra_plane *plane;
120
121 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
122 if (!plane)
123 return -ENOMEM;
124
125 plane->index = 1 + i;
126
127 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
128 &tegra_plane_funcs, plane_formats,
129 ARRAY_SIZE(plane_formats), false);
130 if (err < 0)
131 return err;
132 }
133
134 return 0;
135}
136
23fb4740
TR		 137static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
138 struct drm_framebuffer *fb)
139{
140 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, 0);
141 unsigned long value;
142
143 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
144
145 value = fb->offsets[0] + y * fb->pitches[0] +
146 x * fb->bits_per_pixel / 8;
147
148 tegra_dc_writel(dc, gem->paddr + value, DC_WINBUF_START_ADDR);
149 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
150
151 value = GENERAL_UPDATE | WIN_A_UPDATE;
152 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
153
154 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
155 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
156
157 return 0;
158}
159
d8f4a9ed
TR		 160static const struct drm_crtc_funcs tegra_crtc_funcs = {
161 .set_config = drm_crtc_helper_set_config,
162 .destroy = drm_crtc_cleanup,
163};
164
f34bc787 165static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 166{
f34bc787
TR		 167 struct drm_device *drm = crtc->dev;
168 struct drm_plane *plane;
169
170 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
171 if (plane->crtc == crtc) {
172 tegra_plane_disable(plane);
173 plane->crtc = NULL;
174
175 if (plane->fb) {
176 drm_framebuffer_unreference(plane->fb);
177 plane->fb = NULL;
178 }
179 }
180 }
d8f4a9ed
TR		 181}
182
183static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
184 const struct drm_display_mode *mode,
185 struct drm_display_mode *adjusted)
186{
187 return true;
188}
189
f34bc787 190static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 191 unsigned int bpp)
192{
193 fixed20_12 outf = dfixed_init(out);
f34bc787 194 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 195 u32 dda_inc;
196 int max;
197
198 if (v)
199 max = 15;
200 else {
201 switch (bpp) {
202 case 2:
203 max = 8;
204 break;
205
206 default:
207 WARN_ON_ONCE(1);
208 /* fallthrough */
209 case 4:
210 max = 4;
211 break;
212 }
213 }
214
215 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
216 inf.full -= dfixed_const(1);
217
218 dda_inc = dfixed_div(inf, outf);
219 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
220
221 return dda_inc;
222}
223
f34bc787 224static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 225{
f34bc787
TR		 226 fixed20_12 inf = dfixed_init(in);
227 return dfixed_frac(inf);
d8f4a9ed
TR		 228}
229
230static int tegra_dc_set_timings(struct tegra_dc *dc,
231 struct drm_display_mode *mode)
232{
233 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
234 unsigned int h_ref_to_sync = 0;
235 unsigned int v_ref_to_sync = 0;
236 unsigned long value;
237
238 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
239
240 value = (v_ref_to_sync << 16) | h_ref_to_sync;
241 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
242
243 value = ((mode->vsync_end - mode->vsync_start) << 16) |
244 ((mode->hsync_end - mode->hsync_start) << 0);
245 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
246
d8f4a9ed
TR		 247 value = ((mode->vtotal - mode->vsync_end) << 16) |
248 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 249 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
250
251 value = ((mode->vsync_start - mode->vdisplay) << 16) |
252 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 253 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
254
255 value = (mode->vdisplay << 16) | mode->hdisplay;
256 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
257
258 return 0;
259}
260
261static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
262 struct drm_display_mode *mode,
263 unsigned long *div)
264{
265 unsigned long pclk = mode->clock * 1000, rate;
266 struct tegra_dc *dc = to_tegra_dc(crtc);
267 struct tegra_output *output = NULL;
268 struct drm_encoder *encoder;
269 long err;
270
271 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
272 if (encoder->crtc == crtc) {
273 output = encoder_to_output(encoder);
274 break;
275 }
276
277 if (!output)
278 return -ENODEV;
279
280 /*
281 * This assumes that the display controller will divide its parent
282 * clock by 2 to generate the pixel clock.
283 */
284 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
285 if (err < 0) {
286 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
287 return err;
288 }
289
290 rate = clk_get_rate(dc->clk);
291 *div = (rate * 2 / pclk) - 2;
292
293 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
294
295 return 0;
296}
297
f34bc787
TR		 298static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
299{
300 switch (format) {
301 case WIN_COLOR_DEPTH_YCbCr422:
302 case WIN_COLOR_DEPTH_YUV422:
303 if (planar)
304 *planar = false;
305
306 return true;
307
308 case WIN_COLOR_DEPTH_YCbCr420P:
309 case WIN_COLOR_DEPTH_YUV420P:
310 case WIN_COLOR_DEPTH_YCbCr422P:
311 case WIN_COLOR_DEPTH_YUV422P:
312 case WIN_COLOR_DEPTH_YCbCr422R:
313 case WIN_COLOR_DEPTH_YUV422R:
314 case WIN_COLOR_DEPTH_YCbCr422RA:
315 case WIN_COLOR_DEPTH_YUV422RA:
316 if (planar)
317 *planar = true;
318
319 return true;
320 }
321
322 return false;
323}
324
325int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
326 const struct tegra_dc_window *window)
327{
328 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
329 unsigned long value;
330 bool yuv, planar;
331
332 /*
333 * For YUV planar modes, the number of bytes per pixel takes into
334 * account only the luma component and therefore is 1.
335 */
336 yuv = tegra_dc_format_is_yuv(window->format, &planar);
337 if (!yuv)
338 bpp = window->bits_per_pixel / 8;
339 else
340 bpp = planar ? 1 : 2;
341
342 value = WINDOW_A_SELECT << index;
343 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
344
345 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
346 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
347
348 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
349 tegra_dc_writel(dc, value, DC_WIN_POSITION);
350
351 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
352 tegra_dc_writel(dc, value, DC_WIN_SIZE);
353
354 h_offset = window->src.x * bpp;
355 v_offset = window->src.y;
356 h_size = window->src.w * bpp;
357 v_size = window->src.h;
358
359 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
360 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
361
362 /*
363 * For DDA computations the number of bytes per pixel for YUV planar
364 * modes needs to take into account all Y, U and V components.
365 */
366 if (yuv && planar)
367 bpp = 2;
368
369 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
370 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
371
372 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
373 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
374
375 h_dda = compute_initial_dda(window->src.x);
376 v_dda = compute_initial_dda(window->src.y);
377
378 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
379 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
380
381 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
382 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
383
384 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
385
386 if (yuv && planar) {
387 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
388 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
389 value = window->stride[1] << 16 | window->stride[0];
390 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
391 } else {
392 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
393 }
394
395 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
396 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
397
398 value = WIN_ENABLE;
399
400 if (yuv) {
401 /* setup default colorspace conversion coefficients */
402 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
403 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
404 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
405 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
406 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
407 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
408 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
409 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
410
411 value |= CSC_ENABLE;
412 } else if (bpp < 24) {
413 value |= COLOR_EXPAND;
414 }
415
416 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
417
418 /*
419 * Disable blending and assume Window A is the bottom-most window,
420 * Window C is the top-most window and Window B is in the middle.
421 */
422 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
423 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
424
425 switch (index) {
426 case 0:
427 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
428 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
429 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
430 break;
431
432 case 1:
433 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
434 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
435 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
436 break;
437
438 case 2:
439 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
440 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
441 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
442 break;
443 }
444
445 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
446 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
447
448 return 0;
449}
450
451unsigned int tegra_dc_format(uint32_t format)
452{
453 switch (format) {
454 case DRM_FORMAT_XRGB8888:
455 return WIN_COLOR_DEPTH_B8G8R8A8;
456
457 case DRM_FORMAT_RGB565:
458 return WIN_COLOR_DEPTH_B5G6R5;
459
460 case DRM_FORMAT_UYVY:
461 return WIN_COLOR_DEPTH_YCbCr422;
462
463 case DRM_FORMAT_YUV420:
464 return WIN_COLOR_DEPTH_YCbCr420P;
465
466 case DRM_FORMAT_YUV422:
467 return WIN_COLOR_DEPTH_YCbCr422P;
468
469 default:
470 break;
471 }
472
473 WARN(1, "unsupported pixel format %u, using default\n", format);
474 return WIN_COLOR_DEPTH_B8G8R8A8;
475}
476
d8f4a9ed
TR		 477static int tegra_crtc_mode_set(struct drm_crtc *crtc,
478 struct drm_display_mode *mode,
479 struct drm_display_mode *adjusted,
480 int x, int y, struct drm_framebuffer *old_fb)
481{
894752bb 482 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(crtc->fb, 0);
d8f4a9ed 483 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 484 struct tegra_dc_window window;
d8f4a9ed
TR		 485 unsigned long div, value;
486 int err;
487
488 err = tegra_crtc_setup_clk(crtc, mode, &div);
489 if (err) {
490 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
491 return err;
492 }
493
494 /* program display mode */
495 tegra_dc_set_timings(dc, mode);
496
497 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
498 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
499
500 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
501 value &= ~LVS_OUTPUT_POLARITY_LOW;
502 value &= ~LHS_OUTPUT_POLARITY_LOW;
503 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
504
505 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
506 DISP_ORDER_RED_BLUE;
507 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
508
509 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
510
511 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
512 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
513
514 /* setup window parameters */
f34bc787
TR		 515 memset(&window, 0, sizeof(window));
516 window.src.x = 0;
517 window.src.y = 0;
518 window.src.w = mode->hdisplay;
519 window.src.h = mode->vdisplay;
520 window.dst.x = 0;
521 window.dst.y = 0;
522 window.dst.w = mode->hdisplay;
523 window.dst.h = mode->vdisplay;
524 window.format = tegra_dc_format(crtc->fb->pixel_format);
525 window.bits_per_pixel = crtc->fb->bits_per_pixel;
526 window.stride[0] = crtc->fb->pitches[0];
527 window.base[0] = gem->paddr;
528
529 err = tegra_dc_setup_window(dc, 0, &window);
530 if (err < 0)
531 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed
TR		 532
533 return 0;
534}
535
23fb4740
TR		 536static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
537 struct drm_framebuffer *old_fb)
538{
539 struct tegra_dc *dc = to_tegra_dc(crtc);
540
541 return tegra_dc_set_base(dc, x, y, crtc->fb);
542}
543
d8f4a9ed
TR		 544static void tegra_crtc_prepare(struct drm_crtc *crtc)
545{
546 struct tegra_dc *dc = to_tegra_dc(crtc);
547 unsigned int syncpt;
548 unsigned long value;
549
550 /* hardware initialization */
551 tegra_periph_reset_deassert(dc->clk);
552 usleep_range(10000, 20000);
553
554 if (dc->pipe)
555 syncpt = SYNCPT_VBLANK1;
556 else
557 syncpt = SYNCPT_VBLANK0;
558
559 /* initialize display controller */
560 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
561 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
562
563 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
564 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
565
566 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
567 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
568 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
569
570 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
571 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
572 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
573
574 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
575 value |= DISP_CTRL_MODE_C_DISPLAY;
576 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
577
578 /* initialize timer */
579 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
580 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
581 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
582
583 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
584 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
585 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
586
587 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
588 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
589
590 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
591 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
592}
593
594static void tegra_crtc_commit(struct drm_crtc *crtc)
595{
596 struct tegra_dc *dc = to_tegra_dc(crtc);
597 unsigned long update_mask;
598 unsigned long value;
599
600 update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
601
602 tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
603
604 value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
605 value |= FRAME_END_INT;
606 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
607
608 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
609 value |= FRAME_END_INT;
610 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
611
612 tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
613}
614
615static void tegra_crtc_load_lut(struct drm_crtc *crtc)
616{
617}
618
619static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 620 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 621 .mode_fixup = tegra_crtc_mode_fixup,
622 .mode_set = tegra_crtc_mode_set,
23fb4740 623 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 624 .prepare = tegra_crtc_prepare,
625 .commit = tegra_crtc_commit,
626 .load_lut = tegra_crtc_load_lut,
627};
628
629static irqreturn_t tegra_drm_irq(int irq, void *data)
630{
631 struct tegra_dc *dc = data;
632 unsigned long status;
633
634 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
635 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
636
637 if (status & FRAME_END_INT) {
638 /*
639 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
640 */
641 }
642
643 if (status & VBLANK_INT) {
644 /*
645 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
646 */
647 drm_handle_vblank(dc->base.dev, dc->pipe);
648 }
649
650 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
651 /*
652 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
653 */
654 }
655
656 return IRQ_HANDLED;
657}
658
659static int tegra_dc_show_regs(struct seq_file *s, void *data)
660{
661 struct drm_info_node *node = s->private;
662 struct tegra_dc *dc = node->info_ent->data;
663
664#define DUMP_REG(name) \
665 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
666 tegra_dc_readl(dc, name))
667
668 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
669 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
670 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
671 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
672 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
673 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
674 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
675 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
676 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
677 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
678 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
679 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
680 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
681 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
682 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
683 DUMP_REG(DC_CMD_SIGNAL_RAISE);
684 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
685 DUMP_REG(DC_CMD_INT_STATUS);
686 DUMP_REG(DC_CMD_INT_MASK);
687 DUMP_REG(DC_CMD_INT_ENABLE);
688 DUMP_REG(DC_CMD_INT_TYPE);
689 DUMP_REG(DC_CMD_INT_POLARITY);
690 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
691 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
692 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
693 DUMP_REG(DC_CMD_STATE_ACCESS);
694 DUMP_REG(DC_CMD_STATE_CONTROL);
695 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
696 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
697 DUMP_REG(DC_COM_CRC_CONTROL);
698 DUMP_REG(DC_COM_CRC_CHECKSUM);
699 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
700 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
701 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
702 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
703 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
704 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
705 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
706 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
707 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
708 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
709 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
710 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
711 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
712 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
713 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
714 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
715 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
716 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
717 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
718 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
719 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
720 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
721 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
722 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
723 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
724 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
725 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
726 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
727 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
728 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
729 DUMP_REG(DC_COM_SPI_CONTROL);
730 DUMP_REG(DC_COM_SPI_START_BYTE);
731 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
732 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
733 DUMP_REG(DC_COM_HSPI_CS_DC);
734 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
735 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
736 DUMP_REG(DC_COM_GPIO_CTRL);
737 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
738 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
739 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
740 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
741 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
742 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
743 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
744 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
745 DUMP_REG(DC_DISP_REF_TO_SYNC);
746 DUMP_REG(DC_DISP_SYNC_WIDTH);
747 DUMP_REG(DC_DISP_BACK_PORCH);
748 DUMP_REG(DC_DISP_ACTIVE);
749 DUMP_REG(DC_DISP_FRONT_PORCH);
750 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
751 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
752 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
753 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
754 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
755 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
756 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
757 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
758 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
759 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
760 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
761 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
762 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
763 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
764 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
765 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
766 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
767 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
768 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
769 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
770 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
771 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
772 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
773 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
774 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
775 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
776 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
777 DUMP_REG(DC_DISP_M0_CONTROL);
778 DUMP_REG(DC_DISP_M1_CONTROL);
779 DUMP_REG(DC_DISP_DI_CONTROL);
780 DUMP_REG(DC_DISP_PP_CONTROL);
781 DUMP_REG(DC_DISP_PP_SELECT_A);
782 DUMP_REG(DC_DISP_PP_SELECT_B);
783 DUMP_REG(DC_DISP_PP_SELECT_C);
784 DUMP_REG(DC_DISP_PP_SELECT_D);
785 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
786 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
787 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
788 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
789 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
790 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
791 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
792 DUMP_REG(DC_DISP_BORDER_COLOR);
793 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
794 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
795 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
796 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
797 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
798 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
799 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
800 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
801 DUMP_REG(DC_DISP_CURSOR_POSITION);
802 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
803 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
804 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
805 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
806 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
807 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
808 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
809 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
810 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
811 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
812 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
813 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
814 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
815 DUMP_REG(DC_DISP_SD_CONTROL);
816 DUMP_REG(DC_DISP_SD_CSC_COEFF);
817 DUMP_REG(DC_DISP_SD_LUT(0));
818 DUMP_REG(DC_DISP_SD_LUT(1));
819 DUMP_REG(DC_DISP_SD_LUT(2));
820 DUMP_REG(DC_DISP_SD_LUT(3));
821 DUMP_REG(DC_DISP_SD_LUT(4));
822 DUMP_REG(DC_DISP_SD_LUT(5));
823 DUMP_REG(DC_DISP_SD_LUT(6));
824 DUMP_REG(DC_DISP_SD_LUT(7));
825 DUMP_REG(DC_DISP_SD_LUT(8));
826 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
827 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
828 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
829 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
830 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
831 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
832 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
833 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
834 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
835 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
836 DUMP_REG(DC_DISP_SD_BL_TF(0));
837 DUMP_REG(DC_DISP_SD_BL_TF(1));
838 DUMP_REG(DC_DISP_SD_BL_TF(2));
839 DUMP_REG(DC_DISP_SD_BL_TF(3));
840 DUMP_REG(DC_DISP_SD_BL_CONTROL);
841 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
842 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
843 DUMP_REG(DC_WIN_WIN_OPTIONS);
844 DUMP_REG(DC_WIN_BYTE_SWAP);
845 DUMP_REG(DC_WIN_BUFFER_CONTROL);
846 DUMP_REG(DC_WIN_COLOR_DEPTH);
847 DUMP_REG(DC_WIN_POSITION);
848 DUMP_REG(DC_WIN_SIZE);
849 DUMP_REG(DC_WIN_PRESCALED_SIZE);
850 DUMP_REG(DC_WIN_H_INITIAL_DDA);
851 DUMP_REG(DC_WIN_V_INITIAL_DDA);
852 DUMP_REG(DC_WIN_DDA_INC);
853 DUMP_REG(DC_WIN_LINE_STRIDE);
854 DUMP_REG(DC_WIN_BUF_STRIDE);
855 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
856 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
857 DUMP_REG(DC_WIN_DV_CONTROL);
858 DUMP_REG(DC_WIN_BLEND_NOKEY);
859 DUMP_REG(DC_WIN_BLEND_1WIN);
860 DUMP_REG(DC_WIN_BLEND_2WIN_X);
861 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 862 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 863 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
864 DUMP_REG(DC_WINBUF_START_ADDR);
865 DUMP_REG(DC_WINBUF_START_ADDR_NS);
866 DUMP_REG(DC_WINBUF_START_ADDR_U);
867 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
868 DUMP_REG(DC_WINBUF_START_ADDR_V);
869 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
870 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
871 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
872 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
873 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
874 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
875 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
876 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
877 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
878
879#undef DUMP_REG
880
881 return 0;
882}
883
884static struct drm_info_list debugfs_files[] = {
885 { "regs", tegra_dc_show_regs, 0, NULL },
886};
887
888static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
889{
890 unsigned int i;
891 char *name;
892 int err;
893
894 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
895 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
896 kfree(name);
897
898 if (!dc->debugfs)
899 return -ENOMEM;
900
901 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
902 GFP_KERNEL);
903 if (!dc->debugfs_files) {
904 err = -ENOMEM;
905 goto remove;
906 }
907
908 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
909 dc->debugfs_files[i].data = dc;
910
911 err = drm_debugfs_create_files(dc->debugfs_files,
912 ARRAY_SIZE(debugfs_files),
913 dc->debugfs, minor);
914 if (err < 0)
915 goto free;
916
917 dc->minor = minor;
918
919 return 0;
920
921free:
922 kfree(dc->debugfs_files);
923 dc->debugfs_files = NULL;
924remove:
925 debugfs_remove(dc->debugfs);
926 dc->debugfs = NULL;
927
928 return err;
929}
930
931static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
932{
933 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
934 dc->minor);
935 dc->minor = NULL;
936
937 kfree(dc->debugfs_files);
938 dc->debugfs_files = NULL;
939
940 debugfs_remove(dc->debugfs);
941 dc->debugfs = NULL;
942
943 return 0;
944}
945
946static int tegra_dc_drm_init(struct host1x_client *client,
947 struct drm_device *drm)
948{
949 struct tegra_dc *dc = host1x_client_to_dc(client);
950 int err;
951
952 dc->pipe = drm->mode_config.num_crtc;
953
954 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
955 drm_mode_crtc_set_gamma_size(&dc->base, 256);
956 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
957
958 err = tegra_dc_rgb_init(drm, dc);
959 if (err < 0 && err != -ENODEV) {
960 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
961 return err;
962 }
963
f34bc787
TR		 964 err = tegra_dc_add_planes(drm, dc);
965 if (err < 0)
966 return err;
967
d8f4a9ed
TR		 968 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
969 err = tegra_dc_debugfs_init(dc, drm->primary);
970 if (err < 0)
971 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
972 }
973
974 err = devm_request_irq(dc->dev, dc->irq, tegra_drm_irq, 0,
975 dev_name(dc->dev), dc);
976 if (err < 0) {
977 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
978 err);
979 return err;
980 }
981
982 return 0;
983}
984
985static int tegra_dc_drm_exit(struct host1x_client *client)
986{
987 struct tegra_dc *dc = host1x_client_to_dc(client);
988 int err;
989
990 devm_free_irq(dc->dev, dc->irq, dc);
991
992 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
993 err = tegra_dc_debugfs_exit(dc);
994 if (err < 0)
995 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
996 }
997
998 err = tegra_dc_rgb_exit(dc);
999 if (err) {
1000 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1001 return err;
1002 }
1003
1004 return 0;
1005}
1006
1007static const struct host1x_client_ops dc_client_ops = {
1008 .drm_init = tegra_dc_drm_init,
1009 .drm_exit = tegra_dc_drm_exit,
1010};
1011
1012static int tegra_dc_probe(struct platform_device *pdev)
1013{
1014 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1015 struct resource *regs;
1016 struct tegra_dc *dc;
1017 int err;
1018
1019 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1020 if (!dc)
1021 return -ENOMEM;
1022
1023 INIT_LIST_HEAD(&dc->list);
1024 dc->dev = &pdev->dev;
1025
1026 dc->clk = devm_clk_get(&pdev->dev, NULL);
1027 if (IS_ERR(dc->clk)) {
1028 dev_err(&pdev->dev, "failed to get clock\n");
1029 return PTR_ERR(dc->clk);
1030 }
1031
1032 err = clk_prepare_enable(dc->clk);
1033 if (err < 0)
1034 return err;
1035
1036 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1037 if (!regs) {
1038 dev_err(&pdev->dev, "failed to get registers\n");
1039 return -ENXIO;
1040 }
1041
1042 dc->regs = devm_request_and_ioremap(&pdev->dev, regs);
1043 if (!dc->regs) {
1044 dev_err(&pdev->dev, "failed to remap registers\n");
1045 return -ENXIO;
1046 }
1047
1048 dc->irq = platform_get_irq(pdev, 0);
1049 if (dc->irq < 0) {
1050 dev_err(&pdev->dev, "failed to get IRQ\n");
1051 return -ENXIO;
1052 }
1053
1054 INIT_LIST_HEAD(&dc->client.list);
1055 dc->client.ops = &dc_client_ops;
1056 dc->client.dev = &pdev->dev;
1057
1058 err = tegra_dc_rgb_probe(dc);
1059 if (err < 0 && err != -ENODEV) {
1060 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1061 return err;
1062 }
1063
1064 err = host1x_register_client(host1x, &dc->client);
1065 if (err < 0) {
1066 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1067 err);
1068 return err;
1069 }
1070
1071 platform_set_drvdata(pdev, dc);
1072
1073 return 0;
1074}
1075
1076static int tegra_dc_remove(struct platform_device *pdev)
1077{
1078 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1079 struct tegra_dc *dc = platform_get_drvdata(pdev);
1080 int err;
1081
1082 err = host1x_unregister_client(host1x, &dc->client);
1083 if (err < 0) {
1084 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1085 err);
1086 return err;
1087 }
1088
1089 clk_disable_unprepare(dc->clk);
1090
1091 return 0;
1092}
1093
1094static struct of_device_id tegra_dc_of_match[] = {
219e8153 1095 { .compatible = "nvidia,tegra30-dc", },
d8f4a9ed
TR		 1096 { .compatible = "nvidia,tegra20-dc", },
1097 { },
1098};
1099
1100struct platform_driver tegra_dc_driver = {
1101 .driver = {
1102 .name = "tegra-dc",
1103 .owner = THIS_MODULE,
1104 .of_match_table = tegra_dc_of_match,
1105 },
1106 .probe = tegra_dc_probe,
1107 .remove = tegra_dc_remove,
1108};
Linux kernel - Deliverables
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