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drm/tegra: Stop CRTC at CRTC disable time
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
ca48080a 13#include <linux/reset.h>
d8f4a9ed 14
9c012700
TR		 15#include <soc/tegra/pmc.h>
16
de2ba664
AM		 17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
d8f4a9ed 20
3cb9ae4f
DV		 21#include <drm/drm_plane_helper.h>
22
8620fc62 23struct tegra_dc_soc_info {
42d0659b 24 bool supports_border_color;
8620fc62 25 bool supports_interlacing;
e687651b 26 bool supports_cursor;
c134f019 27 bool supports_block_linear;
d1f3e1e0 28 unsigned int pitch_align;
9c012700 29 bool has_powergate;
8620fc62
TR		 30};
31
f34bc787
TR		 32struct tegra_plane {
33 struct drm_plane base;
34 unsigned int index;
d8f4a9ed
TR		 35};
36
f34bc787
TR		 37static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
38{
39 return container_of(plane, struct tegra_plane, base);
40}
41
205d48ed
TR		 42static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index)
43{
44 u32 value = WIN_A_ACT_REQ << index;
45
46 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
47 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
48}
49
50static void tegra_dc_cursor_commit(struct tegra_dc *dc)
51{
52 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
53 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
54}
55
d700ba7a
TR		 56/*
57 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
58 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
59 * Latching happens mmediately if the display controller is in STOP mode or
60 * on the next frame boundary otherwise.
61 *
62 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
63 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
64 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
65 * into the ACTIVE copy, either immediately if the display controller is in
66 * STOP mode, or at the next frame boundary otherwise.
67 */
62b9e063 68void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 69{
70 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
71 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
72}
73
10288eea
TR		 74static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
75{
76 /* assume no swapping of fetched data */
77 if (swap)
78 *swap = BYTE_SWAP_NOSWAP;
79
80 switch (format) {
81 case DRM_FORMAT_XBGR8888:
82 return WIN_COLOR_DEPTH_R8G8B8A8;
83
84 case DRM_FORMAT_XRGB8888:
85 return WIN_COLOR_DEPTH_B8G8R8A8;
86
87 case DRM_FORMAT_RGB565:
88 return WIN_COLOR_DEPTH_B5G6R5;
89
90 case DRM_FORMAT_UYVY:
91 return WIN_COLOR_DEPTH_YCbCr422;
92
93 case DRM_FORMAT_YUYV:
94 if (swap)
95 *swap = BYTE_SWAP_SWAP2;
96
97 return WIN_COLOR_DEPTH_YCbCr422;
98
99 case DRM_FORMAT_YUV420:
100 return WIN_COLOR_DEPTH_YCbCr420P;
101
102 case DRM_FORMAT_YUV422:
103 return WIN_COLOR_DEPTH_YCbCr422P;
104
105 default:
106 break;
107 }
108
109 WARN(1, "unsupported pixel format %u, using default\n", format);
110 return WIN_COLOR_DEPTH_B8G8R8A8;
111}
112
113static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
114{
115 switch (format) {
116 case WIN_COLOR_DEPTH_YCbCr422:
117 case WIN_COLOR_DEPTH_YUV422:
118 if (planar)
119 *planar = false;
120
121 return true;
122
123 case WIN_COLOR_DEPTH_YCbCr420P:
124 case WIN_COLOR_DEPTH_YUV420P:
125 case WIN_COLOR_DEPTH_YCbCr422P:
126 case WIN_COLOR_DEPTH_YUV422P:
127 case WIN_COLOR_DEPTH_YCbCr422R:
128 case WIN_COLOR_DEPTH_YUV422R:
129 case WIN_COLOR_DEPTH_YCbCr422RA:
130 case WIN_COLOR_DEPTH_YUV422RA:
131 if (planar)
132 *planar = true;
133
134 return true;
135 }
136
fb35c6b6
TR		 137 if (planar)
138 *planar = false;
139
10288eea
TR		 140 return false;
141}
142
143static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
144 unsigned int bpp)
145{
146 fixed20_12 outf = dfixed_init(out);
147 fixed20_12 inf = dfixed_init(in);
148 u32 dda_inc;
149 int max;
150
151 if (v)
152 max = 15;
153 else {
154 switch (bpp) {
155 case 2:
156 max = 8;
157 break;
158
159 default:
160 WARN_ON_ONCE(1);
161 /* fallthrough */
162 case 4:
163 max = 4;
164 break;
165 }
166 }
167
168 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
169 inf.full -= dfixed_const(1);
170
171 dda_inc = dfixed_div(inf, outf);
172 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
173
174 return dda_inc;
175}
176
177static inline u32 compute_initial_dda(unsigned int in)
178{
179 fixed20_12 inf = dfixed_init(in);
180 return dfixed_frac(inf);
181}
182
183static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
184 const struct tegra_dc_window *window)
185{
186 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 187 unsigned long value, flags;
10288eea
TR		 188 bool yuv, planar;
189
190 /*
191 * For YUV planar modes, the number of bytes per pixel takes into
192 * account only the luma component and therefore is 1.
193 */
194 yuv = tegra_dc_format_is_yuv(window->format, &planar);
195 if (!yuv)
196 bpp = window->bits_per_pixel / 8;
197 else
198 bpp = planar ? 1 : 2;
199
93396d0f
SP		 200 spin_lock_irqsave(&dc->lock, flags);
201
10288eea
TR		 202 value = WINDOW_A_SELECT << index;
203 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
204
205 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
206 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
207
208 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
209 tegra_dc_writel(dc, value, DC_WIN_POSITION);
210
211 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
212 tegra_dc_writel(dc, value, DC_WIN_SIZE);
213
214 h_offset = window->src.x * bpp;
215 v_offset = window->src.y;
216 h_size = window->src.w * bpp;
217 v_size = window->src.h;
218
219 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
220 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
221
222 /*
223 * For DDA computations the number of bytes per pixel for YUV planar
224 * modes needs to take into account all Y, U and V components.
225 */
226 if (yuv && planar)
227 bpp = 2;
228
229 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
230 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
231
232 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
233 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
234
235 h_dda = compute_initial_dda(window->src.x);
236 v_dda = compute_initial_dda(window->src.y);
237
238 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
239 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
240
241 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
242 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
243
244 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
245
246 if (yuv && planar) {
247 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
248 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
249 value = window->stride[1] << 16 | window->stride[0];
250 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
251 } else {
252 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
253 }
254
255 if (window->bottom_up)
256 v_offset += window->src.h - 1;
257
258 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
259 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
260
c134f019
TR		 261 if (dc->soc->supports_block_linear) {
262 unsigned long height = window->tiling.value;
263
264 switch (window->tiling.mode) {
265 case TEGRA_BO_TILING_MODE_PITCH:
266 value = DC_WINBUF_SURFACE_KIND_PITCH;
267 break;
268
269 case TEGRA_BO_TILING_MODE_TILED:
270 value = DC_WINBUF_SURFACE_KIND_TILED;
271 break;
272
273 case TEGRA_BO_TILING_MODE_BLOCK:
274 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
275 DC_WINBUF_SURFACE_KIND_BLOCK;
276 break;
277 }
278
279 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 280 } else {
c134f019
TR		 281 switch (window->tiling.mode) {
282 case TEGRA_BO_TILING_MODE_PITCH:
283 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
284 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
285 break;
10288eea 286
c134f019
TR		 287 case TEGRA_BO_TILING_MODE_TILED:
288 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
289 DC_WIN_BUFFER_ADDR_MODE_TILE;
290 break;
291
292 case TEGRA_BO_TILING_MODE_BLOCK:
293 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 294 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 295 return -EINVAL;
296 }
297
298 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
299 }
10288eea
TR		 300
301 value = WIN_ENABLE;
302
303 if (yuv) {
304 /* setup default colorspace conversion coefficients */
305 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
306 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
307 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
308 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
309 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
310 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
311 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
312 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
313
314 value |= CSC_ENABLE;
315 } else if (window->bits_per_pixel < 24) {
316 value |= COLOR_EXPAND;
317 }
318
319 if (window->bottom_up)
320 value |= V_DIRECTION;
321
322 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
323
324 /*
325 * Disable blending and assume Window A is the bottom-most window,
326 * Window C is the top-most window and Window B is in the middle.
327 */
328 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
329 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
330
331 switch (index) {
332 case 0:
333 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
334 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
335 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
336 break;
337
338 case 1:
339 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
340 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
341 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
342 break;
343
344 case 2:
345 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
346 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
347 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
348 break;
349 }
350
205d48ed 351 tegra_dc_window_commit(dc, index);
10288eea 352
93396d0f
SP		 353 spin_unlock_irqrestore(&dc->lock, flags);
354
10288eea
TR		 355 return 0;
356}
357
c7679306
TR		 358static int tegra_window_plane_disable(struct drm_plane *plane)
359{
360 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
361 struct tegra_plane *p = to_tegra_plane(plane);
93396d0f 362 unsigned long flags;
c7679306
TR		 363 u32 value;
364
365 if (!plane->crtc)
366 return 0;
367
93396d0f
SP		 368 spin_lock_irqsave(&dc->lock, flags);
369
c7679306
TR		 370 value = WINDOW_A_SELECT << p->index;
371 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
372
373 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
374 value &= ~WIN_ENABLE;
375 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
376
377 tegra_dc_window_commit(dc, p->index);
378
93396d0f
SP		 379 spin_unlock_irqrestore(&dc->lock, flags);
380
c7679306
TR		 381 return 0;
382}
383
384static void tegra_plane_destroy(struct drm_plane *plane)
385{
386 struct tegra_plane *p = to_tegra_plane(plane);
387
388 drm_plane_cleanup(plane);
389 kfree(p);
390}
391
392static const u32 tegra_primary_plane_formats[] = {
393 DRM_FORMAT_XBGR8888,
394 DRM_FORMAT_XRGB8888,
395 DRM_FORMAT_RGB565,
396};
397
398static int tegra_primary_plane_update(struct drm_plane *plane,
399 struct drm_crtc *crtc,
400 struct drm_framebuffer *fb, int crtc_x,
401 int crtc_y, unsigned int crtc_w,
402 unsigned int crtc_h, uint32_t src_x,
403 uint32_t src_y, uint32_t src_w,
404 uint32_t src_h)
405{
406 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
407 struct tegra_plane *p = to_tegra_plane(plane);
408 struct tegra_dc *dc = to_tegra_dc(crtc);
409 struct tegra_dc_window window;
410 int err;
411
412 memset(&window, 0, sizeof(window));
413 window.src.x = src_x >> 16;
414 window.src.y = src_y >> 16;
415 window.src.w = src_w >> 16;
416 window.src.h = src_h >> 16;
417 window.dst.x = crtc_x;
418 window.dst.y = crtc_y;
419 window.dst.w = crtc_w;
420 window.dst.h = crtc_h;
421 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
422 window.bits_per_pixel = fb->bits_per_pixel;
423 window.bottom_up = tegra_fb_is_bottom_up(fb);
424
425 err = tegra_fb_get_tiling(fb, &window.tiling);
426 if (err < 0)
427 return err;
428
429 window.base[0] = bo->paddr + fb->offsets[0];
430 window.stride[0] = fb->pitches[0];
431
432 err = tegra_dc_setup_window(dc, p->index, &window);
433 if (err < 0)
434 return err;
10288eea
TR		 435
436 return 0;
437}
438
c7679306
TR		 439static void tegra_primary_plane_destroy(struct drm_plane *plane)
440{
441 tegra_window_plane_disable(plane);
442 tegra_plane_destroy(plane);
443}
444
445static const struct drm_plane_funcs tegra_primary_plane_funcs = {
446 .update_plane = tegra_primary_plane_update,
447 .disable_plane = tegra_window_plane_disable,
448 .destroy = tegra_primary_plane_destroy,
449};
450
451static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
452 struct tegra_dc *dc)
453{
518e6227
TR		 454 /*
455 * Ideally this would use drm_crtc_mask(), but that would require the
456 * CRTC to already be in the mode_config's list of CRTCs. However, it
457 * will only be added to that list in the drm_crtc_init_with_planes()
458 * (in tegra_dc_init()), which in turn requires registration of these
459 * planes. So we have ourselves a nice little chicken and egg problem
460 * here.
461 *
462 * We work around this by manually creating the mask from the number
463 * of CRTCs that have been registered, and should therefore always be
464 * the same as drm_crtc_index() after registration.
465 */
466 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 467 struct tegra_plane *plane;
468 unsigned int num_formats;
469 const u32 *formats;
470 int err;
471
472 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
473 if (!plane)
474 return ERR_PTR(-ENOMEM);
475
476 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
477 formats = tegra_primary_plane_formats;
478
518e6227 479 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306
TR		 480 &tegra_primary_plane_funcs, formats,
481 num_formats, DRM_PLANE_TYPE_PRIMARY);
482 if (err < 0) {
483 kfree(plane);
484 return ERR_PTR(err);
485 }
486
487 return &plane->base;
488}
489
490static const u32 tegra_cursor_plane_formats[] = {
491 DRM_FORMAT_RGBA8888,
492};
493
494static int tegra_cursor_plane_update(struct drm_plane *plane,
495 struct drm_crtc *crtc,
496 struct drm_framebuffer *fb, int crtc_x,
497 int crtc_y, unsigned int crtc_w,
498 unsigned int crtc_h, uint32_t src_x,
499 uint32_t src_y, uint32_t src_w,
500 uint32_t src_h)
501{
502 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
503 struct tegra_dc *dc = to_tegra_dc(crtc);
504 u32 value = CURSOR_CLIP_DISPLAY;
505
506 /* scaling not supported for cursor */
507 if ((src_w >> 16 != crtc_w) || (src_h >> 16 != crtc_h))
508 return -EINVAL;
509
510 /* only square cursors supported */
511 if (src_w != src_h)
512 return -EINVAL;
513
514 switch (crtc_w) {
515 case 32:
516 value |= CURSOR_SIZE_32x32;
517 break;
518
519 case 64:
520 value |= CURSOR_SIZE_64x64;
521 break;
522
523 case 128:
524 value |= CURSOR_SIZE_128x128;
525 break;
526
527 case 256:
528 value |= CURSOR_SIZE_256x256;
529 break;
530
531 default:
532 return -EINVAL;
533 }
534
535 value |= (bo->paddr >> 10) & 0x3fffff;
536 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
537
538#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
539 value = (bo->paddr >> 32) & 0x3;
540 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
541#endif
542
543 /* enable cursor and set blend mode */
544 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
545 value |= CURSOR_ENABLE;
546 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
547
548 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
549 value &= ~CURSOR_DST_BLEND_MASK;
550 value &= ~CURSOR_SRC_BLEND_MASK;
551 value |= CURSOR_MODE_NORMAL;
552 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
553 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
554 value |= CURSOR_ALPHA;
555 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
556
557 /* position the cursor */
558 value = (crtc_y & 0x3fff) << 16 | (crtc_x & 0x3fff);
559 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
560
561 /* apply changes */
562 tegra_dc_cursor_commit(dc);
563 tegra_dc_commit(dc);
564
565 return 0;
566}
567
568static int tegra_cursor_plane_disable(struct drm_plane *plane)
569{
570 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
571 u32 value;
572
573 if (!plane->crtc)
574 return 0;
575
576 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
577 value &= ~CURSOR_ENABLE;
578 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
579
580 tegra_dc_cursor_commit(dc);
581 tegra_dc_commit(dc);
582
583 return 0;
584}
585
586static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
587 .update_plane = tegra_cursor_plane_update,
588 .disable_plane = tegra_cursor_plane_disable,
589 .destroy = tegra_plane_destroy,
590};
591
592static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
593 struct tegra_dc *dc)
594{
595 struct tegra_plane *plane;
596 unsigned int num_formats;
597 const u32 *formats;
598 int err;
599
600 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
601 if (!plane)
602 return ERR_PTR(-ENOMEM);
603
604 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
605 formats = tegra_cursor_plane_formats;
606
607 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
608 &tegra_cursor_plane_funcs, formats,
609 num_formats, DRM_PLANE_TYPE_CURSOR);
610 if (err < 0) {
611 kfree(plane);
612 return ERR_PTR(err);
613 }
614
615 return &plane->base;
616}
617
618static int tegra_overlay_plane_update(struct drm_plane *plane,
619 struct drm_crtc *crtc,
620 struct drm_framebuffer *fb, int crtc_x,
621 int crtc_y, unsigned int crtc_w,
622 unsigned int crtc_h, uint32_t src_x,
623 uint32_t src_y, uint32_t src_w,
624 uint32_t src_h)
f34bc787
TR		 625{
626 struct tegra_plane *p = to_tegra_plane(plane);
627 struct tegra_dc *dc = to_tegra_dc(crtc);
628 struct tegra_dc_window window;
629 unsigned int i;
c134f019 630 int err;
f34bc787
TR		 631
632 memset(&window, 0, sizeof(window));
633 window.src.x = src_x >> 16;
634 window.src.y = src_y >> 16;
635 window.src.w = src_w >> 16;
636 window.src.h = src_h >> 16;
637 window.dst.x = crtc_x;
638 window.dst.y = crtc_y;
639 window.dst.w = crtc_w;
640 window.dst.h = crtc_h;
f925390e 641 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
f34bc787 642 window.bits_per_pixel = fb->bits_per_pixel;
db7fbdfd 643 window.bottom_up = tegra_fb_is_bottom_up(fb);
c134f019
TR		 644
645 err = tegra_fb_get_tiling(fb, &window.tiling);
646 if (err < 0)
647 return err;
f34bc787
TR		 648
649 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 650 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 651
de2ba664 652 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 653
654 /*
655 * Tegra doesn't support different strides for U and V planes
656 * so we display a warning if the user tries to display a
657 * framebuffer with such a configuration.
658 */
659 if (i >= 2) {
660 if (fb->pitches[i] != window.stride[1])
661 DRM_ERROR("unsupported UV-plane configuration\n");
662 } else {
663 window.stride[i] = fb->pitches[i];
664 }
665 }
666
667 return tegra_dc_setup_window(dc, p->index, &window);
668}
669
c7679306 670static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 671{
c7679306
TR		 672 tegra_window_plane_disable(plane);
673 tegra_plane_destroy(plane);
f34bc787
TR		 674}
675
c7679306
TR		 676static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
677 .update_plane = tegra_overlay_plane_update,
678 .disable_plane = tegra_window_plane_disable,
679 .destroy = tegra_overlay_plane_destroy,
f34bc787
TR		 680};
681
c7679306 682static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 683 DRM_FORMAT_XBGR8888,
f34bc787 684 DRM_FORMAT_XRGB8888,
dbe4d9a7 685 DRM_FORMAT_RGB565,
f34bc787 686 DRM_FORMAT_UYVY,
f925390e 687 DRM_FORMAT_YUYV,
f34bc787
TR		 688 DRM_FORMAT_YUV420,
689 DRM_FORMAT_YUV422,
690};
691
c7679306
TR		 692static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
693 struct tegra_dc *dc,
694 unsigned int index)
f34bc787 695{
c7679306
TR		 696 struct tegra_plane *plane;
697 unsigned int num_formats;
698 const u32 *formats;
699 int err;
f34bc787 700
c7679306
TR		 701 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
702 if (!plane)
703 return ERR_PTR(-ENOMEM);
f34bc787 704
c7679306 705 plane->index = index;
f34bc787 706
c7679306
TR		 707 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
708 formats = tegra_overlay_plane_formats;
f34bc787 709
c7679306
TR		 710 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
711 &tegra_overlay_plane_funcs, formats,
712 num_formats, DRM_PLANE_TYPE_OVERLAY);
713 if (err < 0) {
714 kfree(plane);
715 return ERR_PTR(err);
716 }
717
718 return &plane->base;
719}
720
721static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
722{
723 struct drm_plane *plane;
724 unsigned int i;
725
726 for (i = 0; i < 2; i++) {
727 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
728 if (IS_ERR(plane))
729 return PTR_ERR(plane);
f34bc787
TR		 730 }
731
732 return 0;
733}
734
23fb4740
TR		 735static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
736 struct drm_framebuffer *fb)
737{
de2ba664 738 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
db7fbdfd 739 unsigned int h_offset = 0, v_offset = 0;
c134f019 740 struct tegra_bo_tiling tiling;
93396d0f 741 unsigned long value, flags;
f925390e 742 unsigned int format, swap;
c134f019
TR		 743 int err;
744
745 err = tegra_fb_get_tiling(fb, &tiling);
746 if (err < 0)
747 return err;
23fb4740 748
93396d0f
SP		 749 spin_lock_irqsave(&dc->lock, flags);
750
23fb4740
TR		 751 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
752
753 value = fb->offsets[0] + y * fb->pitches[0] +
754 x * fb->bits_per_pixel / 8;
755
de2ba664 756 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 757 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
f925390e
TR		 758
759 format = tegra_dc_format(fb->pixel_format, &swap);
ed683aea 760 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
f925390e 761 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
23fb4740 762
c134f019
TR		 763 if (dc->soc->supports_block_linear) {
764 unsigned long height = tiling.value;
765
766 switch (tiling.mode) {
767 case TEGRA_BO_TILING_MODE_PITCH:
768 value = DC_WINBUF_SURFACE_KIND_PITCH;
769 break;
770
771 case TEGRA_BO_TILING_MODE_TILED:
772 value = DC_WINBUF_SURFACE_KIND_TILED;
773 break;
774
775 case TEGRA_BO_TILING_MODE_BLOCK:
776 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
777 DC_WINBUF_SURFACE_KIND_BLOCK;
778 break;
779 }
780
781 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
773af77f 782 } else {
c134f019
TR		 783 switch (tiling.mode) {
784 case TEGRA_BO_TILING_MODE_PITCH:
785 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
786 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
787 break;
773af77f 788
c134f019
TR		 789 case TEGRA_BO_TILING_MODE_TILED:
790 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
791 DC_WIN_BUFFER_ADDR_MODE_TILE;
792 break;
793
794 case TEGRA_BO_TILING_MODE_BLOCK:
795 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 796 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 797 return -EINVAL;
798 }
799
800 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
801 }
773af77f 802
db7fbdfd
TR		 803 /* make sure bottom-up buffers are properly displayed */
804 if (tegra_fb_is_bottom_up(fb)) {
805 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 806 value |= V_DIRECTION;
db7fbdfd
TR		 807 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
808
809 v_offset += fb->height - 1;
810 } else {
811 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 812 value &= ~V_DIRECTION;
db7fbdfd
TR		 813 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
814 }
815
816 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
817 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
818
23fb4740 819 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
205d48ed 820 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
23fb4740
TR		 821 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
822
93396d0f
SP		 823 spin_unlock_irqrestore(&dc->lock, flags);
824
23fb4740
TR		 825 return 0;
826}
827
6e5ff998
TR		 828void tegra_dc_enable_vblank(struct tegra_dc *dc)
829{
830 unsigned long value, flags;
831
832 spin_lock_irqsave(&dc->lock, flags);
833
834 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
835 value |= VBLANK_INT;
836 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
837
838 spin_unlock_irqrestore(&dc->lock, flags);
839}
840
841void tegra_dc_disable_vblank(struct tegra_dc *dc)
842{
843 unsigned long value, flags;
844
845 spin_lock_irqsave(&dc->lock, flags);
846
847 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
848 value &= ~VBLANK_INT;
849 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
850
851 spin_unlock_irqrestore(&dc->lock, flags);
852}
853
3c03c46a
TR		 854static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
855{
856 struct drm_device *drm = dc->base.dev;
857 struct drm_crtc *crtc = &dc->base;
3c03c46a 858 unsigned long flags, base;
de2ba664 859 struct tegra_bo *bo;
3c03c46a 860
6b59cc1c
TR		 861 spin_lock_irqsave(&drm->event_lock, flags);
862
863 if (!dc->event) {
864 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 865 return;
6b59cc1c 866 }
3c03c46a 867
f4510a27 868 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 869
8643bc6d 870 spin_lock(&dc->lock);
93396d0f 871
3c03c46a 872 /* check if new start address has been latched */
93396d0f 873 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 874 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
875 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
876 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
877
8643bc6d 878 spin_unlock(&dc->lock);
93396d0f 879
f4510a27 880 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 881 drm_crtc_send_vblank_event(crtc, dc->event);
882 drm_crtc_vblank_put(crtc);
3c03c46a 883 dc->event = NULL;
3c03c46a 884 }
6b59cc1c
TR		 885
886 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 887}
888
889void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
890{
891 struct tegra_dc *dc = to_tegra_dc(crtc);
892 struct drm_device *drm = crtc->dev;
893 unsigned long flags;
894
895 spin_lock_irqsave(&drm->event_lock, flags);
896
897 if (dc->event && dc->event->base.file_priv == file) {
898 dc->event->base.destroy(&dc->event->base);
ed7dae58 899 drm_crtc_vblank_put(crtc);
3c03c46a
TR		 900 dc->event = NULL;
901 }
902
903 spin_unlock_irqrestore(&drm->event_lock, flags);
904}
905
906static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 907 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a 908{
ed7dae58 909 unsigned int pipe = drm_crtc_index(crtc);
3c03c46a 910 struct tegra_dc *dc = to_tegra_dc(crtc);
3c03c46a
TR		 911
912 if (dc->event)
913 return -EBUSY;
914
915 if (event) {
ed7dae58 916 event->pipe = pipe;
3c03c46a 917 dc->event = event;
ed7dae58 918 drm_crtc_vblank_get(crtc);
3c03c46a
TR		 919 }
920
921 tegra_dc_set_base(dc, 0, 0, fb);
f4510a27 922 crtc->primary->fb = fb;
3c03c46a
TR		 923
924 return 0;
925}
926
f002abc1
TR		 927static void tegra_dc_destroy(struct drm_crtc *crtc)
928{
929 drm_crtc_cleanup(crtc);
f002abc1
TR		 930}
931
d8f4a9ed 932static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 933 .page_flip = tegra_dc_page_flip,
d8f4a9ed 934 .set_config = drm_crtc_helper_set_config,
f002abc1 935 .destroy = tegra_dc_destroy,
d8f4a9ed
TR		 936};
937
f34bc787 938static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 939{
f002abc1 940 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787
TR		 941 struct drm_device *drm = crtc->dev;
942 struct drm_plane *plane;
36904adf 943 u32 value;
f34bc787 944
2b4c3661 945 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
f34bc787 946 if (plane->crtc == crtc) {
c7679306 947 tegra_window_plane_disable(plane);
f34bc787
TR		 948 plane->crtc = NULL;
949
950 if (plane->fb) {
951 drm_framebuffer_unreference(plane->fb);
952 plane->fb = NULL;
953 }
954 }
955 }
f002abc1 956
36904adf
TR		 957 /* stop the display controller */
958 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
959 value &= ~DISP_CTRL_MODE_MASK;
960 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
961
8ff64c17 962 drm_crtc_vblank_off(crtc);
c7679306 963 tegra_dc_commit(dc);
d8f4a9ed
TR		 964}
965
966static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
967 const struct drm_display_mode *mode,
968 struct drm_display_mode *adjusted)
969{
970 return true;
971}
972
d8f4a9ed
TR		 973static int tegra_dc_set_timings(struct tegra_dc *dc,
974 struct drm_display_mode *mode)
975{
0444c0ff
TR		 976 unsigned int h_ref_to_sync = 1;
977 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 978 unsigned long value;
979
980 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
981
982 value = (v_ref_to_sync << 16) | h_ref_to_sync;
983 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
984
985 value = ((mode->vsync_end - mode->vsync_start) << 16) |
986 ((mode->hsync_end - mode->hsync_start) << 0);
987 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
988
d8f4a9ed
TR		 989 value = ((mode->vtotal - mode->vsync_end) << 16) |
990 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 991 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
992
993 value = ((mode->vsync_start - mode->vdisplay) << 16) |
994 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 995 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
996
997 value = (mode->vdisplay << 16) | mode->hdisplay;
998 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
999
1000 return 0;
1001}
1002
1003static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
dbb3f2f7 1004 struct drm_display_mode *mode)
d8f4a9ed 1005{
91eded9b 1006 unsigned long pclk = mode->clock * 1000;
d8f4a9ed
TR		 1007 struct tegra_dc *dc = to_tegra_dc(crtc);
1008 struct tegra_output *output = NULL;
1009 struct drm_encoder *encoder;
dbb3f2f7
TR		 1010 unsigned int div;
1011 u32 value;
d8f4a9ed
TR		 1012 long err;
1013
1014 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
1015 if (encoder->crtc == crtc) {
1016 output = encoder_to_output(encoder);
1017 break;
1018 }
1019
1020 if (!output)
1021 return -ENODEV;
1022
1023 /*
91eded9b
TR		 1024 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
1025 * respectively, each of which divides the base pll_d by 2.
d8f4a9ed 1026 */
91eded9b 1027 err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
d8f4a9ed
TR		 1028 if (err < 0) {
1029 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
1030 return err;
1031 }
1032
91eded9b 1033 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
d8f4a9ed 1034
dbb3f2f7
TR		 1035 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
1036 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
d8f4a9ed
TR		 1037
1038 return 0;
1039}
1040
1041static int tegra_crtc_mode_set(struct drm_crtc *crtc,
1042 struct drm_display_mode *mode,
1043 struct drm_display_mode *adjusted,
1044 int x, int y, struct drm_framebuffer *old_fb)
1045{
f4510a27 1046 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
d8f4a9ed 1047 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 1048 struct tegra_dc_window window;
dbb3f2f7 1049 u32 value;
d8f4a9ed
TR		 1050 int err;
1051
dbb3f2f7 1052 err = tegra_crtc_setup_clk(crtc, mode);
d8f4a9ed
TR		 1053 if (err) {
1054 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
1055 return err;
1056 }
1057
1058 /* program display mode */
1059 tegra_dc_set_timings(dc, mode);
1060
42d0659b
TR		 1061 if (dc->soc->supports_border_color)
1062 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1063
8620fc62
TR		 1064 /* interlacing isn't supported yet, so disable it */
1065 if (dc->soc->supports_interlacing) {
1066 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1067 value &= ~INTERLACE_ENABLE;
1068 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1069 }
1070
d8f4a9ed 1071 /* setup window parameters */
f34bc787
TR		 1072 memset(&window, 0, sizeof(window));
1073 window.src.x = 0;
1074 window.src.y = 0;
1075 window.src.w = mode->hdisplay;
1076 window.src.h = mode->vdisplay;
1077 window.dst.x = 0;
1078 window.dst.y = 0;
1079 window.dst.w = mode->hdisplay;
1080 window.dst.h = mode->vdisplay;
f925390e
TR		 1081 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
1082 &window.swap);
f4510a27
MR		 1083 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
1084 window.stride[0] = crtc->primary->fb->pitches[0];
de2ba664 1085 window.base[0] = bo->paddr;
f34bc787
TR		 1086
1087 err = tegra_dc_setup_window(dc, 0, &window);
1088 if (err < 0)
1089 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 1090
d8f4a9ed
TR		 1091 return 0;
1092}
d8f4a9ed 1093
23fb4740
TR		 1094static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1095 struct drm_framebuffer *old_fb)
1096{
1097 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1098
f4510a27 1099 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
d8f4a9ed
TR		 1100}
1101
1102static void tegra_crtc_prepare(struct drm_crtc *crtc)
1103{
1104 struct tegra_dc *dc = to_tegra_dc(crtc);
1105 unsigned int syncpt;
1106 unsigned long value;
1107
8ff64c17
TR		 1108 drm_crtc_vblank_off(crtc);
1109
d8f4a9ed 1110 /* hardware initialization */
ca48080a 1111 reset_control_deassert(dc->rst);
d8f4a9ed
TR		 1112 usleep_range(10000, 20000);
1113
1114 if (dc->pipe)
1115 syncpt = SYNCPT_VBLANK1;
1116 else
1117 syncpt = SYNCPT_VBLANK0;
1118
1119 /* initialize display controller */
1120 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1121 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1122
1123 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1124 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1125
1126 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1127 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1128 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1129
d8f4a9ed
TR		 1130 /* initialize timer */
1131 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1132 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1133 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1134
1135 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1136 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1137 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1138
d8f4a9ed
TR		 1139 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1140 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 1141
1142 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1143 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 1144}
1145
1146static void tegra_crtc_commit(struct drm_crtc *crtc)
1147{
1148 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1149
8ff64c17 1150 drm_crtc_vblank_on(crtc);
205d48ed 1151 tegra_dc_commit(dc);
d8f4a9ed
TR		 1152}
1153
d8f4a9ed 1154static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1155 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 1156 .mode_fixup = tegra_crtc_mode_fixup,
1157 .mode_set = tegra_crtc_mode_set,
23fb4740 1158 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 1159 .prepare = tegra_crtc_prepare,
1160 .commit = tegra_crtc_commit,
d8f4a9ed
TR		 1161};
1162
6e5ff998 1163static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1164{
1165 struct tegra_dc *dc = data;
1166 unsigned long status;
1167
1168 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1169 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1170
1171 if (status & FRAME_END_INT) {
1172 /*
1173 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1174 */
1175 }
1176
1177 if (status & VBLANK_INT) {
1178 /*
1179 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1180 */
ed7dae58 1181 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1182 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 1183 }
1184
1185 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1186 /*
1187 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1188 */
1189 }
1190
1191 return IRQ_HANDLED;
1192}
1193
1194static int tegra_dc_show_regs(struct seq_file *s, void *data)
1195{
1196 struct drm_info_node *node = s->private;
1197 struct tegra_dc *dc = node->info_ent->data;
1198
1199#define DUMP_REG(name) \
03a60569 1200 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1201 tegra_dc_readl(dc, name))
1202
1203 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1204 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1205 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1206 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1207 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1208 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1209 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1210 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1211 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1212 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1213 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1214 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1215 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1216 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1217 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1218 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1219 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1220 DUMP_REG(DC_CMD_INT_STATUS);
1221 DUMP_REG(DC_CMD_INT_MASK);
1222 DUMP_REG(DC_CMD_INT_ENABLE);
1223 DUMP_REG(DC_CMD_INT_TYPE);
1224 DUMP_REG(DC_CMD_INT_POLARITY);
1225 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1226 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1227 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1228 DUMP_REG(DC_CMD_STATE_ACCESS);
1229 DUMP_REG(DC_CMD_STATE_CONTROL);
1230 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1231 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1232 DUMP_REG(DC_COM_CRC_CONTROL);
1233 DUMP_REG(DC_COM_CRC_CHECKSUM);
1234 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1235 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1236 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1237 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1238 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1239 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1240 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1241 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1242 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1243 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1244 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1245 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1246 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1247 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1248 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1249 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1250 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1251 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1252 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1253 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1254 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1255 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1256 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1257 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1258 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1259 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1260 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1261 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1262 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1263 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1264 DUMP_REG(DC_COM_SPI_CONTROL);
1265 DUMP_REG(DC_COM_SPI_START_BYTE);
1266 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1267 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1268 DUMP_REG(DC_COM_HSPI_CS_DC);
1269 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1270 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1271 DUMP_REG(DC_COM_GPIO_CTRL);
1272 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1273 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1274 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1275 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1276 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1277 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1278 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1279 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1280 DUMP_REG(DC_DISP_REF_TO_SYNC);
1281 DUMP_REG(DC_DISP_SYNC_WIDTH);
1282 DUMP_REG(DC_DISP_BACK_PORCH);
1283 DUMP_REG(DC_DISP_ACTIVE);
1284 DUMP_REG(DC_DISP_FRONT_PORCH);
1285 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1286 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1287 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1288 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1289 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1290 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1291 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1292 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1293 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1294 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1295 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1296 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1297 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1298 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1299 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1300 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1301 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1302 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1303 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1304 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1305 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1306 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1307 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1308 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1309 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1310 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1311 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1312 DUMP_REG(DC_DISP_M0_CONTROL);
1313 DUMP_REG(DC_DISP_M1_CONTROL);
1314 DUMP_REG(DC_DISP_DI_CONTROL);
1315 DUMP_REG(DC_DISP_PP_CONTROL);
1316 DUMP_REG(DC_DISP_PP_SELECT_A);
1317 DUMP_REG(DC_DISP_PP_SELECT_B);
1318 DUMP_REG(DC_DISP_PP_SELECT_C);
1319 DUMP_REG(DC_DISP_PP_SELECT_D);
1320 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1321 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1322 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1323 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1324 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1325 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1326 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1327 DUMP_REG(DC_DISP_BORDER_COLOR);
1328 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1329 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1330 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1331 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1332 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1333 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1334 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1335 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1336 DUMP_REG(DC_DISP_CURSOR_POSITION);
1337 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1338 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1339 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1340 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1341 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1342 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1343 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1344 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1345 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1346 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1347 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1348 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1349 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1350 DUMP_REG(DC_DISP_SD_CONTROL);
1351 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1352 DUMP_REG(DC_DISP_SD_LUT(0));
1353 DUMP_REG(DC_DISP_SD_LUT(1));
1354 DUMP_REG(DC_DISP_SD_LUT(2));
1355 DUMP_REG(DC_DISP_SD_LUT(3));
1356 DUMP_REG(DC_DISP_SD_LUT(4));
1357 DUMP_REG(DC_DISP_SD_LUT(5));
1358 DUMP_REG(DC_DISP_SD_LUT(6));
1359 DUMP_REG(DC_DISP_SD_LUT(7));
1360 DUMP_REG(DC_DISP_SD_LUT(8));
1361 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1362 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1363 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1364 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1365 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1366 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1367 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1368 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1369 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1370 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1371 DUMP_REG(DC_DISP_SD_BL_TF(0));
1372 DUMP_REG(DC_DISP_SD_BL_TF(1));
1373 DUMP_REG(DC_DISP_SD_BL_TF(2));
1374 DUMP_REG(DC_DISP_SD_BL_TF(3));
1375 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1376 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1377 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1378 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1379 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1380 DUMP_REG(DC_WIN_WIN_OPTIONS);
1381 DUMP_REG(DC_WIN_BYTE_SWAP);
1382 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1383 DUMP_REG(DC_WIN_COLOR_DEPTH);
1384 DUMP_REG(DC_WIN_POSITION);
1385 DUMP_REG(DC_WIN_SIZE);
1386 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1387 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1388 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1389 DUMP_REG(DC_WIN_DDA_INC);
1390 DUMP_REG(DC_WIN_LINE_STRIDE);
1391 DUMP_REG(DC_WIN_BUF_STRIDE);
1392 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1393 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1394 DUMP_REG(DC_WIN_DV_CONTROL);
1395 DUMP_REG(DC_WIN_BLEND_NOKEY);
1396 DUMP_REG(DC_WIN_BLEND_1WIN);
1397 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1398 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1399 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1400 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1401 DUMP_REG(DC_WINBUF_START_ADDR);
1402 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1403 DUMP_REG(DC_WINBUF_START_ADDR_U);
1404 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1405 DUMP_REG(DC_WINBUF_START_ADDR_V);
1406 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1407 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1408 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1409 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1410 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1411 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1412 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1413 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1414 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1415
1416#undef DUMP_REG
1417
1418 return 0;
1419}
1420
1421static struct drm_info_list debugfs_files[] = {
1422 { "regs", tegra_dc_show_regs, 0, NULL },
1423};
1424
1425static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1426{
1427 unsigned int i;
1428 char *name;
1429 int err;
1430
1431 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1432 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1433 kfree(name);
1434
1435 if (!dc->debugfs)
1436 return -ENOMEM;
1437
1438 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1439 GFP_KERNEL);
1440 if (!dc->debugfs_files) {
1441 err = -ENOMEM;
1442 goto remove;
1443 }
1444
1445 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1446 dc->debugfs_files[i].data = dc;
1447
1448 err = drm_debugfs_create_files(dc->debugfs_files,
1449 ARRAY_SIZE(debugfs_files),
1450 dc->debugfs, minor);
1451 if (err < 0)
1452 goto free;
1453
1454 dc->minor = minor;
1455
1456 return 0;
1457
1458free:
1459 kfree(dc->debugfs_files);
1460 dc->debugfs_files = NULL;
1461remove:
1462 debugfs_remove(dc->debugfs);
1463 dc->debugfs = NULL;
1464
1465 return err;
1466}
1467
1468static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1469{
1470 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1471 dc->minor);
1472 dc->minor = NULL;
1473
1474 kfree(dc->debugfs_files);
1475 dc->debugfs_files = NULL;
1476
1477 debugfs_remove(dc->debugfs);
1478 dc->debugfs = NULL;
1479
1480 return 0;
1481}
1482
53fa7f72 1483static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1484{
9910f5c4 1485 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1486 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1487 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1488 struct drm_plane *primary = NULL;
1489 struct drm_plane *cursor = NULL;
d8f4a9ed
TR		 1490 int err;
1491
df06b759
TR		 1492 if (tegra->domain) {
1493 err = iommu_attach_device(tegra->domain, dc->dev);
1494 if (err < 0) {
1495 dev_err(dc->dev, "failed to attach to domain: %d\n",
1496 err);
1497 return err;
1498 }
1499
1500 dc->domain = tegra->domain;
1501 }
1502
c7679306
TR		 1503 primary = tegra_dc_primary_plane_create(drm, dc);
1504 if (IS_ERR(primary)) {
1505 err = PTR_ERR(primary);
1506 goto cleanup;
1507 }
1508
1509 if (dc->soc->supports_cursor) {
1510 cursor = tegra_dc_cursor_plane_create(drm, dc);
1511 if (IS_ERR(cursor)) {
1512 err = PTR_ERR(cursor);
1513 goto cleanup;
1514 }
1515 }
1516
1517 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1518 &tegra_crtc_funcs);
1519 if (err < 0)
1520 goto cleanup;
1521
d8f4a9ed
TR		 1522 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1523 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1524
d1f3e1e0
TR		 1525 /*
1526 * Keep track of the minimum pitch alignment across all display
1527 * controllers.
1528 */
1529 if (dc->soc->pitch_align > tegra->pitch_align)
1530 tegra->pitch_align = dc->soc->pitch_align;
1531
9910f5c4 1532 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1533 if (err < 0 && err != -ENODEV) {
1534 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1535 goto cleanup;
d8f4a9ed
TR		 1536 }
1537
9910f5c4 1538 err = tegra_dc_add_planes(drm, dc);
f34bc787 1539 if (err < 0)
c7679306 1540 goto cleanup;
f34bc787 1541
d8f4a9ed 1542 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1543 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1544 if (err < 0)
1545 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1546 }
1547
6e5ff998 1548 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1549 dev_name(dc->dev), dc);
1550 if (err < 0) {
1551 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1552 err);
c7679306 1553 goto cleanup;
d8f4a9ed
TR		 1554 }
1555
1556 return 0;
c7679306
TR		 1557
1558cleanup:
1559 if (cursor)
1560 drm_plane_cleanup(cursor);
1561
1562 if (primary)
1563 drm_plane_cleanup(primary);
1564
1565 if (tegra->domain) {
1566 iommu_detach_device(tegra->domain, dc->dev);
1567 dc->domain = NULL;
1568 }
1569
1570 return err;
d8f4a9ed
TR		 1571}
1572
53fa7f72 1573static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1574{
776dc384 1575 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1576 int err;
1577
1578 devm_free_irq(dc->dev, dc->irq, dc);
1579
1580 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1581 err = tegra_dc_debugfs_exit(dc);
1582 if (err < 0)
1583 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1584 }
1585
1586 err = tegra_dc_rgb_exit(dc);
1587 if (err) {
1588 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1589 return err;
1590 }
1591
df06b759
TR		 1592 if (dc->domain) {
1593 iommu_detach_device(dc->domain, dc->dev);
1594 dc->domain = NULL;
1595 }
1596
d8f4a9ed
TR		 1597 return 0;
1598}
1599
1600static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1601 .init = tegra_dc_init,
1602 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1603};
1604
8620fc62 1605static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1606 .supports_border_color = true,
8620fc62 1607 .supports_interlacing = false,
e687651b 1608 .supports_cursor = false,
c134f019 1609 .supports_block_linear = false,
d1f3e1e0 1610 .pitch_align = 8,
9c012700 1611 .has_powergate = false,
8620fc62
TR		 1612};
1613
1614static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1615 .supports_border_color = true,
8620fc62 1616 .supports_interlacing = false,
e687651b 1617 .supports_cursor = false,
c134f019 1618 .supports_block_linear = false,
d1f3e1e0 1619 .pitch_align = 8,
9c012700 1620 .has_powergate = false,
d1f3e1e0
TR		 1621};
1622
1623static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1624 .supports_border_color = true,
d1f3e1e0
TR		 1625 .supports_interlacing = false,
1626 .supports_cursor = false,
1627 .supports_block_linear = false,
1628 .pitch_align = 64,
9c012700 1629 .has_powergate = true,
8620fc62
TR		 1630};
1631
1632static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1633 .supports_border_color = false,
8620fc62 1634 .supports_interlacing = true,
e687651b 1635 .supports_cursor = true,
c134f019 1636 .supports_block_linear = true,
d1f3e1e0 1637 .pitch_align = 64,
9c012700 1638 .has_powergate = true,
8620fc62
TR		 1639};
1640
1641static const struct of_device_id tegra_dc_of_match[] = {
1642 {
1643 .compatible = "nvidia,tegra124-dc",
1644 .data = &tegra124_dc_soc_info,
9c012700
TR		 1645 }, {
1646 .compatible = "nvidia,tegra114-dc",
1647 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1648 }, {
1649 .compatible = "nvidia,tegra30-dc",
1650 .data = &tegra30_dc_soc_info,
1651 }, {
1652 .compatible = "nvidia,tegra20-dc",
1653 .data = &tegra20_dc_soc_info,
1654 }, {
1655 /* sentinel */
1656 }
1657};
ef70728c 1658MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1659
13411ddd
TR		 1660static int tegra_dc_parse_dt(struct tegra_dc *dc)
1661{
1662 struct device_node *np;
1663 u32 value = 0;
1664 int err;
1665
1666 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1667 if (err < 0) {
1668 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1669
1670 /*
1671 * If the nvidia,head property isn't present, try to find the
1672 * correct head number by looking up the position of this
1673 * display controller's node within the device tree. Assuming
1674 * that the nodes are ordered properly in the DTS file and
1675 * that the translation into a flattened device tree blob
1676 * preserves that ordering this will actually yield the right
1677 * head number.
1678 *
1679 * If those assumptions don't hold, this will still work for
1680 * cases where only a single display controller is used.
1681 */
1682 for_each_matching_node(np, tegra_dc_of_match) {
1683 if (np == dc->dev->of_node)
1684 break;
1685
1686 value++;
1687 }
1688 }
1689
1690 dc->pipe = value;
1691
1692 return 0;
1693}
1694
d8f4a9ed
TR		 1695static int tegra_dc_probe(struct platform_device *pdev)
1696{
8620fc62 1697 const struct of_device_id *id;
d8f4a9ed
TR		 1698 struct resource *regs;
1699 struct tegra_dc *dc;
1700 int err;
1701
1702 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1703 if (!dc)
1704 return -ENOMEM;
1705
8620fc62
TR		 1706 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1707 if (!id)
1708 return -ENODEV;
1709
6e5ff998 1710 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1711 INIT_LIST_HEAD(&dc->list);
1712 dc->dev = &pdev->dev;
8620fc62 1713 dc->soc = id->data;
d8f4a9ed 1714
13411ddd
TR		 1715 err = tegra_dc_parse_dt(dc);
1716 if (err < 0)
1717 return err;
1718
d8f4a9ed
TR		 1719 dc->clk = devm_clk_get(&pdev->dev, NULL);
1720 if (IS_ERR(dc->clk)) {
1721 dev_err(&pdev->dev, "failed to get clock\n");
1722 return PTR_ERR(dc->clk);
1723 }
1724
ca48080a
SW		 1725 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1726 if (IS_ERR(dc->rst)) {
1727 dev_err(&pdev->dev, "failed to get reset\n");
1728 return PTR_ERR(dc->rst);
1729 }
1730
9c012700
TR		 1731 if (dc->soc->has_powergate) {
1732 if (dc->pipe == 0)
1733 dc->powergate = TEGRA_POWERGATE_DIS;
1734 else
1735 dc->powergate = TEGRA_POWERGATE_DISB;
1736
1737 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1738 dc->rst);
1739 if (err < 0) {
1740 dev_err(&pdev->dev, "failed to power partition: %d\n",
1741 err);
1742 return err;
1743 }
1744 } else {
1745 err = clk_prepare_enable(dc->clk);
1746 if (err < 0) {
1747 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1748 err);
1749 return err;
1750 }
1751
1752 err = reset_control_deassert(dc->rst);
1753 if (err < 0) {
1754 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1755 err);
1756 return err;
1757 }
1758 }
d8f4a9ed
TR		 1759
1760 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1761 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1762 if (IS_ERR(dc->regs))
1763 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1764
1765 dc->irq = platform_get_irq(pdev, 0);
1766 if (dc->irq < 0) {
1767 dev_err(&pdev->dev, "failed to get IRQ\n");
1768 return -ENXIO;
1769 }
1770
776dc384
TR		 1771 INIT_LIST_HEAD(&dc->client.list);
1772 dc->client.ops = &dc_client_ops;
1773 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1774
1775 err = tegra_dc_rgb_probe(dc);
1776 if (err < 0 && err != -ENODEV) {
1777 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1778 return err;
1779 }
1780
776dc384 1781 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1782 if (err < 0) {
1783 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1784 err);
1785 return err;
1786 }
1787
1788 platform_set_drvdata(pdev, dc);
1789
1790 return 0;
1791}
1792
1793static int tegra_dc_remove(struct platform_device *pdev)
1794{
d8f4a9ed
TR		 1795 struct tegra_dc *dc = platform_get_drvdata(pdev);
1796 int err;
1797
776dc384 1798 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1799 if (err < 0) {
1800 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1801 err);
1802 return err;
1803 }
1804
59d29c0e
TR		 1805 err = tegra_dc_rgb_remove(dc);
1806 if (err < 0) {
1807 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1808 return err;
1809 }
1810
5482d75a 1811 reset_control_assert(dc->rst);
9c012700
TR		 1812
1813 if (dc->soc->has_powergate)
1814 tegra_powergate_power_off(dc->powergate);
1815
d8f4a9ed
TR		 1816 clk_disable_unprepare(dc->clk);
1817
1818 return 0;
1819}
1820
d8f4a9ed
TR		 1821struct platform_driver tegra_dc_driver = {
1822 .driver = {
1823 .name = "tegra-dc",
1824 .owner = THIS_MODULE,
1825 .of_match_table = tegra_dc_of_match,
1826 },
1827 .probe = tegra_dc_probe,
1828 .remove = tegra_dc_remove,
1829};
Linux kernel - Deliverables
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