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drm/tegra: dc - Do not touch power control register
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
ca48080a 12#include <linux/reset.h>
d8f4a9ed 13
de2ba664
AM		 14#include "dc.h"
15#include "drm.h"
16#include "gem.h"
d8f4a9ed 17
8620fc62
TR		 18struct tegra_dc_soc_info {
19 bool supports_interlacing;
20};
21
f34bc787
TR		 22struct tegra_plane {
23 struct drm_plane base;
24 unsigned int index;
d8f4a9ed
TR		 25};
26
f34bc787
TR		 27static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
28{
29 return container_of(plane, struct tegra_plane, base);
30}
31
10288eea
TR		 32static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
33{
34 /* assume no swapping of fetched data */
35 if (swap)
36 *swap = BYTE_SWAP_NOSWAP;
37
38 switch (format) {
39 case DRM_FORMAT_XBGR8888:
40 return WIN_COLOR_DEPTH_R8G8B8A8;
41
42 case DRM_FORMAT_XRGB8888:
43 return WIN_COLOR_DEPTH_B8G8R8A8;
44
45 case DRM_FORMAT_RGB565:
46 return WIN_COLOR_DEPTH_B5G6R5;
47
48 case DRM_FORMAT_UYVY:
49 return WIN_COLOR_DEPTH_YCbCr422;
50
51 case DRM_FORMAT_YUYV:
52 if (swap)
53 *swap = BYTE_SWAP_SWAP2;
54
55 return WIN_COLOR_DEPTH_YCbCr422;
56
57 case DRM_FORMAT_YUV420:
58 return WIN_COLOR_DEPTH_YCbCr420P;
59
60 case DRM_FORMAT_YUV422:
61 return WIN_COLOR_DEPTH_YCbCr422P;
62
63 default:
64 break;
65 }
66
67 WARN(1, "unsupported pixel format %u, using default\n", format);
68 return WIN_COLOR_DEPTH_B8G8R8A8;
69}
70
71static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
72{
73 switch (format) {
74 case WIN_COLOR_DEPTH_YCbCr422:
75 case WIN_COLOR_DEPTH_YUV422:
76 if (planar)
77 *planar = false;
78
79 return true;
80
81 case WIN_COLOR_DEPTH_YCbCr420P:
82 case WIN_COLOR_DEPTH_YUV420P:
83 case WIN_COLOR_DEPTH_YCbCr422P:
84 case WIN_COLOR_DEPTH_YUV422P:
85 case WIN_COLOR_DEPTH_YCbCr422R:
86 case WIN_COLOR_DEPTH_YUV422R:
87 case WIN_COLOR_DEPTH_YCbCr422RA:
88 case WIN_COLOR_DEPTH_YUV422RA:
89 if (planar)
90 *planar = true;
91
92 return true;
93 }
94
95 return false;
96}
97
98static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
99 unsigned int bpp)
100{
101 fixed20_12 outf = dfixed_init(out);
102 fixed20_12 inf = dfixed_init(in);
103 u32 dda_inc;
104 int max;
105
106 if (v)
107 max = 15;
108 else {
109 switch (bpp) {
110 case 2:
111 max = 8;
112 break;
113
114 default:
115 WARN_ON_ONCE(1);
116 /* fallthrough */
117 case 4:
118 max = 4;
119 break;
120 }
121 }
122
123 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
124 inf.full -= dfixed_const(1);
125
126 dda_inc = dfixed_div(inf, outf);
127 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
128
129 return dda_inc;
130}
131
132static inline u32 compute_initial_dda(unsigned int in)
133{
134 fixed20_12 inf = dfixed_init(in);
135 return dfixed_frac(inf);
136}
137
138static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
139 const struct tegra_dc_window *window)
140{
141 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
142 unsigned long value;
143 bool yuv, planar;
144
145 /*
146 * For YUV planar modes, the number of bytes per pixel takes into
147 * account only the luma component and therefore is 1.
148 */
149 yuv = tegra_dc_format_is_yuv(window->format, &planar);
150 if (!yuv)
151 bpp = window->bits_per_pixel / 8;
152 else
153 bpp = planar ? 1 : 2;
154
155 value = WINDOW_A_SELECT << index;
156 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
157
158 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
159 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
160
161 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
162 tegra_dc_writel(dc, value, DC_WIN_POSITION);
163
164 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
165 tegra_dc_writel(dc, value, DC_WIN_SIZE);
166
167 h_offset = window->src.x * bpp;
168 v_offset = window->src.y;
169 h_size = window->src.w * bpp;
170 v_size = window->src.h;
171
172 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
173 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
174
175 /*
176 * For DDA computations the number of bytes per pixel for YUV planar
177 * modes needs to take into account all Y, U and V components.
178 */
179 if (yuv && planar)
180 bpp = 2;
181
182 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
183 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
184
185 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
186 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
187
188 h_dda = compute_initial_dda(window->src.x);
189 v_dda = compute_initial_dda(window->src.y);
190
191 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
192 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
193
194 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
195 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
196
197 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
198
199 if (yuv && planar) {
200 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
201 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
202 value = window->stride[1] << 16 | window->stride[0];
203 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
204 } else {
205 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
206 }
207
208 if (window->bottom_up)
209 v_offset += window->src.h - 1;
210
211 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
212 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
213
214 if (window->tiled) {
215 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
216 DC_WIN_BUFFER_ADDR_MODE_TILE;
217 } else {
218 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
219 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
220 }
221
222 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
223
224 value = WIN_ENABLE;
225
226 if (yuv) {
227 /* setup default colorspace conversion coefficients */
228 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
229 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
230 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
231 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
232 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
233 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
234 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
235 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
236
237 value |= CSC_ENABLE;
238 } else if (window->bits_per_pixel < 24) {
239 value |= COLOR_EXPAND;
240 }
241
242 if (window->bottom_up)
243 value |= V_DIRECTION;
244
245 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
246
247 /*
248 * Disable blending and assume Window A is the bottom-most window,
249 * Window C is the top-most window and Window B is in the middle.
250 */
251 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
252 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
253
254 switch (index) {
255 case 0:
256 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
257 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
258 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
259 break;
260
261 case 1:
262 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
263 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
264 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
265 break;
266
267 case 2:
268 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
269 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
270 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
271 break;
272 }
273
274 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
275 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
276
277 return 0;
278}
279
f34bc787
TR		 280static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
281 struct drm_framebuffer *fb, int crtc_x,
282 int crtc_y, unsigned int crtc_w,
283 unsigned int crtc_h, uint32_t src_x,
284 uint32_t src_y, uint32_t src_w, uint32_t src_h)
285{
286 struct tegra_plane *p = to_tegra_plane(plane);
287 struct tegra_dc *dc = to_tegra_dc(crtc);
288 struct tegra_dc_window window;
289 unsigned int i;
290
291 memset(&window, 0, sizeof(window));
292 window.src.x = src_x >> 16;
293 window.src.y = src_y >> 16;
294 window.src.w = src_w >> 16;
295 window.src.h = src_h >> 16;
296 window.dst.x = crtc_x;
297 window.dst.y = crtc_y;
298 window.dst.w = crtc_w;
299 window.dst.h = crtc_h;
f925390e 300 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
f34bc787 301 window.bits_per_pixel = fb->bits_per_pixel;
db7fbdfd 302 window.bottom_up = tegra_fb_is_bottom_up(fb);
773af77f 303 window.tiled = tegra_fb_is_tiled(fb);
f34bc787
TR		 304
305 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 306 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 307
de2ba664 308 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 309
310 /*
311 * Tegra doesn't support different strides for U and V planes
312 * so we display a warning if the user tries to display a
313 * framebuffer with such a configuration.
314 */
315 if (i >= 2) {
316 if (fb->pitches[i] != window.stride[1])
317 DRM_ERROR("unsupported UV-plane configuration\n");
318 } else {
319 window.stride[i] = fb->pitches[i];
320 }
321 }
322
323 return tegra_dc_setup_window(dc, p->index, &window);
324}
325
326static int tegra_plane_disable(struct drm_plane *plane)
327{
328 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
329 struct tegra_plane *p = to_tegra_plane(plane);
330 unsigned long value;
331
2678aeba
TR		 332 if (!plane->crtc)
333 return 0;
334
f34bc787
TR		 335 value = WINDOW_A_SELECT << p->index;
336 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
337
338 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
339 value &= ~WIN_ENABLE;
340 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
341
342 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
343 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
344
345 return 0;
346}
347
348static void tegra_plane_destroy(struct drm_plane *plane)
349{
f002abc1
TR		 350 struct tegra_plane *p = to_tegra_plane(plane);
351
f34bc787
TR		 352 tegra_plane_disable(plane);
353 drm_plane_cleanup(plane);
f002abc1 354 kfree(p);
f34bc787
TR		 355}
356
357static const struct drm_plane_funcs tegra_plane_funcs = {
358 .update_plane = tegra_plane_update,
359 .disable_plane = tegra_plane_disable,
360 .destroy = tegra_plane_destroy,
361};
362
363static const uint32_t plane_formats[] = {
dbe4d9a7 364 DRM_FORMAT_XBGR8888,
f34bc787 365 DRM_FORMAT_XRGB8888,
dbe4d9a7 366 DRM_FORMAT_RGB565,
f34bc787 367 DRM_FORMAT_UYVY,
f925390e 368 DRM_FORMAT_YUYV,
f34bc787
TR		 369 DRM_FORMAT_YUV420,
370 DRM_FORMAT_YUV422,
371};
372
373static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
374{
375 unsigned int i;
376 int err = 0;
377
378 for (i = 0; i < 2; i++) {
379 struct tegra_plane *plane;
380
f002abc1 381 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
f34bc787
TR		 382 if (!plane)
383 return -ENOMEM;
384
385 plane->index = 1 + i;
386
387 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
388 &tegra_plane_funcs, plane_formats,
389 ARRAY_SIZE(plane_formats), false);
f002abc1
TR		 390 if (err < 0) {
391 kfree(plane);
f34bc787 392 return err;
f002abc1 393 }
f34bc787
TR		 394 }
395
396 return 0;
397}
398
23fb4740
TR		 399static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
400 struct drm_framebuffer *fb)
401{
de2ba664 402 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
db7fbdfd 403 unsigned int h_offset = 0, v_offset = 0;
f925390e 404 unsigned int format, swap;
23fb4740
TR		 405 unsigned long value;
406
407 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
408
409 value = fb->offsets[0] + y * fb->pitches[0] +
410 x * fb->bits_per_pixel / 8;
411
de2ba664 412 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 413 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
f925390e
TR		 414
415 format = tegra_dc_format(fb->pixel_format, &swap);
ed683aea 416 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
f925390e 417 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
23fb4740 418
773af77f
TR		 419 if (tegra_fb_is_tiled(fb)) {
420 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
421 DC_WIN_BUFFER_ADDR_MODE_TILE;
422 } else {
423 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
424 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
425 }
426
427 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
428
db7fbdfd
TR		 429 /* make sure bottom-up buffers are properly displayed */
430 if (tegra_fb_is_bottom_up(fb)) {
431 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 432 value |= V_DIRECTION;
db7fbdfd
TR		 433 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
434
435 v_offset += fb->height - 1;
436 } else {
437 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 438 value &= ~V_DIRECTION;
db7fbdfd
TR		 439 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
440 }
441
442 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
443 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
444
23fb4740
TR		 445 value = GENERAL_UPDATE | WIN_A_UPDATE;
446 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
447
448 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
449 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
450
451 return 0;
452}
453
6e5ff998
TR		 454void tegra_dc_enable_vblank(struct tegra_dc *dc)
455{
456 unsigned long value, flags;
457
458 spin_lock_irqsave(&dc->lock, flags);
459
460 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
461 value |= VBLANK_INT;
462 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
463
464 spin_unlock_irqrestore(&dc->lock, flags);
465}
466
467void tegra_dc_disable_vblank(struct tegra_dc *dc)
468{
469 unsigned long value, flags;
470
471 spin_lock_irqsave(&dc->lock, flags);
472
473 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
474 value &= ~VBLANK_INT;
475 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
476
477 spin_unlock_irqrestore(&dc->lock, flags);
478}
479
3c03c46a
TR		 480static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
481{
482 struct drm_device *drm = dc->base.dev;
483 struct drm_crtc *crtc = &dc->base;
3c03c46a 484 unsigned long flags, base;
de2ba664 485 struct tegra_bo *bo;
3c03c46a
TR		 486
487 if (!dc->event)
488 return;
489
f4510a27 490 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a
TR		 491
492 /* check if new start address has been latched */
493 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
494 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
495 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
496
f4510a27 497 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
3c03c46a
TR		 498 spin_lock_irqsave(&drm->event_lock, flags);
499 drm_send_vblank_event(drm, dc->pipe, dc->event);
500 drm_vblank_put(drm, dc->pipe);
501 dc->event = NULL;
502 spin_unlock_irqrestore(&drm->event_lock, flags);
503 }
504}
505
506void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
507{
508 struct tegra_dc *dc = to_tegra_dc(crtc);
509 struct drm_device *drm = crtc->dev;
510 unsigned long flags;
511
512 spin_lock_irqsave(&drm->event_lock, flags);
513
514 if (dc->event && dc->event->base.file_priv == file) {
515 dc->event->base.destroy(&dc->event->base);
516 drm_vblank_put(drm, dc->pipe);
517 dc->event = NULL;
518 }
519
520 spin_unlock_irqrestore(&drm->event_lock, flags);
521}
522
523static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 524 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a
TR		 525{
526 struct tegra_dc *dc = to_tegra_dc(crtc);
527 struct drm_device *drm = crtc->dev;
528
529 if (dc->event)
530 return -EBUSY;
531
532 if (event) {
533 event->pipe = dc->pipe;
534 dc->event = event;
535 drm_vblank_get(drm, dc->pipe);
536 }
537
538 tegra_dc_set_base(dc, 0, 0, fb);
f4510a27 539 crtc->primary->fb = fb;
3c03c46a
TR		 540
541 return 0;
542}
543
f002abc1
TR		 544static void drm_crtc_clear(struct drm_crtc *crtc)
545{
546 memset(crtc, 0, sizeof(*crtc));
547}
548
549static void tegra_dc_destroy(struct drm_crtc *crtc)
550{
551 drm_crtc_cleanup(crtc);
552 drm_crtc_clear(crtc);
553}
554
d8f4a9ed 555static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 556 .page_flip = tegra_dc_page_flip,
d8f4a9ed 557 .set_config = drm_crtc_helper_set_config,
f002abc1 558 .destroy = tegra_dc_destroy,
d8f4a9ed
TR		 559};
560
f34bc787 561static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 562{
f002abc1 563 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787
TR		 564 struct drm_device *drm = crtc->dev;
565 struct drm_plane *plane;
566
2b4c3661 567 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
f34bc787
TR		 568 if (plane->crtc == crtc) {
569 tegra_plane_disable(plane);
570 plane->crtc = NULL;
571
572 if (plane->fb) {
573 drm_framebuffer_unreference(plane->fb);
574 plane->fb = NULL;
575 }
576 }
577 }
f002abc1
TR		 578
579 drm_vblank_off(drm, dc->pipe);
d8f4a9ed
TR		 580}
581
582static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
583 const struct drm_display_mode *mode,
584 struct drm_display_mode *adjusted)
585{
586 return true;
587}
588
d8f4a9ed
TR		 589static int tegra_dc_set_timings(struct tegra_dc *dc,
590 struct drm_display_mode *mode)
591{
592 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
593 unsigned int h_ref_to_sync = 0;
594 unsigned int v_ref_to_sync = 0;
595 unsigned long value;
596
597 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
598
599 value = (v_ref_to_sync << 16) | h_ref_to_sync;
600 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
601
602 value = ((mode->vsync_end - mode->vsync_start) << 16) |
603 ((mode->hsync_end - mode->hsync_start) << 0);
604 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
605
d8f4a9ed
TR		 606 value = ((mode->vtotal - mode->vsync_end) << 16) |
607 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 608 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
609
610 value = ((mode->vsync_start - mode->vdisplay) << 16) |
611 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 612 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
613
614 value = (mode->vdisplay << 16) | mode->hdisplay;
615 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
616
617 return 0;
618}
619
620static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
621 struct drm_display_mode *mode,
622 unsigned long *div)
623{
624 unsigned long pclk = mode->clock * 1000, rate;
625 struct tegra_dc *dc = to_tegra_dc(crtc);
626 struct tegra_output *output = NULL;
627 struct drm_encoder *encoder;
628 long err;
629
630 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
631 if (encoder->crtc == crtc) {
632 output = encoder_to_output(encoder);
633 break;
634 }
635
636 if (!output)
637 return -ENODEV;
638
639 /*
640 * This assumes that the display controller will divide its parent
641 * clock by 2 to generate the pixel clock.
642 */
643 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
644 if (err < 0) {
645 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
646 return err;
647 }
648
649 rate = clk_get_rate(dc->clk);
650 *div = (rate * 2 / pclk) - 2;
651
652 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
653
654 return 0;
655}
656
657static int tegra_crtc_mode_set(struct drm_crtc *crtc,
658 struct drm_display_mode *mode,
659 struct drm_display_mode *adjusted,
660 int x, int y, struct drm_framebuffer *old_fb)
661{
f4510a27 662 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
d8f4a9ed 663 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 664 struct tegra_dc_window window;
d8f4a9ed
TR		 665 unsigned long div, value;
666 int err;
667
6e5ff998
TR		 668 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
669
d8f4a9ed
TR		 670 err = tegra_crtc_setup_clk(crtc, mode, &div);
671 if (err) {
672 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
673 return err;
674 }
675
676 /* program display mode */
677 tegra_dc_set_timings(dc, mode);
678
8620fc62
TR		 679 /* interlacing isn't supported yet, so disable it */
680 if (dc->soc->supports_interlacing) {
681 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
682 value &= ~INTERLACE_ENABLE;
683 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
684 }
685
d8f4a9ed
TR		 686 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
687 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
688
689 /* setup window parameters */
f34bc787
TR		 690 memset(&window, 0, sizeof(window));
691 window.src.x = 0;
692 window.src.y = 0;
693 window.src.w = mode->hdisplay;
694 window.src.h = mode->vdisplay;
695 window.dst.x = 0;
696 window.dst.y = 0;
697 window.dst.w = mode->hdisplay;
698 window.dst.h = mode->vdisplay;
f925390e
TR		 699 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
700 &window.swap);
f4510a27
MR		 701 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
702 window.stride[0] = crtc->primary->fb->pitches[0];
de2ba664 703 window.base[0] = bo->paddr;
f34bc787
TR		 704
705 err = tegra_dc_setup_window(dc, 0, &window);
706 if (err < 0)
707 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 708
d8f4a9ed
TR		 709 return 0;
710}
d8f4a9ed 711
23fb4740
TR		 712static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
713 struct drm_framebuffer *old_fb)
714{
715 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 716
f4510a27 717 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
d8f4a9ed
TR		 718}
719
720static void tegra_crtc_prepare(struct drm_crtc *crtc)
721{
722 struct tegra_dc *dc = to_tegra_dc(crtc);
723 unsigned int syncpt;
724 unsigned long value;
725
726 /* hardware initialization */
ca48080a 727 reset_control_deassert(dc->rst);
d8f4a9ed
TR		 728 usleep_range(10000, 20000);
729
730 if (dc->pipe)
731 syncpt = SYNCPT_VBLANK1;
732 else
733 syncpt = SYNCPT_VBLANK0;
734
735 /* initialize display controller */
736 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
737 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
738
739 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
740 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
741
742 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
743 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
744 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
745
d8f4a9ed
TR		 746 /* initialize timer */
747 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
748 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
749 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
750
751 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
752 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
753 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
754
d8f4a9ed
TR		 755 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
756 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 757
758 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
759 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 760}
761
762static void tegra_crtc_commit(struct drm_crtc *crtc)
763{
764 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 765 unsigned long value;
766
3b9e71ea
TR		 767 value = GENERAL_UPDATE | WIN_A_UPDATE;
768 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 769
3b9e71ea 770 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 771 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 772
6e5ff998 773 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 774}
775
776static void tegra_crtc_load_lut(struct drm_crtc *crtc)
777{
778}
779
780static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 781 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 782 .mode_fixup = tegra_crtc_mode_fixup,
783 .mode_set = tegra_crtc_mode_set,
23fb4740 784 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 785 .prepare = tegra_crtc_prepare,
786 .commit = tegra_crtc_commit,
787 .load_lut = tegra_crtc_load_lut,
788};
789
6e5ff998 790static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 791{
792 struct tegra_dc *dc = data;
793 unsigned long status;
794
795 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
796 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
797
798 if (status & FRAME_END_INT) {
799 /*
800 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
801 */
802 }
803
804 if (status & VBLANK_INT) {
805 /*
806 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
807 */
808 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 809 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 810 }
811
812 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
813 /*
814 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
815 */
816 }
817
818 return IRQ_HANDLED;
819}
820
821static int tegra_dc_show_regs(struct seq_file *s, void *data)
822{
823 struct drm_info_node *node = s->private;
824 struct tegra_dc *dc = node->info_ent->data;
825
826#define DUMP_REG(name) \
827 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
828 tegra_dc_readl(dc, name))
829
830 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
831 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
832 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
833 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
834 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
835 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
836 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
837 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
838 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
839 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
840 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
841 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
842 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
843 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
844 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
845 DUMP_REG(DC_CMD_SIGNAL_RAISE);
846 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
847 DUMP_REG(DC_CMD_INT_STATUS);
848 DUMP_REG(DC_CMD_INT_MASK);
849 DUMP_REG(DC_CMD_INT_ENABLE);
850 DUMP_REG(DC_CMD_INT_TYPE);
851 DUMP_REG(DC_CMD_INT_POLARITY);
852 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
853 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
854 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
855 DUMP_REG(DC_CMD_STATE_ACCESS);
856 DUMP_REG(DC_CMD_STATE_CONTROL);
857 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
858 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
859 DUMP_REG(DC_COM_CRC_CONTROL);
860 DUMP_REG(DC_COM_CRC_CHECKSUM);
861 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
862 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
863 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
864 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
865 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
866 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
867 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
868 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
869 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
870 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
871 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
872 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
873 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
874 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
875 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
876 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
877 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
878 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
879 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
880 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
881 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
882 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
883 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
884 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
885 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
886 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
887 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
888 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
889 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
890 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
891 DUMP_REG(DC_COM_SPI_CONTROL);
892 DUMP_REG(DC_COM_SPI_START_BYTE);
893 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
894 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
895 DUMP_REG(DC_COM_HSPI_CS_DC);
896 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
897 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
898 DUMP_REG(DC_COM_GPIO_CTRL);
899 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
900 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
901 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
902 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
903 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
904 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
905 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
906 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
907 DUMP_REG(DC_DISP_REF_TO_SYNC);
908 DUMP_REG(DC_DISP_SYNC_WIDTH);
909 DUMP_REG(DC_DISP_BACK_PORCH);
910 DUMP_REG(DC_DISP_ACTIVE);
911 DUMP_REG(DC_DISP_FRONT_PORCH);
912 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
913 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
914 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
915 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
916 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
917 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
918 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
919 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
920 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
921 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
922 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
923 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
924 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
925 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
926 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
927 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
928 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
929 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
930 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
931 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
932 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
933 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
934 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
935 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
936 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
937 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
938 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
939 DUMP_REG(DC_DISP_M0_CONTROL);
940 DUMP_REG(DC_DISP_M1_CONTROL);
941 DUMP_REG(DC_DISP_DI_CONTROL);
942 DUMP_REG(DC_DISP_PP_CONTROL);
943 DUMP_REG(DC_DISP_PP_SELECT_A);
944 DUMP_REG(DC_DISP_PP_SELECT_B);
945 DUMP_REG(DC_DISP_PP_SELECT_C);
946 DUMP_REG(DC_DISP_PP_SELECT_D);
947 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
948 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
949 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
950 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
951 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
952 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
953 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
954 DUMP_REG(DC_DISP_BORDER_COLOR);
955 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
956 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
957 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
958 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
959 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
960 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
961 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
962 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
963 DUMP_REG(DC_DISP_CURSOR_POSITION);
964 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
965 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
966 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
967 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
968 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
969 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
970 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
971 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
972 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
973 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
974 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
975 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
976 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
977 DUMP_REG(DC_DISP_SD_CONTROL);
978 DUMP_REG(DC_DISP_SD_CSC_COEFF);
979 DUMP_REG(DC_DISP_SD_LUT(0));
980 DUMP_REG(DC_DISP_SD_LUT(1));
981 DUMP_REG(DC_DISP_SD_LUT(2));
982 DUMP_REG(DC_DISP_SD_LUT(3));
983 DUMP_REG(DC_DISP_SD_LUT(4));
984 DUMP_REG(DC_DISP_SD_LUT(5));
985 DUMP_REG(DC_DISP_SD_LUT(6));
986 DUMP_REG(DC_DISP_SD_LUT(7));
987 DUMP_REG(DC_DISP_SD_LUT(8));
988 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
989 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
990 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
991 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
992 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
993 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
994 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
995 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
996 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
997 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
998 DUMP_REG(DC_DISP_SD_BL_TF(0));
999 DUMP_REG(DC_DISP_SD_BL_TF(1));
1000 DUMP_REG(DC_DISP_SD_BL_TF(2));
1001 DUMP_REG(DC_DISP_SD_BL_TF(3));
1002 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1003 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1004 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1005 DUMP_REG(DC_WIN_WIN_OPTIONS);
1006 DUMP_REG(DC_WIN_BYTE_SWAP);
1007 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1008 DUMP_REG(DC_WIN_COLOR_DEPTH);
1009 DUMP_REG(DC_WIN_POSITION);
1010 DUMP_REG(DC_WIN_SIZE);
1011 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1012 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1013 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1014 DUMP_REG(DC_WIN_DDA_INC);
1015 DUMP_REG(DC_WIN_LINE_STRIDE);
1016 DUMP_REG(DC_WIN_BUF_STRIDE);
1017 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1018 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1019 DUMP_REG(DC_WIN_DV_CONTROL);
1020 DUMP_REG(DC_WIN_BLEND_NOKEY);
1021 DUMP_REG(DC_WIN_BLEND_1WIN);
1022 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1023 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1024 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1025 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1026 DUMP_REG(DC_WINBUF_START_ADDR);
1027 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1028 DUMP_REG(DC_WINBUF_START_ADDR_U);
1029 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1030 DUMP_REG(DC_WINBUF_START_ADDR_V);
1031 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1032 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1033 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1034 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1035 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1036 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1037 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1038 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1039 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1040
1041#undef DUMP_REG
1042
1043 return 0;
1044}
1045
1046static struct drm_info_list debugfs_files[] = {
1047 { "regs", tegra_dc_show_regs, 0, NULL },
1048};
1049
1050static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1051{
1052 unsigned int i;
1053 char *name;
1054 int err;
1055
1056 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1057 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1058 kfree(name);
1059
1060 if (!dc->debugfs)
1061 return -ENOMEM;
1062
1063 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1064 GFP_KERNEL);
1065 if (!dc->debugfs_files) {
1066 err = -ENOMEM;
1067 goto remove;
1068 }
1069
1070 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1071 dc->debugfs_files[i].data = dc;
1072
1073 err = drm_debugfs_create_files(dc->debugfs_files,
1074 ARRAY_SIZE(debugfs_files),
1075 dc->debugfs, minor);
1076 if (err < 0)
1077 goto free;
1078
1079 dc->minor = minor;
1080
1081 return 0;
1082
1083free:
1084 kfree(dc->debugfs_files);
1085 dc->debugfs_files = NULL;
1086remove:
1087 debugfs_remove(dc->debugfs);
1088 dc->debugfs = NULL;
1089
1090 return err;
1091}
1092
1093static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1094{
1095 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1096 dc->minor);
1097 dc->minor = NULL;
1098
1099 kfree(dc->debugfs_files);
1100 dc->debugfs_files = NULL;
1101
1102 debugfs_remove(dc->debugfs);
1103 dc->debugfs = NULL;
1104
1105 return 0;
1106}
1107
53fa7f72 1108static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1109{
776dc384
TR		 1110 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1111 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1112 int err;
1113
776dc384 1114 drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs);
d8f4a9ed
TR		 1115 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1116 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1117
776dc384 1118 err = tegra_dc_rgb_init(tegra->drm, dc);
d8f4a9ed
TR		 1119 if (err < 0 && err != -ENODEV) {
1120 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1121 return err;
1122 }
1123
776dc384 1124 err = tegra_dc_add_planes(tegra->drm, dc);
f34bc787
TR		 1125 if (err < 0)
1126 return err;
1127
d8f4a9ed 1128 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
776dc384 1129 err = tegra_dc_debugfs_init(dc, tegra->drm->primary);
d8f4a9ed
TR		 1130 if (err < 0)
1131 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1132 }
1133
6e5ff998 1134 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1135 dev_name(dc->dev), dc);
1136 if (err < 0) {
1137 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1138 err);
1139 return err;
1140 }
1141
1142 return 0;
1143}
1144
53fa7f72 1145static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1146{
776dc384 1147 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1148 int err;
1149
1150 devm_free_irq(dc->dev, dc->irq, dc);
1151
1152 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1153 err = tegra_dc_debugfs_exit(dc);
1154 if (err < 0)
1155 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1156 }
1157
1158 err = tegra_dc_rgb_exit(dc);
1159 if (err) {
1160 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1161 return err;
1162 }
1163
1164 return 0;
1165}
1166
1167static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1168 .init = tegra_dc_init,
1169 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1170};
1171
8620fc62
TR		 1172static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1173 .supports_interlacing = false,
1174};
1175
1176static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1177 .supports_interlacing = false,
1178};
1179
1180static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1181 .supports_interlacing = true,
1182};
1183
1184static const struct of_device_id tegra_dc_of_match[] = {
1185 {
1186 .compatible = "nvidia,tegra124-dc",
1187 .data = &tegra124_dc_soc_info,
1188 }, {
1189 .compatible = "nvidia,tegra30-dc",
1190 .data = &tegra30_dc_soc_info,
1191 }, {
1192 .compatible = "nvidia,tegra20-dc",
1193 .data = &tegra20_dc_soc_info,
1194 }, {
1195 /* sentinel */
1196 }
1197};
1198
13411ddd
TR		 1199static int tegra_dc_parse_dt(struct tegra_dc *dc)
1200{
1201 struct device_node *np;
1202 u32 value = 0;
1203 int err;
1204
1205 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1206 if (err < 0) {
1207 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1208
1209 /*
1210 * If the nvidia,head property isn't present, try to find the
1211 * correct head number by looking up the position of this
1212 * display controller's node within the device tree. Assuming
1213 * that the nodes are ordered properly in the DTS file and
1214 * that the translation into a flattened device tree blob
1215 * preserves that ordering this will actually yield the right
1216 * head number.
1217 *
1218 * If those assumptions don't hold, this will still work for
1219 * cases where only a single display controller is used.
1220 */
1221 for_each_matching_node(np, tegra_dc_of_match) {
1222 if (np == dc->dev->of_node)
1223 break;
1224
1225 value++;
1226 }
1227 }
1228
1229 dc->pipe = value;
1230
1231 return 0;
1232}
1233
d8f4a9ed
TR		 1234static int tegra_dc_probe(struct platform_device *pdev)
1235{
8620fc62 1236 const struct of_device_id *id;
d8f4a9ed
TR		 1237 struct resource *regs;
1238 struct tegra_dc *dc;
1239 int err;
1240
1241 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1242 if (!dc)
1243 return -ENOMEM;
1244
8620fc62
TR		 1245 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1246 if (!id)
1247 return -ENODEV;
1248
6e5ff998 1249 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1250 INIT_LIST_HEAD(&dc->list);
1251 dc->dev = &pdev->dev;
8620fc62 1252 dc->soc = id->data;
d8f4a9ed 1253
13411ddd
TR		 1254 err = tegra_dc_parse_dt(dc);
1255 if (err < 0)
1256 return err;
1257
d8f4a9ed
TR		 1258 dc->clk = devm_clk_get(&pdev->dev, NULL);
1259 if (IS_ERR(dc->clk)) {
1260 dev_err(&pdev->dev, "failed to get clock\n");
1261 return PTR_ERR(dc->clk);
1262 }
1263
ca48080a
SW		 1264 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1265 if (IS_ERR(dc->rst)) {
1266 dev_err(&pdev->dev, "failed to get reset\n");
1267 return PTR_ERR(dc->rst);
1268 }
1269
d8f4a9ed
TR		 1270 err = clk_prepare_enable(dc->clk);
1271 if (err < 0)
1272 return err;
1273
1274 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1275 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1276 if (IS_ERR(dc->regs))
1277 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1278
1279 dc->irq = platform_get_irq(pdev, 0);
1280 if (dc->irq < 0) {
1281 dev_err(&pdev->dev, "failed to get IRQ\n");
1282 return -ENXIO;
1283 }
1284
776dc384
TR		 1285 INIT_LIST_HEAD(&dc->client.list);
1286 dc->client.ops = &dc_client_ops;
1287 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1288
1289 err = tegra_dc_rgb_probe(dc);
1290 if (err < 0 && err != -ENODEV) {
1291 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1292 return err;
1293 }
1294
776dc384 1295 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1296 if (err < 0) {
1297 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1298 err);
1299 return err;
1300 }
1301
1302 platform_set_drvdata(pdev, dc);
1303
1304 return 0;
1305}
1306
1307static int tegra_dc_remove(struct platform_device *pdev)
1308{
d8f4a9ed
TR		 1309 struct tegra_dc *dc = platform_get_drvdata(pdev);
1310 int err;
1311
776dc384 1312 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1313 if (err < 0) {
1314 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1315 err);
1316 return err;
1317 }
1318
59d29c0e
TR		 1319 err = tegra_dc_rgb_remove(dc);
1320 if (err < 0) {
1321 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1322 return err;
1323 }
1324
d8f4a9ed
TR		 1325 clk_disable_unprepare(dc->clk);
1326
1327 return 0;
1328}
1329
d8f4a9ed
TR		 1330struct platform_driver tegra_dc_driver = {
1331 .driver = {
1332 .name = "tegra-dc",
1333 .owner = THIS_MODULE,
1334 .of_match_table = tegra_dc_of_match,
1335 },
1336 .probe = tegra_dc_probe,
1337 .remove = tegra_dc_remove,
1338};
Linux kernel - Deliverables
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