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drm/tegra: Implement VBLANK support
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15
16#include <mach/clk.h>
17
18#include "drm.h"
19#include "dc.h"
20
f34bc787
TR		 21struct tegra_plane {
22 struct drm_plane base;
23 unsigned int index;
d8f4a9ed
TR		 24};
25
f34bc787
TR		 26static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
27{
28 return container_of(plane, struct tegra_plane, base);
29}
30
31static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
32 struct drm_framebuffer *fb, int crtc_x,
33 int crtc_y, unsigned int crtc_w,
34 unsigned int crtc_h, uint32_t src_x,
35 uint32_t src_y, uint32_t src_w, uint32_t src_h)
36{
37 struct tegra_plane *p = to_tegra_plane(plane);
38 struct tegra_dc *dc = to_tegra_dc(crtc);
39 struct tegra_dc_window window;
40 unsigned int i;
41
42 memset(&window, 0, sizeof(window));
43 window.src.x = src_x >> 16;
44 window.src.y = src_y >> 16;
45 window.src.w = src_w >> 16;
46 window.src.h = src_h >> 16;
47 window.dst.x = crtc_x;
48 window.dst.y = crtc_y;
49 window.dst.w = crtc_w;
50 window.dst.h = crtc_h;
51 window.format = tegra_dc_format(fb->pixel_format);
52 window.bits_per_pixel = fb->bits_per_pixel;
53
54 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
55 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
56
57 window.base[i] = gem->paddr + fb->offsets[i];
58
59 /*
60 * Tegra doesn't support different strides for U and V planes
61 * so we display a warning if the user tries to display a
62 * framebuffer with such a configuration.
63 */
64 if (i >= 2) {
65 if (fb->pitches[i] != window.stride[1])
66 DRM_ERROR("unsupported UV-plane configuration\n");
67 } else {
68 window.stride[i] = fb->pitches[i];
69 }
70 }
71
72 return tegra_dc_setup_window(dc, p->index, &window);
73}
74
75static int tegra_plane_disable(struct drm_plane *plane)
76{
77 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
78 struct tegra_plane *p = to_tegra_plane(plane);
79 unsigned long value;
80
81 value = WINDOW_A_SELECT << p->index;
82 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
83
84 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
85 value &= ~WIN_ENABLE;
86 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
87
88 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
89 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
90
91 return 0;
92}
93
94static void tegra_plane_destroy(struct drm_plane *plane)
95{
96 tegra_plane_disable(plane);
97 drm_plane_cleanup(plane);
98}
99
100static const struct drm_plane_funcs tegra_plane_funcs = {
101 .update_plane = tegra_plane_update,
102 .disable_plane = tegra_plane_disable,
103 .destroy = tegra_plane_destroy,
104};
105
106static const uint32_t plane_formats[] = {
107 DRM_FORMAT_XRGB8888,
108 DRM_FORMAT_UYVY,
109 DRM_FORMAT_YUV420,
110 DRM_FORMAT_YUV422,
111};
112
113static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
114{
115 unsigned int i;
116 int err = 0;
117
118 for (i = 0; i < 2; i++) {
119 struct tegra_plane *plane;
120
121 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
122 if (!plane)
123 return -ENOMEM;
124
125 plane->index = 1 + i;
126
127 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
128 &tegra_plane_funcs, plane_formats,
129 ARRAY_SIZE(plane_formats), false);
130 if (err < 0)
131 return err;
132 }
133
134 return 0;
135}
136
23fb4740
TR		 137static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
138 struct drm_framebuffer *fb)
139{
140 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, 0);
141 unsigned long value;
142
143 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
144
145 value = fb->offsets[0] + y * fb->pitches[0] +
146 x * fb->bits_per_pixel / 8;
147
148 tegra_dc_writel(dc, gem->paddr + value, DC_WINBUF_START_ADDR);
149 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
150
151 value = GENERAL_UPDATE | WIN_A_UPDATE;
152 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
153
154 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
155 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
156
157 return 0;
158}
159
6e5ff998
TR		 160void tegra_dc_enable_vblank(struct tegra_dc *dc)
161{
162 unsigned long value, flags;
163
164 spin_lock_irqsave(&dc->lock, flags);
165
166 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
167 value |= VBLANK_INT;
168 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
169
170 spin_unlock_irqrestore(&dc->lock, flags);
171}
172
173void tegra_dc_disable_vblank(struct tegra_dc *dc)
174{
175 unsigned long value, flags;
176
177 spin_lock_irqsave(&dc->lock, flags);
178
179 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
180 value &= ~VBLANK_INT;
181 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
182
183 spin_unlock_irqrestore(&dc->lock, flags);
184}
185
d8f4a9ed
TR		 186static const struct drm_crtc_funcs tegra_crtc_funcs = {
187 .set_config = drm_crtc_helper_set_config,
188 .destroy = drm_crtc_cleanup,
189};
190
f34bc787 191static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 192{
f34bc787
TR		 193 struct drm_device *drm = crtc->dev;
194 struct drm_plane *plane;
195
196 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
197 if (plane->crtc == crtc) {
198 tegra_plane_disable(plane);
199 plane->crtc = NULL;
200
201 if (plane->fb) {
202 drm_framebuffer_unreference(plane->fb);
203 plane->fb = NULL;
204 }
205 }
206 }
d8f4a9ed
TR		 207}
208
209static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
210 const struct drm_display_mode *mode,
211 struct drm_display_mode *adjusted)
212{
213 return true;
214}
215
f34bc787 216static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 217 unsigned int bpp)
218{
219 fixed20_12 outf = dfixed_init(out);
f34bc787 220 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 221 u32 dda_inc;
222 int max;
223
224 if (v)
225 max = 15;
226 else {
227 switch (bpp) {
228 case 2:
229 max = 8;
230 break;
231
232 default:
233 WARN_ON_ONCE(1);
234 /* fallthrough */
235 case 4:
236 max = 4;
237 break;
238 }
239 }
240
241 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
242 inf.full -= dfixed_const(1);
243
244 dda_inc = dfixed_div(inf, outf);
245 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
246
247 return dda_inc;
248}
249
f34bc787 250static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 251{
f34bc787
TR		 252 fixed20_12 inf = dfixed_init(in);
253 return dfixed_frac(inf);
d8f4a9ed
TR		 254}
255
256static int tegra_dc_set_timings(struct tegra_dc *dc,
257 struct drm_display_mode *mode)
258{
259 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
260 unsigned int h_ref_to_sync = 0;
261 unsigned int v_ref_to_sync = 0;
262 unsigned long value;
263
264 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
265
266 value = (v_ref_to_sync << 16) | h_ref_to_sync;
267 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
268
269 value = ((mode->vsync_end - mode->vsync_start) << 16) |
270 ((mode->hsync_end - mode->hsync_start) << 0);
271 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
272
d8f4a9ed
TR		 273 value = ((mode->vtotal - mode->vsync_end) << 16) |
274 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 275 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
276
277 value = ((mode->vsync_start - mode->vdisplay) << 16) |
278 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 279 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
280
281 value = (mode->vdisplay << 16) | mode->hdisplay;
282 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
283
284 return 0;
285}
286
287static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
288 struct drm_display_mode *mode,
289 unsigned long *div)
290{
291 unsigned long pclk = mode->clock * 1000, rate;
292 struct tegra_dc *dc = to_tegra_dc(crtc);
293 struct tegra_output *output = NULL;
294 struct drm_encoder *encoder;
295 long err;
296
297 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
298 if (encoder->crtc == crtc) {
299 output = encoder_to_output(encoder);
300 break;
301 }
302
303 if (!output)
304 return -ENODEV;
305
306 /*
307 * This assumes that the display controller will divide its parent
308 * clock by 2 to generate the pixel clock.
309 */
310 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
311 if (err < 0) {
312 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
313 return err;
314 }
315
316 rate = clk_get_rate(dc->clk);
317 *div = (rate * 2 / pclk) - 2;
318
319 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
320
321 return 0;
322}
323
f34bc787
TR		 324static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
325{
326 switch (format) {
327 case WIN_COLOR_DEPTH_YCbCr422:
328 case WIN_COLOR_DEPTH_YUV422:
329 if (planar)
330 *planar = false;
331
332 return true;
333
334 case WIN_COLOR_DEPTH_YCbCr420P:
335 case WIN_COLOR_DEPTH_YUV420P:
336 case WIN_COLOR_DEPTH_YCbCr422P:
337 case WIN_COLOR_DEPTH_YUV422P:
338 case WIN_COLOR_DEPTH_YCbCr422R:
339 case WIN_COLOR_DEPTH_YUV422R:
340 case WIN_COLOR_DEPTH_YCbCr422RA:
341 case WIN_COLOR_DEPTH_YUV422RA:
342 if (planar)
343 *planar = true;
344
345 return true;
346 }
347
348 return false;
349}
350
351int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
352 const struct tegra_dc_window *window)
353{
354 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
355 unsigned long value;
356 bool yuv, planar;
357
358 /*
359 * For YUV planar modes, the number of bytes per pixel takes into
360 * account only the luma component and therefore is 1.
361 */
362 yuv = tegra_dc_format_is_yuv(window->format, &planar);
363 if (!yuv)
364 bpp = window->bits_per_pixel / 8;
365 else
366 bpp = planar ? 1 : 2;
367
368 value = WINDOW_A_SELECT << index;
369 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
370
371 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
372 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
373
374 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
375 tegra_dc_writel(dc, value, DC_WIN_POSITION);
376
377 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
378 tegra_dc_writel(dc, value, DC_WIN_SIZE);
379
380 h_offset = window->src.x * bpp;
381 v_offset = window->src.y;
382 h_size = window->src.w * bpp;
383 v_size = window->src.h;
384
385 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
386 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
387
388 /*
389 * For DDA computations the number of bytes per pixel for YUV planar
390 * modes needs to take into account all Y, U and V components.
391 */
392 if (yuv && planar)
393 bpp = 2;
394
395 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
396 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
397
398 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
399 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
400
401 h_dda = compute_initial_dda(window->src.x);
402 v_dda = compute_initial_dda(window->src.y);
403
404 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
405 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
406
407 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
408 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
409
410 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
411
412 if (yuv && planar) {
413 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
414 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
415 value = window->stride[1] << 16 | window->stride[0];
416 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
417 } else {
418 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
419 }
420
421 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
422 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
423
424 value = WIN_ENABLE;
425
426 if (yuv) {
427 /* setup default colorspace conversion coefficients */
428 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
429 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
430 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
431 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
432 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
433 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
434 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
435 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
436
437 value |= CSC_ENABLE;
438 } else if (bpp < 24) {
439 value |= COLOR_EXPAND;
440 }
441
442 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
443
444 /*
445 * Disable blending and assume Window A is the bottom-most window,
446 * Window C is the top-most window and Window B is in the middle.
447 */
448 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
449 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
450
451 switch (index) {
452 case 0:
453 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
454 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
455 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
456 break;
457
458 case 1:
459 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
460 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
461 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
462 break;
463
464 case 2:
465 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
466 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
467 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
468 break;
469 }
470
471 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
472 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
473
474 return 0;
475}
476
477unsigned int tegra_dc_format(uint32_t format)
478{
479 switch (format) {
480 case DRM_FORMAT_XRGB8888:
481 return WIN_COLOR_DEPTH_B8G8R8A8;
482
483 case DRM_FORMAT_RGB565:
484 return WIN_COLOR_DEPTH_B5G6R5;
485
486 case DRM_FORMAT_UYVY:
487 return WIN_COLOR_DEPTH_YCbCr422;
488
489 case DRM_FORMAT_YUV420:
490 return WIN_COLOR_DEPTH_YCbCr420P;
491
492 case DRM_FORMAT_YUV422:
493 return WIN_COLOR_DEPTH_YCbCr422P;
494
495 default:
496 break;
497 }
498
499 WARN(1, "unsupported pixel format %u, using default\n", format);
500 return WIN_COLOR_DEPTH_B8G8R8A8;
501}
502
d8f4a9ed
TR		 503static int tegra_crtc_mode_set(struct drm_crtc *crtc,
504 struct drm_display_mode *mode,
505 struct drm_display_mode *adjusted,
506 int x, int y, struct drm_framebuffer *old_fb)
507{
894752bb 508 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(crtc->fb, 0);
d8f4a9ed 509 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 510 struct tegra_dc_window window;
d8f4a9ed
TR		 511 unsigned long div, value;
512 int err;
513
6e5ff998
TR		 514 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
515
d8f4a9ed
TR		 516 err = tegra_crtc_setup_clk(crtc, mode, &div);
517 if (err) {
518 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
519 return err;
520 }
521
522 /* program display mode */
523 tegra_dc_set_timings(dc, mode);
524
525 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
526 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
527
528 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
529 value &= ~LVS_OUTPUT_POLARITY_LOW;
530 value &= ~LHS_OUTPUT_POLARITY_LOW;
531 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
532
533 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
534 DISP_ORDER_RED_BLUE;
535 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
536
537 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
538
539 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
540 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
541
542 /* setup window parameters */
f34bc787
TR		 543 memset(&window, 0, sizeof(window));
544 window.src.x = 0;
545 window.src.y = 0;
546 window.src.w = mode->hdisplay;
547 window.src.h = mode->vdisplay;
548 window.dst.x = 0;
549 window.dst.y = 0;
550 window.dst.w = mode->hdisplay;
551 window.dst.h = mode->vdisplay;
552 window.format = tegra_dc_format(crtc->fb->pixel_format);
553 window.bits_per_pixel = crtc->fb->bits_per_pixel;
554 window.stride[0] = crtc->fb->pitches[0];
555 window.base[0] = gem->paddr;
556
557 err = tegra_dc_setup_window(dc, 0, &window);
558 if (err < 0)
559 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed
TR		 560
561 return 0;
562}
563
23fb4740
TR		 564static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
565 struct drm_framebuffer *old_fb)
566{
567 struct tegra_dc *dc = to_tegra_dc(crtc);
568
569 return tegra_dc_set_base(dc, x, y, crtc->fb);
570}
571
d8f4a9ed
TR		 572static void tegra_crtc_prepare(struct drm_crtc *crtc)
573{
574 struct tegra_dc *dc = to_tegra_dc(crtc);
575 unsigned int syncpt;
576 unsigned long value;
577
578 /* hardware initialization */
579 tegra_periph_reset_deassert(dc->clk);
580 usleep_range(10000, 20000);
581
582 if (dc->pipe)
583 syncpt = SYNCPT_VBLANK1;
584 else
585 syncpt = SYNCPT_VBLANK0;
586
587 /* initialize display controller */
588 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
589 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
590
591 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
592 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
593
594 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
595 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
596 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
597
598 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
599 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
600 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
601
602 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
603 value |= DISP_CTRL_MODE_C_DISPLAY;
604 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
605
606 /* initialize timer */
607 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
608 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
609 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
610
611 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
612 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
613 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
614
d8f4a9ed
TR		 615 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
616 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 617
618 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
619 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 620}
621
622static void tegra_crtc_commit(struct drm_crtc *crtc)
623{
624 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 625 unsigned long value;
626
6e5ff998
TR		 627 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ |
628 GENERAL_UPDATE | WIN_A_UPDATE;
d8f4a9ed 629
6e5ff998 630 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 631
6e5ff998 632 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 633}
634
635static void tegra_crtc_load_lut(struct drm_crtc *crtc)
636{
637}
638
639static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 640 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 641 .mode_fixup = tegra_crtc_mode_fixup,
642 .mode_set = tegra_crtc_mode_set,
23fb4740 643 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 644 .prepare = tegra_crtc_prepare,
645 .commit = tegra_crtc_commit,
646 .load_lut = tegra_crtc_load_lut,
647};
648
6e5ff998 649static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 650{
651 struct tegra_dc *dc = data;
652 unsigned long status;
653
654 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
655 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
656
657 if (status & FRAME_END_INT) {
658 /*
659 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
660 */
661 }
662
663 if (status & VBLANK_INT) {
664 /*
665 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
666 */
667 drm_handle_vblank(dc->base.dev, dc->pipe);
668 }
669
670 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
671 /*
672 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
673 */
674 }
675
676 return IRQ_HANDLED;
677}
678
679static int tegra_dc_show_regs(struct seq_file *s, void *data)
680{
681 struct drm_info_node *node = s->private;
682 struct tegra_dc *dc = node->info_ent->data;
683
684#define DUMP_REG(name) \
685 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
686 tegra_dc_readl(dc, name))
687
688 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
689 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
690 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
691 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
692 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
693 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
694 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
695 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
696 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
697 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
698 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
699 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
700 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
701 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
702 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
703 DUMP_REG(DC_CMD_SIGNAL_RAISE);
704 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
705 DUMP_REG(DC_CMD_INT_STATUS);
706 DUMP_REG(DC_CMD_INT_MASK);
707 DUMP_REG(DC_CMD_INT_ENABLE);
708 DUMP_REG(DC_CMD_INT_TYPE);
709 DUMP_REG(DC_CMD_INT_POLARITY);
710 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
711 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
712 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
713 DUMP_REG(DC_CMD_STATE_ACCESS);
714 DUMP_REG(DC_CMD_STATE_CONTROL);
715 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
716 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
717 DUMP_REG(DC_COM_CRC_CONTROL);
718 DUMP_REG(DC_COM_CRC_CHECKSUM);
719 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
720 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
721 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
722 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
723 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
724 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
725 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
726 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
727 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
728 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
729 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
730 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
731 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
732 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
733 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
734 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
735 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
736 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
737 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
738 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
739 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
740 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
741 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
742 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
743 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
744 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
745 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
746 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
747 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
748 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
749 DUMP_REG(DC_COM_SPI_CONTROL);
750 DUMP_REG(DC_COM_SPI_START_BYTE);
751 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
752 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
753 DUMP_REG(DC_COM_HSPI_CS_DC);
754 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
755 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
756 DUMP_REG(DC_COM_GPIO_CTRL);
757 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
758 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
759 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
760 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
761 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
762 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
763 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
764 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
765 DUMP_REG(DC_DISP_REF_TO_SYNC);
766 DUMP_REG(DC_DISP_SYNC_WIDTH);
767 DUMP_REG(DC_DISP_BACK_PORCH);
768 DUMP_REG(DC_DISP_ACTIVE);
769 DUMP_REG(DC_DISP_FRONT_PORCH);
770 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
771 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
772 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
773 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
774 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
775 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
776 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
777 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
778 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
779 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
780 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
781 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
782 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
783 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
784 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
785 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
786 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
787 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
788 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
789 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
790 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
791 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
792 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
793 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
794 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
795 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
796 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
797 DUMP_REG(DC_DISP_M0_CONTROL);
798 DUMP_REG(DC_DISP_M1_CONTROL);
799 DUMP_REG(DC_DISP_DI_CONTROL);
800 DUMP_REG(DC_DISP_PP_CONTROL);
801 DUMP_REG(DC_DISP_PP_SELECT_A);
802 DUMP_REG(DC_DISP_PP_SELECT_B);
803 DUMP_REG(DC_DISP_PP_SELECT_C);
804 DUMP_REG(DC_DISP_PP_SELECT_D);
805 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
806 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
807 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
808 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
809 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
810 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
811 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
812 DUMP_REG(DC_DISP_BORDER_COLOR);
813 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
814 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
815 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
816 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
817 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
818 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
819 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
820 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
821 DUMP_REG(DC_DISP_CURSOR_POSITION);
822 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
823 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
824 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
825 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
826 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
827 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
828 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
829 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
830 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
831 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
832 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
833 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
834 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
835 DUMP_REG(DC_DISP_SD_CONTROL);
836 DUMP_REG(DC_DISP_SD_CSC_COEFF);
837 DUMP_REG(DC_DISP_SD_LUT(0));
838 DUMP_REG(DC_DISP_SD_LUT(1));
839 DUMP_REG(DC_DISP_SD_LUT(2));
840 DUMP_REG(DC_DISP_SD_LUT(3));
841 DUMP_REG(DC_DISP_SD_LUT(4));
842 DUMP_REG(DC_DISP_SD_LUT(5));
843 DUMP_REG(DC_DISP_SD_LUT(6));
844 DUMP_REG(DC_DISP_SD_LUT(7));
845 DUMP_REG(DC_DISP_SD_LUT(8));
846 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
847 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
848 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
849 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
850 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
851 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
852 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
853 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
854 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
855 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
856 DUMP_REG(DC_DISP_SD_BL_TF(0));
857 DUMP_REG(DC_DISP_SD_BL_TF(1));
858 DUMP_REG(DC_DISP_SD_BL_TF(2));
859 DUMP_REG(DC_DISP_SD_BL_TF(3));
860 DUMP_REG(DC_DISP_SD_BL_CONTROL);
861 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
862 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
863 DUMP_REG(DC_WIN_WIN_OPTIONS);
864 DUMP_REG(DC_WIN_BYTE_SWAP);
865 DUMP_REG(DC_WIN_BUFFER_CONTROL);
866 DUMP_REG(DC_WIN_COLOR_DEPTH);
867 DUMP_REG(DC_WIN_POSITION);
868 DUMP_REG(DC_WIN_SIZE);
869 DUMP_REG(DC_WIN_PRESCALED_SIZE);
870 DUMP_REG(DC_WIN_H_INITIAL_DDA);
871 DUMP_REG(DC_WIN_V_INITIAL_DDA);
872 DUMP_REG(DC_WIN_DDA_INC);
873 DUMP_REG(DC_WIN_LINE_STRIDE);
874 DUMP_REG(DC_WIN_BUF_STRIDE);
875 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
876 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
877 DUMP_REG(DC_WIN_DV_CONTROL);
878 DUMP_REG(DC_WIN_BLEND_NOKEY);
879 DUMP_REG(DC_WIN_BLEND_1WIN);
880 DUMP_REG(DC_WIN_BLEND_2WIN_X);
881 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 882 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 883 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
884 DUMP_REG(DC_WINBUF_START_ADDR);
885 DUMP_REG(DC_WINBUF_START_ADDR_NS);
886 DUMP_REG(DC_WINBUF_START_ADDR_U);
887 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
888 DUMP_REG(DC_WINBUF_START_ADDR_V);
889 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
890 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
891 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
892 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
893 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
894 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
895 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
896 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
897 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
898
899#undef DUMP_REG
900
901 return 0;
902}
903
904static struct drm_info_list debugfs_files[] = {
905 { "regs", tegra_dc_show_regs, 0, NULL },
906};
907
908static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
909{
910 unsigned int i;
911 char *name;
912 int err;
913
914 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
915 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
916 kfree(name);
917
918 if (!dc->debugfs)
919 return -ENOMEM;
920
921 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
922 GFP_KERNEL);
923 if (!dc->debugfs_files) {
924 err = -ENOMEM;
925 goto remove;
926 }
927
928 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
929 dc->debugfs_files[i].data = dc;
930
931 err = drm_debugfs_create_files(dc->debugfs_files,
932 ARRAY_SIZE(debugfs_files),
933 dc->debugfs, minor);
934 if (err < 0)
935 goto free;
936
937 dc->minor = minor;
938
939 return 0;
940
941free:
942 kfree(dc->debugfs_files);
943 dc->debugfs_files = NULL;
944remove:
945 debugfs_remove(dc->debugfs);
946 dc->debugfs = NULL;
947
948 return err;
949}
950
951static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
952{
953 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
954 dc->minor);
955 dc->minor = NULL;
956
957 kfree(dc->debugfs_files);
958 dc->debugfs_files = NULL;
959
960 debugfs_remove(dc->debugfs);
961 dc->debugfs = NULL;
962
963 return 0;
964}
965
966static int tegra_dc_drm_init(struct host1x_client *client,
967 struct drm_device *drm)
968{
969 struct tegra_dc *dc = host1x_client_to_dc(client);
970 int err;
971
972 dc->pipe = drm->mode_config.num_crtc;
973
974 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
975 drm_mode_crtc_set_gamma_size(&dc->base, 256);
976 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
977
978 err = tegra_dc_rgb_init(drm, dc);
979 if (err < 0 && err != -ENODEV) {
980 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
981 return err;
982 }
983
f34bc787
TR		 984 err = tegra_dc_add_planes(drm, dc);
985 if (err < 0)
986 return err;
987
d8f4a9ed
TR		 988 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
989 err = tegra_dc_debugfs_init(dc, drm->primary);
990 if (err < 0)
991 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
992 }
993
6e5ff998 994 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 995 dev_name(dc->dev), dc);
996 if (err < 0) {
997 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
998 err);
999 return err;
1000 }
1001
1002 return 0;
1003}
1004
1005static int tegra_dc_drm_exit(struct host1x_client *client)
1006{
1007 struct tegra_dc *dc = host1x_client_to_dc(client);
1008 int err;
1009
1010 devm_free_irq(dc->dev, dc->irq, dc);
1011
1012 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1013 err = tegra_dc_debugfs_exit(dc);
1014 if (err < 0)
1015 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1016 }
1017
1018 err = tegra_dc_rgb_exit(dc);
1019 if (err) {
1020 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1021 return err;
1022 }
1023
1024 return 0;
1025}
1026
1027static const struct host1x_client_ops dc_client_ops = {
1028 .drm_init = tegra_dc_drm_init,
1029 .drm_exit = tegra_dc_drm_exit,
1030};
1031
1032static int tegra_dc_probe(struct platform_device *pdev)
1033{
1034 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1035 struct resource *regs;
1036 struct tegra_dc *dc;
1037 int err;
1038
1039 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1040 if (!dc)
1041 return -ENOMEM;
1042
6e5ff998 1043 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1044 INIT_LIST_HEAD(&dc->list);
1045 dc->dev = &pdev->dev;
1046
1047 dc->clk = devm_clk_get(&pdev->dev, NULL);
1048 if (IS_ERR(dc->clk)) {
1049 dev_err(&pdev->dev, "failed to get clock\n");
1050 return PTR_ERR(dc->clk);
1051 }
1052
1053 err = clk_prepare_enable(dc->clk);
1054 if (err < 0)
1055 return err;
1056
1057 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1058 if (!regs) {
1059 dev_err(&pdev->dev, "failed to get registers\n");
1060 return -ENXIO;
1061 }
1062
1063 dc->regs = devm_request_and_ioremap(&pdev->dev, regs);
1064 if (!dc->regs) {
1065 dev_err(&pdev->dev, "failed to remap registers\n");
1066 return -ENXIO;
1067 }
1068
1069 dc->irq = platform_get_irq(pdev, 0);
1070 if (dc->irq < 0) {
1071 dev_err(&pdev->dev, "failed to get IRQ\n");
1072 return -ENXIO;
1073 }
1074
1075 INIT_LIST_HEAD(&dc->client.list);
1076 dc->client.ops = &dc_client_ops;
1077 dc->client.dev = &pdev->dev;
1078
1079 err = tegra_dc_rgb_probe(dc);
1080 if (err < 0 && err != -ENODEV) {
1081 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1082 return err;
1083 }
1084
1085 err = host1x_register_client(host1x, &dc->client);
1086 if (err < 0) {
1087 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1088 err);
1089 return err;
1090 }
1091
1092 platform_set_drvdata(pdev, dc);
1093
1094 return 0;
1095}
1096
1097static int tegra_dc_remove(struct platform_device *pdev)
1098{
1099 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1100 struct tegra_dc *dc = platform_get_drvdata(pdev);
1101 int err;
1102
1103 err = host1x_unregister_client(host1x, &dc->client);
1104 if (err < 0) {
1105 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1106 err);
1107 return err;
1108 }
1109
1110 clk_disable_unprepare(dc->clk);
1111
1112 return 0;
1113}
1114
1115static struct of_device_id tegra_dc_of_match[] = {
219e8153 1116 { .compatible = "nvidia,tegra30-dc", },
d8f4a9ed
TR		 1117 { .compatible = "nvidia,tegra20-dc", },
1118 { },
1119};
1120
1121struct platform_driver tegra_dc_driver = {
1122 .driver = {
1123 .name = "tegra-dc",
1124 .owner = THIS_MODULE,
1125 .of_match_table = tegra_dc_of_match,
1126 },
1127 .probe = tegra_dc_probe,
1128 .remove = tegra_dc_remove,
1129};
Linux kernel - Deliverables
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