Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
9eb9b220 | 11 | #include <linux/debugfs.h> |
df06b759 | 12 | #include <linux/iommu.h> |
ca48080a | 13 | #include <linux/reset.h> |
d8f4a9ed | 14 | |
9c012700 TR |
15 | #include <soc/tegra/pmc.h> |
16 | ||
de2ba664 AM |
17 | #include "dc.h" |
18 | #include "drm.h" | |
19 | #include "gem.h" | |
d8f4a9ed | 20 | |
9d44189f | 21 | #include <drm/drm_atomic.h> |
4aa3df71 | 22 | #include <drm/drm_atomic_helper.h> |
3cb9ae4f DV |
23 | #include <drm/drm_plane_helper.h> |
24 | ||
8620fc62 | 25 | struct tegra_dc_soc_info { |
42d0659b | 26 | bool supports_border_color; |
8620fc62 | 27 | bool supports_interlacing; |
e687651b | 28 | bool supports_cursor; |
c134f019 | 29 | bool supports_block_linear; |
d1f3e1e0 | 30 | unsigned int pitch_align; |
9c012700 | 31 | bool has_powergate; |
8620fc62 TR |
32 | }; |
33 | ||
f34bc787 TR |
34 | struct tegra_plane { |
35 | struct drm_plane base; | |
36 | unsigned int index; | |
d8f4a9ed TR |
37 | }; |
38 | ||
f34bc787 TR |
39 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
40 | { | |
41 | return container_of(plane, struct tegra_plane, base); | |
42 | } | |
43 | ||
ca915b10 TR |
44 | struct tegra_dc_state { |
45 | struct drm_crtc_state base; | |
46 | ||
47 | struct clk *clk; | |
48 | unsigned long pclk; | |
49 | unsigned int div; | |
50 | }; | |
51 | ||
52 | static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) | |
53 | { | |
54 | if (state) | |
55 | return container_of(state, struct tegra_dc_state, base); | |
56 | ||
57 | return NULL; | |
58 | } | |
59 | ||
205d48ed TR |
60 | static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index) |
61 | { | |
62 | u32 value = WIN_A_ACT_REQ << index; | |
63 | ||
64 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); | |
65 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); | |
66 | } | |
67 | ||
68 | static void tegra_dc_cursor_commit(struct tegra_dc *dc) | |
69 | { | |
70 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
71 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); | |
72 | } | |
73 | ||
86df256f TR |
74 | /* |
75 | * Reads the active copy of a register. This takes the dc->lock spinlock to | |
76 | * prevent races with the VBLANK processing which also needs access to the | |
77 | * active copy of some registers. | |
78 | */ | |
79 | static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) | |
80 | { | |
81 | unsigned long flags; | |
82 | u32 value; | |
83 | ||
84 | spin_lock_irqsave(&dc->lock, flags); | |
85 | ||
86 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | |
87 | value = tegra_dc_readl(dc, offset); | |
88 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
89 | ||
90 | spin_unlock_irqrestore(&dc->lock, flags); | |
91 | return value; | |
92 | } | |
93 | ||
d700ba7a TR |
94 | /* |
95 | * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the | |
96 | * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. | |
97 | * Latching happens mmediately if the display controller is in STOP mode or | |
98 | * on the next frame boundary otherwise. | |
99 | * | |
100 | * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The | |
101 | * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits | |
102 | * are written. When the *_ACT_REQ bits are written, the ARM copy is latched | |
103 | * into the ACTIVE copy, either immediately if the display controller is in | |
104 | * STOP mode, or at the next frame boundary otherwise. | |
105 | */ | |
62b9e063 | 106 | void tegra_dc_commit(struct tegra_dc *dc) |
205d48ed TR |
107 | { |
108 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
109 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
110 | } | |
111 | ||
10288eea TR |
112 | static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap) |
113 | { | |
114 | /* assume no swapping of fetched data */ | |
115 | if (swap) | |
116 | *swap = BYTE_SWAP_NOSWAP; | |
117 | ||
118 | switch (format) { | |
119 | case DRM_FORMAT_XBGR8888: | |
120 | return WIN_COLOR_DEPTH_R8G8B8A8; | |
121 | ||
122 | case DRM_FORMAT_XRGB8888: | |
123 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
124 | ||
125 | case DRM_FORMAT_RGB565: | |
126 | return WIN_COLOR_DEPTH_B5G6R5; | |
127 | ||
128 | case DRM_FORMAT_UYVY: | |
129 | return WIN_COLOR_DEPTH_YCbCr422; | |
130 | ||
131 | case DRM_FORMAT_YUYV: | |
132 | if (swap) | |
133 | *swap = BYTE_SWAP_SWAP2; | |
134 | ||
135 | return WIN_COLOR_DEPTH_YCbCr422; | |
136 | ||
137 | case DRM_FORMAT_YUV420: | |
138 | return WIN_COLOR_DEPTH_YCbCr420P; | |
139 | ||
140 | case DRM_FORMAT_YUV422: | |
141 | return WIN_COLOR_DEPTH_YCbCr422P; | |
142 | ||
143 | default: | |
144 | break; | |
145 | } | |
146 | ||
147 | WARN(1, "unsupported pixel format %u, using default\n", format); | |
148 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
149 | } | |
150 | ||
151 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) | |
152 | { | |
153 | switch (format) { | |
154 | case WIN_COLOR_DEPTH_YCbCr422: | |
155 | case WIN_COLOR_DEPTH_YUV422: | |
156 | if (planar) | |
157 | *planar = false; | |
158 | ||
159 | return true; | |
160 | ||
161 | case WIN_COLOR_DEPTH_YCbCr420P: | |
162 | case WIN_COLOR_DEPTH_YUV420P: | |
163 | case WIN_COLOR_DEPTH_YCbCr422P: | |
164 | case WIN_COLOR_DEPTH_YUV422P: | |
165 | case WIN_COLOR_DEPTH_YCbCr422R: | |
166 | case WIN_COLOR_DEPTH_YUV422R: | |
167 | case WIN_COLOR_DEPTH_YCbCr422RA: | |
168 | case WIN_COLOR_DEPTH_YUV422RA: | |
169 | if (planar) | |
170 | *planar = true; | |
171 | ||
172 | return true; | |
173 | } | |
174 | ||
fb35c6b6 TR |
175 | if (planar) |
176 | *planar = false; | |
177 | ||
10288eea TR |
178 | return false; |
179 | } | |
180 | ||
181 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, | |
182 | unsigned int bpp) | |
183 | { | |
184 | fixed20_12 outf = dfixed_init(out); | |
185 | fixed20_12 inf = dfixed_init(in); | |
186 | u32 dda_inc; | |
187 | int max; | |
188 | ||
189 | if (v) | |
190 | max = 15; | |
191 | else { | |
192 | switch (bpp) { | |
193 | case 2: | |
194 | max = 8; | |
195 | break; | |
196 | ||
197 | default: | |
198 | WARN_ON_ONCE(1); | |
199 | /* fallthrough */ | |
200 | case 4: | |
201 | max = 4; | |
202 | break; | |
203 | } | |
204 | } | |
205 | ||
206 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); | |
207 | inf.full -= dfixed_const(1); | |
208 | ||
209 | dda_inc = dfixed_div(inf, outf); | |
210 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); | |
211 | ||
212 | return dda_inc; | |
213 | } | |
214 | ||
215 | static inline u32 compute_initial_dda(unsigned int in) | |
216 | { | |
217 | fixed20_12 inf = dfixed_init(in); | |
218 | return dfixed_frac(inf); | |
219 | } | |
220 | ||
4aa3df71 TR |
221 | static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
222 | const struct tegra_dc_window *window) | |
10288eea TR |
223 | { |
224 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | |
93396d0f | 225 | unsigned long value, flags; |
10288eea TR |
226 | bool yuv, planar; |
227 | ||
228 | /* | |
229 | * For YUV planar modes, the number of bytes per pixel takes into | |
230 | * account only the luma component and therefore is 1. | |
231 | */ | |
232 | yuv = tegra_dc_format_is_yuv(window->format, &planar); | |
233 | if (!yuv) | |
234 | bpp = window->bits_per_pixel / 8; | |
235 | else | |
236 | bpp = planar ? 1 : 2; | |
237 | ||
93396d0f SP |
238 | spin_lock_irqsave(&dc->lock, flags); |
239 | ||
10288eea TR |
240 | value = WINDOW_A_SELECT << index; |
241 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
242 | ||
243 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); | |
244 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); | |
245 | ||
246 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); | |
247 | tegra_dc_writel(dc, value, DC_WIN_POSITION); | |
248 | ||
249 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); | |
250 | tegra_dc_writel(dc, value, DC_WIN_SIZE); | |
251 | ||
252 | h_offset = window->src.x * bpp; | |
253 | v_offset = window->src.y; | |
254 | h_size = window->src.w * bpp; | |
255 | v_size = window->src.h; | |
256 | ||
257 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); | |
258 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); | |
259 | ||
260 | /* | |
261 | * For DDA computations the number of bytes per pixel for YUV planar | |
262 | * modes needs to take into account all Y, U and V components. | |
263 | */ | |
264 | if (yuv && planar) | |
265 | bpp = 2; | |
266 | ||
267 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); | |
268 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); | |
269 | ||
270 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); | |
271 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); | |
272 | ||
273 | h_dda = compute_initial_dda(window->src.x); | |
274 | v_dda = compute_initial_dda(window->src.y); | |
275 | ||
276 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); | |
277 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); | |
278 | ||
279 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); | |
280 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); | |
281 | ||
282 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); | |
283 | ||
284 | if (yuv && planar) { | |
285 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); | |
286 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); | |
287 | value = window->stride[1] << 16 | window->stride[0]; | |
288 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); | |
289 | } else { | |
290 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); | |
291 | } | |
292 | ||
293 | if (window->bottom_up) | |
294 | v_offset += window->src.h - 1; | |
295 | ||
296 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
297 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
298 | ||
c134f019 TR |
299 | if (dc->soc->supports_block_linear) { |
300 | unsigned long height = window->tiling.value; | |
301 | ||
302 | switch (window->tiling.mode) { | |
303 | case TEGRA_BO_TILING_MODE_PITCH: | |
304 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
305 | break; | |
306 | ||
307 | case TEGRA_BO_TILING_MODE_TILED: | |
308 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
309 | break; | |
310 | ||
311 | case TEGRA_BO_TILING_MODE_BLOCK: | |
312 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
313 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
314 | break; | |
315 | } | |
316 | ||
317 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
10288eea | 318 | } else { |
c134f019 TR |
319 | switch (window->tiling.mode) { |
320 | case TEGRA_BO_TILING_MODE_PITCH: | |
321 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
322 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
323 | break; | |
10288eea | 324 | |
c134f019 TR |
325 | case TEGRA_BO_TILING_MODE_TILED: |
326 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
327 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
328 | break; | |
329 | ||
330 | case TEGRA_BO_TILING_MODE_BLOCK: | |
4aa3df71 TR |
331 | /* |
332 | * No need to handle this here because ->atomic_check | |
333 | * will already have filtered it out. | |
334 | */ | |
335 | break; | |
c134f019 TR |
336 | } |
337 | ||
338 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
339 | } | |
10288eea TR |
340 | |
341 | value = WIN_ENABLE; | |
342 | ||
343 | if (yuv) { | |
344 | /* setup default colorspace conversion coefficients */ | |
345 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); | |
346 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); | |
347 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); | |
348 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); | |
349 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); | |
350 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); | |
351 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); | |
352 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); | |
353 | ||
354 | value |= CSC_ENABLE; | |
355 | } else if (window->bits_per_pixel < 24) { | |
356 | value |= COLOR_EXPAND; | |
357 | } | |
358 | ||
359 | if (window->bottom_up) | |
360 | value |= V_DIRECTION; | |
361 | ||
362 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
363 | ||
364 | /* | |
365 | * Disable blending and assume Window A is the bottom-most window, | |
366 | * Window C is the top-most window and Window B is in the middle. | |
367 | */ | |
368 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); | |
369 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); | |
370 | ||
371 | switch (index) { | |
372 | case 0: | |
373 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); | |
374 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
375 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
376 | break; | |
377 | ||
378 | case 1: | |
379 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
380 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
381 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
382 | break; | |
383 | ||
384 | case 2: | |
385 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
386 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); | |
387 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); | |
388 | break; | |
389 | } | |
390 | ||
205d48ed | 391 | tegra_dc_window_commit(dc, index); |
10288eea | 392 | |
93396d0f | 393 | spin_unlock_irqrestore(&dc->lock, flags); |
c7679306 TR |
394 | } |
395 | ||
396 | static void tegra_plane_destroy(struct drm_plane *plane) | |
397 | { | |
398 | struct tegra_plane *p = to_tegra_plane(plane); | |
399 | ||
400 | drm_plane_cleanup(plane); | |
401 | kfree(p); | |
402 | } | |
403 | ||
404 | static const u32 tegra_primary_plane_formats[] = { | |
405 | DRM_FORMAT_XBGR8888, | |
406 | DRM_FORMAT_XRGB8888, | |
407 | DRM_FORMAT_RGB565, | |
408 | }; | |
409 | ||
4aa3df71 | 410 | static void tegra_primary_plane_destroy(struct drm_plane *plane) |
c7679306 | 411 | { |
4aa3df71 TR |
412 | tegra_plane_destroy(plane); |
413 | } | |
414 | ||
415 | static const struct drm_plane_funcs tegra_primary_plane_funcs = { | |
07866963 TR |
416 | .update_plane = drm_atomic_helper_update_plane, |
417 | .disable_plane = drm_atomic_helper_disable_plane, | |
4aa3df71 | 418 | .destroy = tegra_primary_plane_destroy, |
9d44189f TR |
419 | .reset = drm_atomic_helper_plane_reset, |
420 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
4aa3df71 TR |
421 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
422 | }; | |
423 | ||
424 | static int tegra_plane_prepare_fb(struct drm_plane *plane, | |
425 | struct drm_framebuffer *fb) | |
426 | { | |
427 | return 0; | |
428 | } | |
429 | ||
430 | static void tegra_plane_cleanup_fb(struct drm_plane *plane, | |
431 | struct drm_framebuffer *fb) | |
432 | { | |
433 | } | |
434 | ||
435 | static int tegra_plane_atomic_check(struct drm_plane *plane, | |
436 | struct drm_plane_state *state) | |
437 | { | |
438 | struct tegra_dc *dc = to_tegra_dc(state->crtc); | |
439 | struct tegra_bo_tiling tiling; | |
440 | int err; | |
441 | ||
442 | /* no need for further checks if the plane is being disabled */ | |
443 | if (!state->crtc) | |
444 | return 0; | |
445 | ||
446 | err = tegra_fb_get_tiling(state->fb, &tiling); | |
447 | if (err < 0) | |
448 | return err; | |
449 | ||
450 | if (tiling.mode == TEGRA_BO_TILING_MODE_BLOCK && | |
451 | !dc->soc->supports_block_linear) { | |
452 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
456 | /* | |
457 | * Tegra doesn't support different strides for U and V planes so we | |
458 | * error out if the user tries to display a framebuffer with such a | |
459 | * configuration. | |
460 | */ | |
461 | if (drm_format_num_planes(state->fb->pixel_format) > 2) { | |
462 | if (state->fb->pitches[2] != state->fb->pitches[1]) { | |
463 | DRM_ERROR("unsupported UV-plane configuration\n"); | |
464 | return -EINVAL; | |
465 | } | |
466 | } | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | static void tegra_plane_atomic_update(struct drm_plane *plane, | |
472 | struct drm_plane_state *old_state) | |
473 | { | |
474 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); | |
475 | struct drm_framebuffer *fb = plane->state->fb; | |
c7679306 | 476 | struct tegra_plane *p = to_tegra_plane(plane); |
c7679306 | 477 | struct tegra_dc_window window; |
4aa3df71 | 478 | unsigned int i; |
c7679306 TR |
479 | int err; |
480 | ||
4aa3df71 TR |
481 | /* rien ne va plus */ |
482 | if (!plane->state->crtc || !plane->state->fb) | |
483 | return; | |
484 | ||
c7679306 | 485 | memset(&window, 0, sizeof(window)); |
4aa3df71 TR |
486 | window.src.x = plane->state->src_x >> 16; |
487 | window.src.y = plane->state->src_y >> 16; | |
488 | window.src.w = plane->state->src_w >> 16; | |
489 | window.src.h = plane->state->src_h >> 16; | |
490 | window.dst.x = plane->state->crtc_x; | |
491 | window.dst.y = plane->state->crtc_y; | |
492 | window.dst.w = plane->state->crtc_w; | |
493 | window.dst.h = plane->state->crtc_h; | |
c7679306 TR |
494 | window.format = tegra_dc_format(fb->pixel_format, &window.swap); |
495 | window.bits_per_pixel = fb->bits_per_pixel; | |
496 | window.bottom_up = tegra_fb_is_bottom_up(fb); | |
497 | ||
498 | err = tegra_fb_get_tiling(fb, &window.tiling); | |
4aa3df71 | 499 | WARN_ON(err < 0); |
c7679306 | 500 | |
4aa3df71 TR |
501 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { |
502 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); | |
c7679306 | 503 | |
4aa3df71 TR |
504 | window.base[i] = bo->paddr + fb->offsets[i]; |
505 | window.stride[i] = fb->pitches[i]; | |
506 | } | |
10288eea | 507 | |
4aa3df71 | 508 | tegra_dc_setup_window(dc, p->index, &window); |
10288eea TR |
509 | } |
510 | ||
4aa3df71 TR |
511 | static void tegra_plane_atomic_disable(struct drm_plane *plane, |
512 | struct drm_plane_state *old_state) | |
c7679306 | 513 | { |
4aa3df71 TR |
514 | struct tegra_plane *p = to_tegra_plane(plane); |
515 | struct tegra_dc *dc; | |
516 | unsigned long flags; | |
517 | u32 value; | |
518 | ||
519 | /* rien ne va plus */ | |
520 | if (!old_state || !old_state->crtc) | |
521 | return; | |
522 | ||
523 | dc = to_tegra_dc(old_state->crtc); | |
524 | ||
525 | spin_lock_irqsave(&dc->lock, flags); | |
526 | ||
527 | value = WINDOW_A_SELECT << p->index; | |
528 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
529 | ||
530 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
531 | value &= ~WIN_ENABLE; | |
532 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
533 | ||
534 | tegra_dc_window_commit(dc, p->index); | |
535 | ||
536 | spin_unlock_irqrestore(&dc->lock, flags); | |
c7679306 TR |
537 | } |
538 | ||
4aa3df71 TR |
539 | static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = { |
540 | .prepare_fb = tegra_plane_prepare_fb, | |
541 | .cleanup_fb = tegra_plane_cleanup_fb, | |
542 | .atomic_check = tegra_plane_atomic_check, | |
543 | .atomic_update = tegra_plane_atomic_update, | |
544 | .atomic_disable = tegra_plane_atomic_disable, | |
c7679306 TR |
545 | }; |
546 | ||
547 | static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, | |
548 | struct tegra_dc *dc) | |
549 | { | |
518e6227 TR |
550 | /* |
551 | * Ideally this would use drm_crtc_mask(), but that would require the | |
552 | * CRTC to already be in the mode_config's list of CRTCs. However, it | |
553 | * will only be added to that list in the drm_crtc_init_with_planes() | |
554 | * (in tegra_dc_init()), which in turn requires registration of these | |
555 | * planes. So we have ourselves a nice little chicken and egg problem | |
556 | * here. | |
557 | * | |
558 | * We work around this by manually creating the mask from the number | |
559 | * of CRTCs that have been registered, and should therefore always be | |
560 | * the same as drm_crtc_index() after registration. | |
561 | */ | |
562 | unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; | |
c7679306 TR |
563 | struct tegra_plane *plane; |
564 | unsigned int num_formats; | |
565 | const u32 *formats; | |
566 | int err; | |
567 | ||
568 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
569 | if (!plane) | |
570 | return ERR_PTR(-ENOMEM); | |
571 | ||
572 | num_formats = ARRAY_SIZE(tegra_primary_plane_formats); | |
573 | formats = tegra_primary_plane_formats; | |
574 | ||
518e6227 | 575 | err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, |
c7679306 TR |
576 | &tegra_primary_plane_funcs, formats, |
577 | num_formats, DRM_PLANE_TYPE_PRIMARY); | |
578 | if (err < 0) { | |
579 | kfree(plane); | |
580 | return ERR_PTR(err); | |
581 | } | |
582 | ||
4aa3df71 TR |
583 | drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs); |
584 | ||
c7679306 TR |
585 | return &plane->base; |
586 | } | |
587 | ||
588 | static const u32 tegra_cursor_plane_formats[] = { | |
589 | DRM_FORMAT_RGBA8888, | |
590 | }; | |
591 | ||
4aa3df71 TR |
592 | static int tegra_cursor_atomic_check(struct drm_plane *plane, |
593 | struct drm_plane_state *state) | |
c7679306 | 594 | { |
4aa3df71 TR |
595 | /* no need for further checks if the plane is being disabled */ |
596 | if (!state->crtc) | |
597 | return 0; | |
c7679306 TR |
598 | |
599 | /* scaling not supported for cursor */ | |
4aa3df71 TR |
600 | if ((state->src_w >> 16 != state->crtc_w) || |
601 | (state->src_h >> 16 != state->crtc_h)) | |
c7679306 TR |
602 | return -EINVAL; |
603 | ||
604 | /* only square cursors supported */ | |
4aa3df71 TR |
605 | if (state->src_w != state->src_h) |
606 | return -EINVAL; | |
607 | ||
608 | if (state->crtc_w != 32 && state->crtc_w != 64 && | |
609 | state->crtc_w != 128 && state->crtc_w != 256) | |
c7679306 TR |
610 | return -EINVAL; |
611 | ||
4aa3df71 TR |
612 | return 0; |
613 | } | |
614 | ||
615 | static void tegra_cursor_atomic_update(struct drm_plane *plane, | |
616 | struct drm_plane_state *old_state) | |
617 | { | |
618 | struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); | |
619 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); | |
620 | struct drm_plane_state *state = plane->state; | |
621 | u32 value = CURSOR_CLIP_DISPLAY; | |
622 | ||
623 | /* rien ne va plus */ | |
624 | if (!plane->state->crtc || !plane->state->fb) | |
625 | return; | |
626 | ||
627 | switch (state->crtc_w) { | |
c7679306 TR |
628 | case 32: |
629 | value |= CURSOR_SIZE_32x32; | |
630 | break; | |
631 | ||
632 | case 64: | |
633 | value |= CURSOR_SIZE_64x64; | |
634 | break; | |
635 | ||
636 | case 128: | |
637 | value |= CURSOR_SIZE_128x128; | |
638 | break; | |
639 | ||
640 | case 256: | |
641 | value |= CURSOR_SIZE_256x256; | |
642 | break; | |
643 | ||
644 | default: | |
4aa3df71 TR |
645 | WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, |
646 | state->crtc_h); | |
647 | return; | |
c7679306 TR |
648 | } |
649 | ||
650 | value |= (bo->paddr >> 10) & 0x3fffff; | |
651 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); | |
652 | ||
653 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
654 | value = (bo->paddr >> 32) & 0x3; | |
655 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); | |
656 | #endif | |
657 | ||
658 | /* enable cursor and set blend mode */ | |
659 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
660 | value |= CURSOR_ENABLE; | |
661 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
662 | ||
663 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); | |
664 | value &= ~CURSOR_DST_BLEND_MASK; | |
665 | value &= ~CURSOR_SRC_BLEND_MASK; | |
666 | value |= CURSOR_MODE_NORMAL; | |
667 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; | |
668 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; | |
669 | value |= CURSOR_ALPHA; | |
670 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); | |
671 | ||
672 | /* position the cursor */ | |
4aa3df71 | 673 | value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); |
c7679306 TR |
674 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); |
675 | ||
676 | /* apply changes */ | |
677 | tegra_dc_cursor_commit(dc); | |
678 | tegra_dc_commit(dc); | |
c7679306 TR |
679 | } |
680 | ||
4aa3df71 TR |
681 | static void tegra_cursor_atomic_disable(struct drm_plane *plane, |
682 | struct drm_plane_state *old_state) | |
c7679306 | 683 | { |
4aa3df71 | 684 | struct tegra_dc *dc; |
c7679306 TR |
685 | u32 value; |
686 | ||
4aa3df71 TR |
687 | /* rien ne va plus */ |
688 | if (!old_state || !old_state->crtc) | |
689 | return; | |
690 | ||
691 | dc = to_tegra_dc(old_state->crtc); | |
c7679306 TR |
692 | |
693 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
694 | value &= ~CURSOR_ENABLE; | |
695 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
696 | ||
697 | tegra_dc_cursor_commit(dc); | |
698 | tegra_dc_commit(dc); | |
c7679306 TR |
699 | } |
700 | ||
701 | static const struct drm_plane_funcs tegra_cursor_plane_funcs = { | |
07866963 TR |
702 | .update_plane = drm_atomic_helper_update_plane, |
703 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 704 | .destroy = tegra_plane_destroy, |
9d44189f TR |
705 | .reset = drm_atomic_helper_plane_reset, |
706 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
4aa3df71 TR |
707 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
708 | }; | |
709 | ||
710 | static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { | |
711 | .prepare_fb = tegra_plane_prepare_fb, | |
712 | .cleanup_fb = tegra_plane_cleanup_fb, | |
713 | .atomic_check = tegra_cursor_atomic_check, | |
714 | .atomic_update = tegra_cursor_atomic_update, | |
715 | .atomic_disable = tegra_cursor_atomic_disable, | |
c7679306 TR |
716 | }; |
717 | ||
718 | static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, | |
719 | struct tegra_dc *dc) | |
720 | { | |
721 | struct tegra_plane *plane; | |
722 | unsigned int num_formats; | |
723 | const u32 *formats; | |
724 | int err; | |
725 | ||
726 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
727 | if (!plane) | |
728 | return ERR_PTR(-ENOMEM); | |
729 | ||
730 | num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); | |
731 | formats = tegra_cursor_plane_formats; | |
732 | ||
733 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, | |
734 | &tegra_cursor_plane_funcs, formats, | |
735 | num_formats, DRM_PLANE_TYPE_CURSOR); | |
736 | if (err < 0) { | |
737 | kfree(plane); | |
738 | return ERR_PTR(err); | |
739 | } | |
740 | ||
4aa3df71 | 741 | drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); |
f34bc787 | 742 | |
4aa3df71 | 743 | return &plane->base; |
f34bc787 TR |
744 | } |
745 | ||
c7679306 | 746 | static void tegra_overlay_plane_destroy(struct drm_plane *plane) |
f34bc787 | 747 | { |
c7679306 | 748 | tegra_plane_destroy(plane); |
f34bc787 TR |
749 | } |
750 | ||
c7679306 | 751 | static const struct drm_plane_funcs tegra_overlay_plane_funcs = { |
07866963 TR |
752 | .update_plane = drm_atomic_helper_update_plane, |
753 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 754 | .destroy = tegra_overlay_plane_destroy, |
9d44189f TR |
755 | .reset = drm_atomic_helper_plane_reset, |
756 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
4aa3df71 | 757 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
f34bc787 TR |
758 | }; |
759 | ||
c7679306 | 760 | static const uint32_t tegra_overlay_plane_formats[] = { |
dbe4d9a7 | 761 | DRM_FORMAT_XBGR8888, |
f34bc787 | 762 | DRM_FORMAT_XRGB8888, |
dbe4d9a7 | 763 | DRM_FORMAT_RGB565, |
f34bc787 | 764 | DRM_FORMAT_UYVY, |
f925390e | 765 | DRM_FORMAT_YUYV, |
f34bc787 TR |
766 | DRM_FORMAT_YUV420, |
767 | DRM_FORMAT_YUV422, | |
768 | }; | |
769 | ||
4aa3df71 TR |
770 | static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = { |
771 | .prepare_fb = tegra_plane_prepare_fb, | |
772 | .cleanup_fb = tegra_plane_cleanup_fb, | |
773 | .atomic_check = tegra_plane_atomic_check, | |
774 | .atomic_update = tegra_plane_atomic_update, | |
775 | .atomic_disable = tegra_plane_atomic_disable, | |
776 | }; | |
777 | ||
c7679306 TR |
778 | static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, |
779 | struct tegra_dc *dc, | |
780 | unsigned int index) | |
f34bc787 | 781 | { |
c7679306 TR |
782 | struct tegra_plane *plane; |
783 | unsigned int num_formats; | |
784 | const u32 *formats; | |
785 | int err; | |
f34bc787 | 786 | |
c7679306 TR |
787 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
788 | if (!plane) | |
789 | return ERR_PTR(-ENOMEM); | |
f34bc787 | 790 | |
c7679306 | 791 | plane->index = index; |
f34bc787 | 792 | |
c7679306 TR |
793 | num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); |
794 | formats = tegra_overlay_plane_formats; | |
f34bc787 | 795 | |
c7679306 TR |
796 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
797 | &tegra_overlay_plane_funcs, formats, | |
798 | num_formats, DRM_PLANE_TYPE_OVERLAY); | |
799 | if (err < 0) { | |
800 | kfree(plane); | |
801 | return ERR_PTR(err); | |
802 | } | |
803 | ||
4aa3df71 TR |
804 | drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs); |
805 | ||
c7679306 TR |
806 | return &plane->base; |
807 | } | |
808 | ||
809 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) | |
810 | { | |
811 | struct drm_plane *plane; | |
812 | unsigned int i; | |
813 | ||
814 | for (i = 0; i < 2; i++) { | |
815 | plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); | |
816 | if (IS_ERR(plane)) | |
817 | return PTR_ERR(plane); | |
f34bc787 TR |
818 | } |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
23fb4740 TR |
823 | static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, |
824 | struct drm_framebuffer *fb) | |
825 | { | |
de2ba664 | 826 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); |
db7fbdfd | 827 | unsigned int h_offset = 0, v_offset = 0; |
c134f019 | 828 | struct tegra_bo_tiling tiling; |
93396d0f | 829 | unsigned long value, flags; |
f925390e | 830 | unsigned int format, swap; |
c134f019 TR |
831 | int err; |
832 | ||
833 | err = tegra_fb_get_tiling(fb, &tiling); | |
834 | if (err < 0) | |
835 | return err; | |
23fb4740 | 836 | |
93396d0f SP |
837 | spin_lock_irqsave(&dc->lock, flags); |
838 | ||
23fb4740 TR |
839 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
840 | ||
841 | value = fb->offsets[0] + y * fb->pitches[0] + | |
842 | x * fb->bits_per_pixel / 8; | |
843 | ||
de2ba664 | 844 | tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); |
23fb4740 | 845 | tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); |
f925390e TR |
846 | |
847 | format = tegra_dc_format(fb->pixel_format, &swap); | |
ed683aea | 848 | tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); |
f925390e | 849 | tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP); |
23fb4740 | 850 | |
c134f019 TR |
851 | if (dc->soc->supports_block_linear) { |
852 | unsigned long height = tiling.value; | |
853 | ||
854 | switch (tiling.mode) { | |
855 | case TEGRA_BO_TILING_MODE_PITCH: | |
856 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
857 | break; | |
858 | ||
859 | case TEGRA_BO_TILING_MODE_TILED: | |
860 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
861 | break; | |
862 | ||
863 | case TEGRA_BO_TILING_MODE_BLOCK: | |
864 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
865 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
866 | break; | |
867 | } | |
868 | ||
869 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
773af77f | 870 | } else { |
c134f019 TR |
871 | switch (tiling.mode) { |
872 | case TEGRA_BO_TILING_MODE_PITCH: | |
873 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
874 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
875 | break; | |
773af77f | 876 | |
c134f019 TR |
877 | case TEGRA_BO_TILING_MODE_TILED: |
878 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
879 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
880 | break; | |
881 | ||
882 | case TEGRA_BO_TILING_MODE_BLOCK: | |
883 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
93396d0f | 884 | spin_unlock_irqrestore(&dc->lock, flags); |
c134f019 TR |
885 | return -EINVAL; |
886 | } | |
887 | ||
888 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
889 | } | |
773af77f | 890 | |
db7fbdfd TR |
891 | /* make sure bottom-up buffers are properly displayed */ |
892 | if (tegra_fb_is_bottom_up(fb)) { | |
893 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 894 | value |= V_DIRECTION; |
db7fbdfd TR |
895 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
896 | ||
897 | v_offset += fb->height - 1; | |
898 | } else { | |
899 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 900 | value &= ~V_DIRECTION; |
db7fbdfd TR |
901 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
902 | } | |
903 | ||
904 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
905 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
906 | ||
23fb4740 | 907 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
205d48ed | 908 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); |
23fb4740 TR |
909 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
910 | ||
93396d0f SP |
911 | spin_unlock_irqrestore(&dc->lock, flags); |
912 | ||
23fb4740 TR |
913 | return 0; |
914 | } | |
915 | ||
6e5ff998 TR |
916 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
917 | { | |
918 | unsigned long value, flags; | |
919 | ||
920 | spin_lock_irqsave(&dc->lock, flags); | |
921 | ||
922 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
923 | value |= VBLANK_INT; | |
924 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
925 | ||
926 | spin_unlock_irqrestore(&dc->lock, flags); | |
927 | } | |
928 | ||
929 | void tegra_dc_disable_vblank(struct tegra_dc *dc) | |
930 | { | |
931 | unsigned long value, flags; | |
932 | ||
933 | spin_lock_irqsave(&dc->lock, flags); | |
934 | ||
935 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
936 | value &= ~VBLANK_INT; | |
937 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
938 | ||
939 | spin_unlock_irqrestore(&dc->lock, flags); | |
940 | } | |
941 | ||
3c03c46a TR |
942 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
943 | { | |
944 | struct drm_device *drm = dc->base.dev; | |
945 | struct drm_crtc *crtc = &dc->base; | |
3c03c46a | 946 | unsigned long flags, base; |
de2ba664 | 947 | struct tegra_bo *bo; |
3c03c46a | 948 | |
6b59cc1c TR |
949 | spin_lock_irqsave(&drm->event_lock, flags); |
950 | ||
951 | if (!dc->event) { | |
952 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a | 953 | return; |
6b59cc1c | 954 | } |
3c03c46a | 955 | |
f4510a27 | 956 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
3c03c46a | 957 | |
8643bc6d | 958 | spin_lock(&dc->lock); |
93396d0f | 959 | |
3c03c46a | 960 | /* check if new start address has been latched */ |
93396d0f | 961 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
3c03c46a TR |
962 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
963 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | |
964 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
965 | ||
8643bc6d | 966 | spin_unlock(&dc->lock); |
93396d0f | 967 | |
f4510a27 | 968 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
ed7dae58 TR |
969 | drm_crtc_send_vblank_event(crtc, dc->event); |
970 | drm_crtc_vblank_put(crtc); | |
3c03c46a | 971 | dc->event = NULL; |
3c03c46a | 972 | } |
6b59cc1c TR |
973 | |
974 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a TR |
975 | } |
976 | ||
977 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | |
978 | { | |
979 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
980 | struct drm_device *drm = crtc->dev; | |
981 | unsigned long flags; | |
982 | ||
983 | spin_lock_irqsave(&drm->event_lock, flags); | |
984 | ||
985 | if (dc->event && dc->event->base.file_priv == file) { | |
986 | dc->event->base.destroy(&dc->event->base); | |
ed7dae58 | 987 | drm_crtc_vblank_put(crtc); |
3c03c46a TR |
988 | dc->event = NULL; |
989 | } | |
990 | ||
991 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
992 | } | |
993 | ||
994 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
a5b6f74e | 995 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
3c03c46a | 996 | { |
ed7dae58 | 997 | unsigned int pipe = drm_crtc_index(crtc); |
3c03c46a | 998 | struct tegra_dc *dc = to_tegra_dc(crtc); |
3c03c46a TR |
999 | |
1000 | if (dc->event) | |
1001 | return -EBUSY; | |
1002 | ||
1003 | if (event) { | |
ed7dae58 | 1004 | event->pipe = pipe; |
3c03c46a | 1005 | dc->event = event; |
ed7dae58 | 1006 | drm_crtc_vblank_get(crtc); |
3c03c46a TR |
1007 | } |
1008 | ||
9d44189f TR |
1009 | if (crtc->primary->state) |
1010 | drm_atomic_set_fb_for_plane(crtc->primary->state, fb); | |
1011 | ||
3c03c46a | 1012 | tegra_dc_set_base(dc, 0, 0, fb); |
f4510a27 | 1013 | crtc->primary->fb = fb; |
3c03c46a TR |
1014 | |
1015 | return 0; | |
1016 | } | |
1017 | ||
f002abc1 TR |
1018 | static void tegra_dc_destroy(struct drm_crtc *crtc) |
1019 | { | |
1020 | drm_crtc_cleanup(crtc); | |
f002abc1 TR |
1021 | } |
1022 | ||
ca915b10 TR |
1023 | static void tegra_crtc_reset(struct drm_crtc *crtc) |
1024 | { | |
1025 | struct tegra_dc_state *state; | |
1026 | ||
1027 | kfree(crtc->state); | |
1028 | crtc->state = NULL; | |
1029 | ||
1030 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
1031 | if (state) | |
1032 | crtc->state = &state->base; | |
1033 | } | |
1034 | ||
1035 | static struct drm_crtc_state * | |
1036 | tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) | |
1037 | { | |
1038 | struct tegra_dc_state *state = to_dc_state(crtc->state); | |
1039 | struct tegra_dc_state *copy; | |
1040 | ||
1041 | copy = kmemdup(state, sizeof(*state), GFP_KERNEL); | |
1042 | if (!copy) | |
1043 | return NULL; | |
1044 | ||
1045 | copy->base.mode_changed = false; | |
1046 | copy->base.planes_changed = false; | |
1047 | copy->base.event = NULL; | |
1048 | ||
1049 | return ©->base; | |
1050 | } | |
1051 | ||
1052 | static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, | |
1053 | struct drm_crtc_state *state) | |
1054 | { | |
1055 | kfree(state); | |
1056 | } | |
1057 | ||
d8f4a9ed | 1058 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
3c03c46a | 1059 | .page_flip = tegra_dc_page_flip, |
d8f4a9ed | 1060 | .set_config = drm_crtc_helper_set_config, |
f002abc1 | 1061 | .destroy = tegra_dc_destroy, |
ca915b10 TR |
1062 | .reset = tegra_crtc_reset, |
1063 | .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, | |
1064 | .atomic_destroy_state = tegra_crtc_atomic_destroy_state, | |
d8f4a9ed TR |
1065 | }; |
1066 | ||
86df256f TR |
1067 | static void tegra_dc_stop(struct tegra_dc *dc) |
1068 | { | |
1069 | u32 value; | |
1070 | ||
1071 | /* stop the display controller */ | |
1072 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1073 | value &= ~DISP_CTRL_MODE_MASK; | |
1074 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1075 | ||
1076 | tegra_dc_commit(dc); | |
1077 | } | |
1078 | ||
1079 | static bool tegra_dc_idle(struct tegra_dc *dc) | |
1080 | { | |
1081 | u32 value; | |
1082 | ||
1083 | value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); | |
1084 | ||
1085 | return (value & DISP_CTRL_MODE_MASK) == 0; | |
1086 | } | |
1087 | ||
1088 | static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) | |
1089 | { | |
1090 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1091 | ||
1092 | while (time_before(jiffies, timeout)) { | |
1093 | if (tegra_dc_idle(dc)) | |
1094 | return 0; | |
1095 | ||
1096 | usleep_range(1000, 2000); | |
1097 | } | |
1098 | ||
1099 | dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); | |
1100 | return -ETIMEDOUT; | |
1101 | } | |
1102 | ||
f34bc787 | 1103 | static void tegra_crtc_disable(struct drm_crtc *crtc) |
d8f4a9ed | 1104 | { |
f002abc1 | 1105 | struct tegra_dc *dc = to_tegra_dc(crtc); |
3b0e5855 | 1106 | u32 value; |
f002abc1 | 1107 | |
86df256f TR |
1108 | if (!tegra_dc_idle(dc)) { |
1109 | tegra_dc_stop(dc); | |
1110 | ||
1111 | /* | |
1112 | * Ignore the return value, there isn't anything useful to do | |
1113 | * in case this fails. | |
1114 | */ | |
1115 | tegra_dc_wait_idle(dc, 100); | |
1116 | } | |
36904adf | 1117 | |
3b0e5855 TR |
1118 | /* |
1119 | * This should really be part of the RGB encoder driver, but clearing | |
1120 | * these bits has the side-effect of stopping the display controller. | |
1121 | * When that happens no VBLANK interrupts will be raised. At the same | |
1122 | * time the encoder is disabled before the display controller, so the | |
1123 | * above code is always going to timeout waiting for the controller | |
1124 | * to go idle. | |
1125 | * | |
1126 | * Given the close coupling between the RGB encoder and the display | |
1127 | * controller doing it here is still kind of okay. None of the other | |
1128 | * encoder drivers require these bits to be cleared. | |
1129 | * | |
1130 | * XXX: Perhaps given that the display controller is switched off at | |
1131 | * this point anyway maybe clearing these bits isn't even useful for | |
1132 | * the RGB encoder? | |
1133 | */ | |
1134 | if (dc->rgb) { | |
1135 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1136 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1137 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); | |
1138 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1139 | } | |
1140 | ||
8ff64c17 | 1141 | drm_crtc_vblank_off(crtc); |
c7679306 | 1142 | tegra_dc_commit(dc); |
d8f4a9ed TR |
1143 | } |
1144 | ||
1145 | static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, | |
1146 | const struct drm_display_mode *mode, | |
1147 | struct drm_display_mode *adjusted) | |
1148 | { | |
1149 | return true; | |
1150 | } | |
1151 | ||
d8f4a9ed TR |
1152 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
1153 | struct drm_display_mode *mode) | |
1154 | { | |
0444c0ff TR |
1155 | unsigned int h_ref_to_sync = 1; |
1156 | unsigned int v_ref_to_sync = 1; | |
d8f4a9ed TR |
1157 | unsigned long value; |
1158 | ||
1159 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); | |
1160 | ||
1161 | value = (v_ref_to_sync << 16) | h_ref_to_sync; | |
1162 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); | |
1163 | ||
1164 | value = ((mode->vsync_end - mode->vsync_start) << 16) | | |
1165 | ((mode->hsync_end - mode->hsync_start) << 0); | |
1166 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); | |
1167 | ||
d8f4a9ed TR |
1168 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
1169 | ((mode->htotal - mode->hsync_end) << 0); | |
40495089 LS |
1170 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
1171 | ||
1172 | value = ((mode->vsync_start - mode->vdisplay) << 16) | | |
1173 | ((mode->hsync_start - mode->hdisplay) << 0); | |
d8f4a9ed TR |
1174 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
1175 | ||
1176 | value = (mode->vdisplay << 16) | mode->hdisplay; | |
1177 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
c5a107d3 TR |
1182 | int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent, |
1183 | unsigned long pclk, unsigned int div) | |
1184 | { | |
1185 | u32 value; | |
1186 | int err; | |
1187 | ||
1188 | err = clk_set_parent(dc->clk, parent); | |
1189 | if (err < 0) { | |
1190 | dev_err(dc->dev, "failed to set parent clock: %d\n", err); | |
1191 | return err; | |
1192 | } | |
1193 | ||
1194 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); | |
1195 | ||
1196 | value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; | |
1197 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); | |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
ca915b10 TR |
1202 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, |
1203 | struct drm_crtc_state *crtc_state, | |
1204 | struct clk *clk, unsigned long pclk, | |
1205 | unsigned int div) | |
1206 | { | |
1207 | struct tegra_dc_state *state = to_dc_state(crtc_state); | |
1208 | ||
1209 | state->clk = clk; | |
1210 | state->pclk = pclk; | |
1211 | state->div = div; | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
4aa3df71 | 1216 | static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc) |
d8f4a9ed | 1217 | { |
4aa3df71 | 1218 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
d8f4a9ed | 1219 | struct tegra_dc *dc = to_tegra_dc(crtc); |
dbb3f2f7 | 1220 | u32 value; |
d8f4a9ed | 1221 | |
d8f4a9ed TR |
1222 | /* program display mode */ |
1223 | tegra_dc_set_timings(dc, mode); | |
1224 | ||
42d0659b TR |
1225 | if (dc->soc->supports_border_color) |
1226 | tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); | |
1227 | ||
8620fc62 TR |
1228 | /* interlacing isn't supported yet, so disable it */ |
1229 | if (dc->soc->supports_interlacing) { | |
1230 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); | |
1231 | value &= ~INTERLACE_ENABLE; | |
1232 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); | |
1233 | } | |
d8f4a9ed TR |
1234 | } |
1235 | ||
1236 | static void tegra_crtc_prepare(struct drm_crtc *crtc) | |
1237 | { | |
1238 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1239 | unsigned int syncpt; | |
1240 | unsigned long value; | |
1241 | ||
8ff64c17 TR |
1242 | drm_crtc_vblank_off(crtc); |
1243 | ||
d8f4a9ed TR |
1244 | if (dc->pipe) |
1245 | syncpt = SYNCPT_VBLANK1; | |
1246 | else | |
1247 | syncpt = SYNCPT_VBLANK0; | |
1248 | ||
1249 | /* initialize display controller */ | |
1250 | tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1251 | tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); | |
1252 | ||
1253 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; | |
1254 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); | |
1255 | ||
1256 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1257 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1258 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); | |
1259 | ||
d8f4a9ed TR |
1260 | /* initialize timer */ |
1261 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | | |
1262 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); | |
1263 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1264 | ||
1265 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | | |
1266 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); | |
1267 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1268 | ||
d8f4a9ed TR |
1269 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
1270 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); | |
6e5ff998 TR |
1271 | |
1272 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; | |
1273 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
d8f4a9ed TR |
1274 | } |
1275 | ||
1276 | static void tegra_crtc_commit(struct drm_crtc *crtc) | |
1277 | { | |
1278 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
d8f4a9ed | 1279 | |
8ff64c17 | 1280 | drm_crtc_vblank_on(crtc); |
205d48ed | 1281 | tegra_dc_commit(dc); |
d8f4a9ed TR |
1282 | } |
1283 | ||
4aa3df71 TR |
1284 | static int tegra_crtc_atomic_check(struct drm_crtc *crtc, |
1285 | struct drm_crtc_state *state) | |
1286 | { | |
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static void tegra_crtc_atomic_begin(struct drm_crtc *crtc) | |
1291 | { | |
1292 | } | |
1293 | ||
1294 | static void tegra_crtc_atomic_flush(struct drm_crtc *crtc) | |
1295 | { | |
1296 | } | |
1297 | ||
d8f4a9ed | 1298 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { |
f34bc787 | 1299 | .disable = tegra_crtc_disable, |
d8f4a9ed | 1300 | .mode_fixup = tegra_crtc_mode_fixup, |
4aa3df71 TR |
1301 | .mode_set = drm_helper_crtc_mode_set, |
1302 | .mode_set_nofb = tegra_crtc_mode_set_nofb, | |
1303 | .mode_set_base = drm_helper_crtc_mode_set_base, | |
d8f4a9ed TR |
1304 | .prepare = tegra_crtc_prepare, |
1305 | .commit = tegra_crtc_commit, | |
4aa3df71 TR |
1306 | .atomic_check = tegra_crtc_atomic_check, |
1307 | .atomic_begin = tegra_crtc_atomic_begin, | |
1308 | .atomic_flush = tegra_crtc_atomic_flush, | |
d8f4a9ed TR |
1309 | }; |
1310 | ||
6e5ff998 | 1311 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
d8f4a9ed TR |
1312 | { |
1313 | struct tegra_dc *dc = data; | |
1314 | unsigned long status; | |
1315 | ||
1316 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); | |
1317 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); | |
1318 | ||
1319 | if (status & FRAME_END_INT) { | |
1320 | /* | |
1321 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); | |
1322 | */ | |
1323 | } | |
1324 | ||
1325 | if (status & VBLANK_INT) { | |
1326 | /* | |
1327 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | |
1328 | */ | |
ed7dae58 | 1329 | drm_crtc_handle_vblank(&dc->base); |
3c03c46a | 1330 | tegra_dc_finish_page_flip(dc); |
d8f4a9ed TR |
1331 | } |
1332 | ||
1333 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { | |
1334 | /* | |
1335 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); | |
1336 | */ | |
1337 | } | |
1338 | ||
1339 | return IRQ_HANDLED; | |
1340 | } | |
1341 | ||
1342 | static int tegra_dc_show_regs(struct seq_file *s, void *data) | |
1343 | { | |
1344 | struct drm_info_node *node = s->private; | |
1345 | struct tegra_dc *dc = node->info_ent->data; | |
1346 | ||
1347 | #define DUMP_REG(name) \ | |
03a60569 | 1348 | seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ |
d8f4a9ed TR |
1349 | tegra_dc_readl(dc, name)) |
1350 | ||
1351 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); | |
1352 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1353 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); | |
1354 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); | |
1355 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); | |
1356 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); | |
1357 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); | |
1358 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); | |
1359 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); | |
1360 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); | |
1361 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); | |
1362 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); | |
1363 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); | |
1364 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); | |
1365 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); | |
1366 | DUMP_REG(DC_CMD_SIGNAL_RAISE); | |
1367 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); | |
1368 | DUMP_REG(DC_CMD_INT_STATUS); | |
1369 | DUMP_REG(DC_CMD_INT_MASK); | |
1370 | DUMP_REG(DC_CMD_INT_ENABLE); | |
1371 | DUMP_REG(DC_CMD_INT_TYPE); | |
1372 | DUMP_REG(DC_CMD_INT_POLARITY); | |
1373 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); | |
1374 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); | |
1375 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); | |
1376 | DUMP_REG(DC_CMD_STATE_ACCESS); | |
1377 | DUMP_REG(DC_CMD_STATE_CONTROL); | |
1378 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); | |
1379 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); | |
1380 | DUMP_REG(DC_COM_CRC_CONTROL); | |
1381 | DUMP_REG(DC_COM_CRC_CHECKSUM); | |
1382 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); | |
1383 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); | |
1384 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); | |
1385 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); | |
1386 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); | |
1387 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); | |
1388 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); | |
1389 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); | |
1390 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); | |
1391 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); | |
1392 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); | |
1393 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); | |
1394 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); | |
1395 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); | |
1396 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); | |
1397 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); | |
1398 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); | |
1399 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); | |
1400 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); | |
1401 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); | |
1402 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); | |
1403 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); | |
1404 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); | |
1405 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); | |
1406 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); | |
1407 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); | |
1408 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); | |
1409 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); | |
1410 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); | |
1411 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); | |
1412 | DUMP_REG(DC_COM_SPI_CONTROL); | |
1413 | DUMP_REG(DC_COM_SPI_START_BYTE); | |
1414 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); | |
1415 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); | |
1416 | DUMP_REG(DC_COM_HSPI_CS_DC); | |
1417 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); | |
1418 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); | |
1419 | DUMP_REG(DC_COM_GPIO_CTRL); | |
1420 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); | |
1421 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); | |
1422 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); | |
1423 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); | |
1424 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); | |
1425 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1426 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1427 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); | |
1428 | DUMP_REG(DC_DISP_REF_TO_SYNC); | |
1429 | DUMP_REG(DC_DISP_SYNC_WIDTH); | |
1430 | DUMP_REG(DC_DISP_BACK_PORCH); | |
1431 | DUMP_REG(DC_DISP_ACTIVE); | |
1432 | DUMP_REG(DC_DISP_FRONT_PORCH); | |
1433 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); | |
1434 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); | |
1435 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); | |
1436 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); | |
1437 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); | |
1438 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); | |
1439 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); | |
1440 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); | |
1441 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); | |
1442 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); | |
1443 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); | |
1444 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); | |
1445 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); | |
1446 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); | |
1447 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); | |
1448 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); | |
1449 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); | |
1450 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); | |
1451 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); | |
1452 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); | |
1453 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); | |
1454 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); | |
1455 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); | |
1456 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); | |
1457 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); | |
1458 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); | |
1459 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); | |
1460 | DUMP_REG(DC_DISP_M0_CONTROL); | |
1461 | DUMP_REG(DC_DISP_M1_CONTROL); | |
1462 | DUMP_REG(DC_DISP_DI_CONTROL); | |
1463 | DUMP_REG(DC_DISP_PP_CONTROL); | |
1464 | DUMP_REG(DC_DISP_PP_SELECT_A); | |
1465 | DUMP_REG(DC_DISP_PP_SELECT_B); | |
1466 | DUMP_REG(DC_DISP_PP_SELECT_C); | |
1467 | DUMP_REG(DC_DISP_PP_SELECT_D); | |
1468 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); | |
1469 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); | |
1470 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); | |
1471 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); | |
1472 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); | |
1473 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); | |
1474 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); | |
1475 | DUMP_REG(DC_DISP_BORDER_COLOR); | |
1476 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); | |
1477 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); | |
1478 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); | |
1479 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); | |
1480 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); | |
1481 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); | |
1482 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); | |
1483 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); | |
1484 | DUMP_REG(DC_DISP_CURSOR_POSITION); | |
1485 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); | |
1486 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); | |
1487 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); | |
1488 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); | |
1489 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); | |
1490 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); | |
1491 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); | |
1492 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); | |
1493 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); | |
1494 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); | |
1495 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); | |
1496 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); | |
1497 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); | |
1498 | DUMP_REG(DC_DISP_SD_CONTROL); | |
1499 | DUMP_REG(DC_DISP_SD_CSC_COEFF); | |
1500 | DUMP_REG(DC_DISP_SD_LUT(0)); | |
1501 | DUMP_REG(DC_DISP_SD_LUT(1)); | |
1502 | DUMP_REG(DC_DISP_SD_LUT(2)); | |
1503 | DUMP_REG(DC_DISP_SD_LUT(3)); | |
1504 | DUMP_REG(DC_DISP_SD_LUT(4)); | |
1505 | DUMP_REG(DC_DISP_SD_LUT(5)); | |
1506 | DUMP_REG(DC_DISP_SD_LUT(6)); | |
1507 | DUMP_REG(DC_DISP_SD_LUT(7)); | |
1508 | DUMP_REG(DC_DISP_SD_LUT(8)); | |
1509 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); | |
1510 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); | |
1511 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); | |
1512 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); | |
1513 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); | |
1514 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); | |
1515 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); | |
1516 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); | |
1517 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); | |
1518 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); | |
1519 | DUMP_REG(DC_DISP_SD_BL_TF(0)); | |
1520 | DUMP_REG(DC_DISP_SD_BL_TF(1)); | |
1521 | DUMP_REG(DC_DISP_SD_BL_TF(2)); | |
1522 | DUMP_REG(DC_DISP_SD_BL_TF(3)); | |
1523 | DUMP_REG(DC_DISP_SD_BL_CONTROL); | |
1524 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); | |
1525 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); | |
e687651b TR |
1526 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
1527 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); | |
d8f4a9ed TR |
1528 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
1529 | DUMP_REG(DC_WIN_BYTE_SWAP); | |
1530 | DUMP_REG(DC_WIN_BUFFER_CONTROL); | |
1531 | DUMP_REG(DC_WIN_COLOR_DEPTH); | |
1532 | DUMP_REG(DC_WIN_POSITION); | |
1533 | DUMP_REG(DC_WIN_SIZE); | |
1534 | DUMP_REG(DC_WIN_PRESCALED_SIZE); | |
1535 | DUMP_REG(DC_WIN_H_INITIAL_DDA); | |
1536 | DUMP_REG(DC_WIN_V_INITIAL_DDA); | |
1537 | DUMP_REG(DC_WIN_DDA_INC); | |
1538 | DUMP_REG(DC_WIN_LINE_STRIDE); | |
1539 | DUMP_REG(DC_WIN_BUF_STRIDE); | |
1540 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); | |
1541 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); | |
1542 | DUMP_REG(DC_WIN_DV_CONTROL); | |
1543 | DUMP_REG(DC_WIN_BLEND_NOKEY); | |
1544 | DUMP_REG(DC_WIN_BLEND_1WIN); | |
1545 | DUMP_REG(DC_WIN_BLEND_2WIN_X); | |
1546 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); | |
f34bc787 | 1547 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
d8f4a9ed TR |
1548 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
1549 | DUMP_REG(DC_WINBUF_START_ADDR); | |
1550 | DUMP_REG(DC_WINBUF_START_ADDR_NS); | |
1551 | DUMP_REG(DC_WINBUF_START_ADDR_U); | |
1552 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); | |
1553 | DUMP_REG(DC_WINBUF_START_ADDR_V); | |
1554 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); | |
1555 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); | |
1556 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); | |
1557 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); | |
1558 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); | |
1559 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); | |
1560 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); | |
1561 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); | |
1562 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); | |
1563 | ||
1564 | #undef DUMP_REG | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | static struct drm_info_list debugfs_files[] = { | |
1570 | { "regs", tegra_dc_show_regs, 0, NULL }, | |
1571 | }; | |
1572 | ||
1573 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) | |
1574 | { | |
1575 | unsigned int i; | |
1576 | char *name; | |
1577 | int err; | |
1578 | ||
1579 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); | |
1580 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
1581 | kfree(name); | |
1582 | ||
1583 | if (!dc->debugfs) | |
1584 | return -ENOMEM; | |
1585 | ||
1586 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1587 | GFP_KERNEL); | |
1588 | if (!dc->debugfs_files) { | |
1589 | err = -ENOMEM; | |
1590 | goto remove; | |
1591 | } | |
1592 | ||
1593 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1594 | dc->debugfs_files[i].data = dc; | |
1595 | ||
1596 | err = drm_debugfs_create_files(dc->debugfs_files, | |
1597 | ARRAY_SIZE(debugfs_files), | |
1598 | dc->debugfs, minor); | |
1599 | if (err < 0) | |
1600 | goto free; | |
1601 | ||
1602 | dc->minor = minor; | |
1603 | ||
1604 | return 0; | |
1605 | ||
1606 | free: | |
1607 | kfree(dc->debugfs_files); | |
1608 | dc->debugfs_files = NULL; | |
1609 | remove: | |
1610 | debugfs_remove(dc->debugfs); | |
1611 | dc->debugfs = NULL; | |
1612 | ||
1613 | return err; | |
1614 | } | |
1615 | ||
1616 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) | |
1617 | { | |
1618 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1619 | dc->minor); | |
1620 | dc->minor = NULL; | |
1621 | ||
1622 | kfree(dc->debugfs_files); | |
1623 | dc->debugfs_files = NULL; | |
1624 | ||
1625 | debugfs_remove(dc->debugfs); | |
1626 | dc->debugfs = NULL; | |
1627 | ||
1628 | return 0; | |
1629 | } | |
1630 | ||
53fa7f72 | 1631 | static int tegra_dc_init(struct host1x_client *client) |
d8f4a9ed | 1632 | { |
9910f5c4 | 1633 | struct drm_device *drm = dev_get_drvdata(client->parent); |
776dc384 | 1634 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d1f3e1e0 | 1635 | struct tegra_drm *tegra = drm->dev_private; |
c7679306 TR |
1636 | struct drm_plane *primary = NULL; |
1637 | struct drm_plane *cursor = NULL; | |
d8f4a9ed TR |
1638 | int err; |
1639 | ||
df06b759 TR |
1640 | if (tegra->domain) { |
1641 | err = iommu_attach_device(tegra->domain, dc->dev); | |
1642 | if (err < 0) { | |
1643 | dev_err(dc->dev, "failed to attach to domain: %d\n", | |
1644 | err); | |
1645 | return err; | |
1646 | } | |
1647 | ||
1648 | dc->domain = tegra->domain; | |
1649 | } | |
1650 | ||
c7679306 TR |
1651 | primary = tegra_dc_primary_plane_create(drm, dc); |
1652 | if (IS_ERR(primary)) { | |
1653 | err = PTR_ERR(primary); | |
1654 | goto cleanup; | |
1655 | } | |
1656 | ||
1657 | if (dc->soc->supports_cursor) { | |
1658 | cursor = tegra_dc_cursor_plane_create(drm, dc); | |
1659 | if (IS_ERR(cursor)) { | |
1660 | err = PTR_ERR(cursor); | |
1661 | goto cleanup; | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, | |
1666 | &tegra_crtc_funcs); | |
1667 | if (err < 0) | |
1668 | goto cleanup; | |
1669 | ||
d8f4a9ed TR |
1670 | drm_mode_crtc_set_gamma_size(&dc->base, 256); |
1671 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); | |
1672 | ||
d1f3e1e0 TR |
1673 | /* |
1674 | * Keep track of the minimum pitch alignment across all display | |
1675 | * controllers. | |
1676 | */ | |
1677 | if (dc->soc->pitch_align > tegra->pitch_align) | |
1678 | tegra->pitch_align = dc->soc->pitch_align; | |
1679 | ||
9910f5c4 | 1680 | err = tegra_dc_rgb_init(drm, dc); |
d8f4a9ed TR |
1681 | if (err < 0 && err != -ENODEV) { |
1682 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); | |
c7679306 | 1683 | goto cleanup; |
d8f4a9ed TR |
1684 | } |
1685 | ||
9910f5c4 | 1686 | err = tegra_dc_add_planes(drm, dc); |
f34bc787 | 1687 | if (err < 0) |
c7679306 | 1688 | goto cleanup; |
f34bc787 | 1689 | |
d8f4a9ed | 1690 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
9910f5c4 | 1691 | err = tegra_dc_debugfs_init(dc, drm->primary); |
d8f4a9ed TR |
1692 | if (err < 0) |
1693 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); | |
1694 | } | |
1695 | ||
6e5ff998 | 1696 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
d8f4a9ed TR |
1697 | dev_name(dc->dev), dc); |
1698 | if (err < 0) { | |
1699 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, | |
1700 | err); | |
c7679306 | 1701 | goto cleanup; |
d8f4a9ed TR |
1702 | } |
1703 | ||
1704 | return 0; | |
c7679306 TR |
1705 | |
1706 | cleanup: | |
1707 | if (cursor) | |
1708 | drm_plane_cleanup(cursor); | |
1709 | ||
1710 | if (primary) | |
1711 | drm_plane_cleanup(primary); | |
1712 | ||
1713 | if (tegra->domain) { | |
1714 | iommu_detach_device(tegra->domain, dc->dev); | |
1715 | dc->domain = NULL; | |
1716 | } | |
1717 | ||
1718 | return err; | |
d8f4a9ed TR |
1719 | } |
1720 | ||
53fa7f72 | 1721 | static int tegra_dc_exit(struct host1x_client *client) |
d8f4a9ed | 1722 | { |
776dc384 | 1723 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d8f4a9ed TR |
1724 | int err; |
1725 | ||
1726 | devm_free_irq(dc->dev, dc->irq, dc); | |
1727 | ||
1728 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1729 | err = tegra_dc_debugfs_exit(dc); | |
1730 | if (err < 0) | |
1731 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); | |
1732 | } | |
1733 | ||
1734 | err = tegra_dc_rgb_exit(dc); | |
1735 | if (err) { | |
1736 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); | |
1737 | return err; | |
1738 | } | |
1739 | ||
df06b759 TR |
1740 | if (dc->domain) { |
1741 | iommu_detach_device(dc->domain, dc->dev); | |
1742 | dc->domain = NULL; | |
1743 | } | |
1744 | ||
d8f4a9ed TR |
1745 | return 0; |
1746 | } | |
1747 | ||
1748 | static const struct host1x_client_ops dc_client_ops = { | |
53fa7f72 TR |
1749 | .init = tegra_dc_init, |
1750 | .exit = tegra_dc_exit, | |
d8f4a9ed TR |
1751 | }; |
1752 | ||
8620fc62 | 1753 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
42d0659b | 1754 | .supports_border_color = true, |
8620fc62 | 1755 | .supports_interlacing = false, |
e687651b | 1756 | .supports_cursor = false, |
c134f019 | 1757 | .supports_block_linear = false, |
d1f3e1e0 | 1758 | .pitch_align = 8, |
9c012700 | 1759 | .has_powergate = false, |
8620fc62 TR |
1760 | }; |
1761 | ||
1762 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { | |
42d0659b | 1763 | .supports_border_color = true, |
8620fc62 | 1764 | .supports_interlacing = false, |
e687651b | 1765 | .supports_cursor = false, |
c134f019 | 1766 | .supports_block_linear = false, |
d1f3e1e0 | 1767 | .pitch_align = 8, |
9c012700 | 1768 | .has_powergate = false, |
d1f3e1e0 TR |
1769 | }; |
1770 | ||
1771 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { | |
42d0659b | 1772 | .supports_border_color = true, |
d1f3e1e0 TR |
1773 | .supports_interlacing = false, |
1774 | .supports_cursor = false, | |
1775 | .supports_block_linear = false, | |
1776 | .pitch_align = 64, | |
9c012700 | 1777 | .has_powergate = true, |
8620fc62 TR |
1778 | }; |
1779 | ||
1780 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { | |
42d0659b | 1781 | .supports_border_color = false, |
8620fc62 | 1782 | .supports_interlacing = true, |
e687651b | 1783 | .supports_cursor = true, |
c134f019 | 1784 | .supports_block_linear = true, |
d1f3e1e0 | 1785 | .pitch_align = 64, |
9c012700 | 1786 | .has_powergate = true, |
8620fc62 TR |
1787 | }; |
1788 | ||
1789 | static const struct of_device_id tegra_dc_of_match[] = { | |
1790 | { | |
1791 | .compatible = "nvidia,tegra124-dc", | |
1792 | .data = &tegra124_dc_soc_info, | |
9c012700 TR |
1793 | }, { |
1794 | .compatible = "nvidia,tegra114-dc", | |
1795 | .data = &tegra114_dc_soc_info, | |
8620fc62 TR |
1796 | }, { |
1797 | .compatible = "nvidia,tegra30-dc", | |
1798 | .data = &tegra30_dc_soc_info, | |
1799 | }, { | |
1800 | .compatible = "nvidia,tegra20-dc", | |
1801 | .data = &tegra20_dc_soc_info, | |
1802 | }, { | |
1803 | /* sentinel */ | |
1804 | } | |
1805 | }; | |
ef70728c | 1806 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
8620fc62 | 1807 | |
13411ddd TR |
1808 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
1809 | { | |
1810 | struct device_node *np; | |
1811 | u32 value = 0; | |
1812 | int err; | |
1813 | ||
1814 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); | |
1815 | if (err < 0) { | |
1816 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); | |
1817 | ||
1818 | /* | |
1819 | * If the nvidia,head property isn't present, try to find the | |
1820 | * correct head number by looking up the position of this | |
1821 | * display controller's node within the device tree. Assuming | |
1822 | * that the nodes are ordered properly in the DTS file and | |
1823 | * that the translation into a flattened device tree blob | |
1824 | * preserves that ordering this will actually yield the right | |
1825 | * head number. | |
1826 | * | |
1827 | * If those assumptions don't hold, this will still work for | |
1828 | * cases where only a single display controller is used. | |
1829 | */ | |
1830 | for_each_matching_node(np, tegra_dc_of_match) { | |
1831 | if (np == dc->dev->of_node) | |
1832 | break; | |
1833 | ||
1834 | value++; | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | dc->pipe = value; | |
1839 | ||
1840 | return 0; | |
1841 | } | |
1842 | ||
d8f4a9ed TR |
1843 | static int tegra_dc_probe(struct platform_device *pdev) |
1844 | { | |
8620fc62 | 1845 | const struct of_device_id *id; |
d8f4a9ed TR |
1846 | struct resource *regs; |
1847 | struct tegra_dc *dc; | |
1848 | int err; | |
1849 | ||
1850 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); | |
1851 | if (!dc) | |
1852 | return -ENOMEM; | |
1853 | ||
8620fc62 TR |
1854 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
1855 | if (!id) | |
1856 | return -ENODEV; | |
1857 | ||
6e5ff998 | 1858 | spin_lock_init(&dc->lock); |
d8f4a9ed TR |
1859 | INIT_LIST_HEAD(&dc->list); |
1860 | dc->dev = &pdev->dev; | |
8620fc62 | 1861 | dc->soc = id->data; |
d8f4a9ed | 1862 | |
13411ddd TR |
1863 | err = tegra_dc_parse_dt(dc); |
1864 | if (err < 0) | |
1865 | return err; | |
1866 | ||
d8f4a9ed TR |
1867 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
1868 | if (IS_ERR(dc->clk)) { | |
1869 | dev_err(&pdev->dev, "failed to get clock\n"); | |
1870 | return PTR_ERR(dc->clk); | |
1871 | } | |
1872 | ||
ca48080a SW |
1873 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
1874 | if (IS_ERR(dc->rst)) { | |
1875 | dev_err(&pdev->dev, "failed to get reset\n"); | |
1876 | return PTR_ERR(dc->rst); | |
1877 | } | |
1878 | ||
9c012700 TR |
1879 | if (dc->soc->has_powergate) { |
1880 | if (dc->pipe == 0) | |
1881 | dc->powergate = TEGRA_POWERGATE_DIS; | |
1882 | else | |
1883 | dc->powergate = TEGRA_POWERGATE_DISB; | |
1884 | ||
1885 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, | |
1886 | dc->rst); | |
1887 | if (err < 0) { | |
1888 | dev_err(&pdev->dev, "failed to power partition: %d\n", | |
1889 | err); | |
1890 | return err; | |
1891 | } | |
1892 | } else { | |
1893 | err = clk_prepare_enable(dc->clk); | |
1894 | if (err < 0) { | |
1895 | dev_err(&pdev->dev, "failed to enable clock: %d\n", | |
1896 | err); | |
1897 | return err; | |
1898 | } | |
1899 | ||
1900 | err = reset_control_deassert(dc->rst); | |
1901 | if (err < 0) { | |
1902 | dev_err(&pdev->dev, "failed to deassert reset: %d\n", | |
1903 | err); | |
1904 | return err; | |
1905 | } | |
1906 | } | |
d8f4a9ed TR |
1907 | |
1908 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1909 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
1910 | if (IS_ERR(dc->regs)) | |
1911 | return PTR_ERR(dc->regs); | |
d8f4a9ed TR |
1912 | |
1913 | dc->irq = platform_get_irq(pdev, 0); | |
1914 | if (dc->irq < 0) { | |
1915 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
1916 | return -ENXIO; | |
1917 | } | |
1918 | ||
776dc384 TR |
1919 | INIT_LIST_HEAD(&dc->client.list); |
1920 | dc->client.ops = &dc_client_ops; | |
1921 | dc->client.dev = &pdev->dev; | |
d8f4a9ed TR |
1922 | |
1923 | err = tegra_dc_rgb_probe(dc); | |
1924 | if (err < 0 && err != -ENODEV) { | |
1925 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); | |
1926 | return err; | |
1927 | } | |
1928 | ||
776dc384 | 1929 | err = host1x_client_register(&dc->client); |
d8f4a9ed TR |
1930 | if (err < 0) { |
1931 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1932 | err); | |
1933 | return err; | |
1934 | } | |
1935 | ||
1936 | platform_set_drvdata(pdev, dc); | |
1937 | ||
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | static int tegra_dc_remove(struct platform_device *pdev) | |
1942 | { | |
d8f4a9ed TR |
1943 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
1944 | int err; | |
1945 | ||
776dc384 | 1946 | err = host1x_client_unregister(&dc->client); |
d8f4a9ed TR |
1947 | if (err < 0) { |
1948 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1949 | err); | |
1950 | return err; | |
1951 | } | |
1952 | ||
59d29c0e TR |
1953 | err = tegra_dc_rgb_remove(dc); |
1954 | if (err < 0) { | |
1955 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); | |
1956 | return err; | |
1957 | } | |
1958 | ||
5482d75a | 1959 | reset_control_assert(dc->rst); |
9c012700 TR |
1960 | |
1961 | if (dc->soc->has_powergate) | |
1962 | tegra_powergate_power_off(dc->powergate); | |
1963 | ||
d8f4a9ed TR |
1964 | clk_disable_unprepare(dc->clk); |
1965 | ||
1966 | return 0; | |
1967 | } | |
1968 | ||
d8f4a9ed TR |
1969 | struct platform_driver tegra_dc_driver = { |
1970 | .driver = { | |
1971 | .name = "tegra-dc", | |
1972 | .owner = THIS_MODULE, | |
1973 | .of_match_table = tegra_dc_of_match, | |
1974 | }, | |
1975 | .probe = tegra_dc_probe, | |
1976 | .remove = tegra_dc_remove, | |
1977 | }; |