Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
9eb9b220 | 11 | #include <linux/debugfs.h> |
df06b759 | 12 | #include <linux/iommu.h> |
33a8eb8d | 13 | #include <linux/pm_runtime.h> |
ca48080a | 14 | #include <linux/reset.h> |
d8f4a9ed | 15 | |
9c012700 TR |
16 | #include <soc/tegra/pmc.h> |
17 | ||
de2ba664 AM |
18 | #include "dc.h" |
19 | #include "drm.h" | |
20 | #include "gem.h" | |
d8f4a9ed | 21 | |
9d44189f | 22 | #include <drm/drm_atomic.h> |
4aa3df71 | 23 | #include <drm/drm_atomic_helper.h> |
3cb9ae4f DV |
24 | #include <drm/drm_plane_helper.h> |
25 | ||
8620fc62 | 26 | struct tegra_dc_soc_info { |
42d0659b | 27 | bool supports_border_color; |
8620fc62 | 28 | bool supports_interlacing; |
e687651b | 29 | bool supports_cursor; |
c134f019 | 30 | bool supports_block_linear; |
d1f3e1e0 | 31 | unsigned int pitch_align; |
9c012700 | 32 | bool has_powergate; |
8620fc62 TR |
33 | }; |
34 | ||
f34bc787 TR |
35 | struct tegra_plane { |
36 | struct drm_plane base; | |
37 | unsigned int index; | |
d8f4a9ed TR |
38 | }; |
39 | ||
f34bc787 TR |
40 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
41 | { | |
42 | return container_of(plane, struct tegra_plane, base); | |
43 | } | |
44 | ||
ca915b10 TR |
45 | struct tegra_dc_state { |
46 | struct drm_crtc_state base; | |
47 | ||
48 | struct clk *clk; | |
49 | unsigned long pclk; | |
50 | unsigned int div; | |
47802b09 TR |
51 | |
52 | u32 planes; | |
ca915b10 TR |
53 | }; |
54 | ||
55 | static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) | |
56 | { | |
57 | if (state) | |
58 | return container_of(state, struct tegra_dc_state, base); | |
59 | ||
60 | return NULL; | |
61 | } | |
62 | ||
8f604f8c TR |
63 | struct tegra_plane_state { |
64 | struct drm_plane_state base; | |
65 | ||
66 | struct tegra_bo_tiling tiling; | |
67 | u32 format; | |
68 | u32 swap; | |
69 | }; | |
70 | ||
71 | static inline struct tegra_plane_state * | |
72 | to_tegra_plane_state(struct drm_plane_state *state) | |
73 | { | |
74 | if (state) | |
75 | return container_of(state, struct tegra_plane_state, base); | |
76 | ||
77 | return NULL; | |
78 | } | |
79 | ||
791ddb1e TR |
80 | static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) |
81 | { | |
82 | stats->frames = 0; | |
83 | stats->vblank = 0; | |
84 | stats->underflow = 0; | |
85 | stats->overflow = 0; | |
86 | } | |
87 | ||
86df256f TR |
88 | /* |
89 | * Reads the active copy of a register. This takes the dc->lock spinlock to | |
90 | * prevent races with the VBLANK processing which also needs access to the | |
91 | * active copy of some registers. | |
92 | */ | |
93 | static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) | |
94 | { | |
95 | unsigned long flags; | |
96 | u32 value; | |
97 | ||
98 | spin_lock_irqsave(&dc->lock, flags); | |
99 | ||
100 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | |
101 | value = tegra_dc_readl(dc, offset); | |
102 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
103 | ||
104 | spin_unlock_irqrestore(&dc->lock, flags); | |
105 | return value; | |
106 | } | |
107 | ||
d700ba7a TR |
108 | /* |
109 | * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the | |
110 | * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. | |
111 | * Latching happens mmediately if the display controller is in STOP mode or | |
112 | * on the next frame boundary otherwise. | |
113 | * | |
114 | * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The | |
115 | * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits | |
116 | * are written. When the *_ACT_REQ bits are written, the ARM copy is latched | |
117 | * into the ACTIVE copy, either immediately if the display controller is in | |
118 | * STOP mode, or at the next frame boundary otherwise. | |
119 | */ | |
62b9e063 | 120 | void tegra_dc_commit(struct tegra_dc *dc) |
205d48ed TR |
121 | { |
122 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
123 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
124 | } | |
125 | ||
8f604f8c | 126 | static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap) |
10288eea TR |
127 | { |
128 | /* assume no swapping of fetched data */ | |
129 | if (swap) | |
130 | *swap = BYTE_SWAP_NOSWAP; | |
131 | ||
8f604f8c | 132 | switch (fourcc) { |
10288eea | 133 | case DRM_FORMAT_XBGR8888: |
8f604f8c TR |
134 | *format = WIN_COLOR_DEPTH_R8G8B8A8; |
135 | break; | |
10288eea TR |
136 | |
137 | case DRM_FORMAT_XRGB8888: | |
8f604f8c TR |
138 | *format = WIN_COLOR_DEPTH_B8G8R8A8; |
139 | break; | |
10288eea TR |
140 | |
141 | case DRM_FORMAT_RGB565: | |
8f604f8c TR |
142 | *format = WIN_COLOR_DEPTH_B5G6R5; |
143 | break; | |
10288eea TR |
144 | |
145 | case DRM_FORMAT_UYVY: | |
8f604f8c TR |
146 | *format = WIN_COLOR_DEPTH_YCbCr422; |
147 | break; | |
10288eea TR |
148 | |
149 | case DRM_FORMAT_YUYV: | |
150 | if (swap) | |
151 | *swap = BYTE_SWAP_SWAP2; | |
152 | ||
8f604f8c TR |
153 | *format = WIN_COLOR_DEPTH_YCbCr422; |
154 | break; | |
10288eea TR |
155 | |
156 | case DRM_FORMAT_YUV420: | |
8f604f8c TR |
157 | *format = WIN_COLOR_DEPTH_YCbCr420P; |
158 | break; | |
10288eea TR |
159 | |
160 | case DRM_FORMAT_YUV422: | |
8f604f8c TR |
161 | *format = WIN_COLOR_DEPTH_YCbCr422P; |
162 | break; | |
10288eea TR |
163 | |
164 | default: | |
8f604f8c | 165 | return -EINVAL; |
10288eea TR |
166 | } |
167 | ||
8f604f8c | 168 | return 0; |
10288eea TR |
169 | } |
170 | ||
171 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) | |
172 | { | |
173 | switch (format) { | |
174 | case WIN_COLOR_DEPTH_YCbCr422: | |
175 | case WIN_COLOR_DEPTH_YUV422: | |
176 | if (planar) | |
177 | *planar = false; | |
178 | ||
179 | return true; | |
180 | ||
181 | case WIN_COLOR_DEPTH_YCbCr420P: | |
182 | case WIN_COLOR_DEPTH_YUV420P: | |
183 | case WIN_COLOR_DEPTH_YCbCr422P: | |
184 | case WIN_COLOR_DEPTH_YUV422P: | |
185 | case WIN_COLOR_DEPTH_YCbCr422R: | |
186 | case WIN_COLOR_DEPTH_YUV422R: | |
187 | case WIN_COLOR_DEPTH_YCbCr422RA: | |
188 | case WIN_COLOR_DEPTH_YUV422RA: | |
189 | if (planar) | |
190 | *planar = true; | |
191 | ||
192 | return true; | |
193 | } | |
194 | ||
fb35c6b6 TR |
195 | if (planar) |
196 | *planar = false; | |
197 | ||
10288eea TR |
198 | return false; |
199 | } | |
200 | ||
201 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, | |
202 | unsigned int bpp) | |
203 | { | |
204 | fixed20_12 outf = dfixed_init(out); | |
205 | fixed20_12 inf = dfixed_init(in); | |
206 | u32 dda_inc; | |
207 | int max; | |
208 | ||
209 | if (v) | |
210 | max = 15; | |
211 | else { | |
212 | switch (bpp) { | |
213 | case 2: | |
214 | max = 8; | |
215 | break; | |
216 | ||
217 | default: | |
218 | WARN_ON_ONCE(1); | |
219 | /* fallthrough */ | |
220 | case 4: | |
221 | max = 4; | |
222 | break; | |
223 | } | |
224 | } | |
225 | ||
226 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); | |
227 | inf.full -= dfixed_const(1); | |
228 | ||
229 | dda_inc = dfixed_div(inf, outf); | |
230 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); | |
231 | ||
232 | return dda_inc; | |
233 | } | |
234 | ||
235 | static inline u32 compute_initial_dda(unsigned int in) | |
236 | { | |
237 | fixed20_12 inf = dfixed_init(in); | |
238 | return dfixed_frac(inf); | |
239 | } | |
240 | ||
4aa3df71 TR |
241 | static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
242 | const struct tegra_dc_window *window) | |
10288eea TR |
243 | { |
244 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | |
93396d0f | 245 | unsigned long value, flags; |
10288eea TR |
246 | bool yuv, planar; |
247 | ||
248 | /* | |
249 | * For YUV planar modes, the number of bytes per pixel takes into | |
250 | * account only the luma component and therefore is 1. | |
251 | */ | |
252 | yuv = tegra_dc_format_is_yuv(window->format, &planar); | |
253 | if (!yuv) | |
254 | bpp = window->bits_per_pixel / 8; | |
255 | else | |
256 | bpp = planar ? 1 : 2; | |
257 | ||
93396d0f SP |
258 | spin_lock_irqsave(&dc->lock, flags); |
259 | ||
10288eea TR |
260 | value = WINDOW_A_SELECT << index; |
261 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
262 | ||
263 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); | |
264 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); | |
265 | ||
266 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); | |
267 | tegra_dc_writel(dc, value, DC_WIN_POSITION); | |
268 | ||
269 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); | |
270 | tegra_dc_writel(dc, value, DC_WIN_SIZE); | |
271 | ||
272 | h_offset = window->src.x * bpp; | |
273 | v_offset = window->src.y; | |
274 | h_size = window->src.w * bpp; | |
275 | v_size = window->src.h; | |
276 | ||
277 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); | |
278 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); | |
279 | ||
280 | /* | |
281 | * For DDA computations the number of bytes per pixel for YUV planar | |
282 | * modes needs to take into account all Y, U and V components. | |
283 | */ | |
284 | if (yuv && planar) | |
285 | bpp = 2; | |
286 | ||
287 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); | |
288 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); | |
289 | ||
290 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); | |
291 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); | |
292 | ||
293 | h_dda = compute_initial_dda(window->src.x); | |
294 | v_dda = compute_initial_dda(window->src.y); | |
295 | ||
296 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); | |
297 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); | |
298 | ||
299 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); | |
300 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); | |
301 | ||
302 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); | |
303 | ||
304 | if (yuv && planar) { | |
305 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); | |
306 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); | |
307 | value = window->stride[1] << 16 | window->stride[0]; | |
308 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); | |
309 | } else { | |
310 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); | |
311 | } | |
312 | ||
313 | if (window->bottom_up) | |
314 | v_offset += window->src.h - 1; | |
315 | ||
316 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
317 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
318 | ||
c134f019 TR |
319 | if (dc->soc->supports_block_linear) { |
320 | unsigned long height = window->tiling.value; | |
321 | ||
322 | switch (window->tiling.mode) { | |
323 | case TEGRA_BO_TILING_MODE_PITCH: | |
324 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
325 | break; | |
326 | ||
327 | case TEGRA_BO_TILING_MODE_TILED: | |
328 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
329 | break; | |
330 | ||
331 | case TEGRA_BO_TILING_MODE_BLOCK: | |
332 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
333 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
334 | break; | |
335 | } | |
336 | ||
337 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
10288eea | 338 | } else { |
c134f019 TR |
339 | switch (window->tiling.mode) { |
340 | case TEGRA_BO_TILING_MODE_PITCH: | |
341 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
342 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
343 | break; | |
10288eea | 344 | |
c134f019 TR |
345 | case TEGRA_BO_TILING_MODE_TILED: |
346 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
347 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
348 | break; | |
349 | ||
350 | case TEGRA_BO_TILING_MODE_BLOCK: | |
4aa3df71 TR |
351 | /* |
352 | * No need to handle this here because ->atomic_check | |
353 | * will already have filtered it out. | |
354 | */ | |
355 | break; | |
c134f019 TR |
356 | } |
357 | ||
358 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
359 | } | |
10288eea TR |
360 | |
361 | value = WIN_ENABLE; | |
362 | ||
363 | if (yuv) { | |
364 | /* setup default colorspace conversion coefficients */ | |
365 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); | |
366 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); | |
367 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); | |
368 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); | |
369 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); | |
370 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); | |
371 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); | |
372 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); | |
373 | ||
374 | value |= CSC_ENABLE; | |
375 | } else if (window->bits_per_pixel < 24) { | |
376 | value |= COLOR_EXPAND; | |
377 | } | |
378 | ||
379 | if (window->bottom_up) | |
380 | value |= V_DIRECTION; | |
381 | ||
382 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
383 | ||
384 | /* | |
385 | * Disable blending and assume Window A is the bottom-most window, | |
386 | * Window C is the top-most window and Window B is in the middle. | |
387 | */ | |
388 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); | |
389 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); | |
390 | ||
391 | switch (index) { | |
392 | case 0: | |
393 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); | |
394 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
395 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
396 | break; | |
397 | ||
398 | case 1: | |
399 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
400 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
401 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
402 | break; | |
403 | ||
404 | case 2: | |
405 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
406 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); | |
407 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); | |
408 | break; | |
409 | } | |
410 | ||
93396d0f | 411 | spin_unlock_irqrestore(&dc->lock, flags); |
c7679306 TR |
412 | } |
413 | ||
414 | static void tegra_plane_destroy(struct drm_plane *plane) | |
415 | { | |
416 | struct tegra_plane *p = to_tegra_plane(plane); | |
417 | ||
418 | drm_plane_cleanup(plane); | |
419 | kfree(p); | |
420 | } | |
421 | ||
422 | static const u32 tegra_primary_plane_formats[] = { | |
423 | DRM_FORMAT_XBGR8888, | |
424 | DRM_FORMAT_XRGB8888, | |
425 | DRM_FORMAT_RGB565, | |
426 | }; | |
427 | ||
4aa3df71 | 428 | static void tegra_primary_plane_destroy(struct drm_plane *plane) |
c7679306 | 429 | { |
4aa3df71 TR |
430 | tegra_plane_destroy(plane); |
431 | } | |
432 | ||
8f604f8c TR |
433 | static void tegra_plane_reset(struct drm_plane *plane) |
434 | { | |
435 | struct tegra_plane_state *state; | |
436 | ||
3b59b7ac | 437 | if (plane->state) |
2f701695 | 438 | __drm_atomic_helper_plane_destroy_state(plane->state); |
8f604f8c TR |
439 | |
440 | kfree(plane->state); | |
441 | plane->state = NULL; | |
442 | ||
443 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
444 | if (state) { | |
445 | plane->state = &state->base; | |
446 | plane->state->plane = plane; | |
447 | } | |
448 | } | |
449 | ||
450 | static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane) | |
451 | { | |
452 | struct tegra_plane_state *state = to_tegra_plane_state(plane->state); | |
453 | struct tegra_plane_state *copy; | |
454 | ||
3b59b7ac | 455 | copy = kmalloc(sizeof(*copy), GFP_KERNEL); |
8f604f8c TR |
456 | if (!copy) |
457 | return NULL; | |
458 | ||
3b59b7ac TR |
459 | __drm_atomic_helper_plane_duplicate_state(plane, ©->base); |
460 | copy->tiling = state->tiling; | |
461 | copy->format = state->format; | |
462 | copy->swap = state->swap; | |
8f604f8c TR |
463 | |
464 | return ©->base; | |
465 | } | |
466 | ||
467 | static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, | |
468 | struct drm_plane_state *state) | |
469 | { | |
2f701695 | 470 | __drm_atomic_helper_plane_destroy_state(state); |
8f604f8c TR |
471 | kfree(state); |
472 | } | |
473 | ||
4aa3df71 | 474 | static const struct drm_plane_funcs tegra_primary_plane_funcs = { |
07866963 TR |
475 | .update_plane = drm_atomic_helper_update_plane, |
476 | .disable_plane = drm_atomic_helper_disable_plane, | |
4aa3df71 | 477 | .destroy = tegra_primary_plane_destroy, |
8f604f8c TR |
478 | .reset = tegra_plane_reset, |
479 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
480 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
4aa3df71 TR |
481 | }; |
482 | ||
483 | static int tegra_plane_prepare_fb(struct drm_plane *plane, | |
d136dfee | 484 | const struct drm_plane_state *new_state) |
4aa3df71 TR |
485 | { |
486 | return 0; | |
487 | } | |
488 | ||
489 | static void tegra_plane_cleanup_fb(struct drm_plane *plane, | |
d136dfee | 490 | const struct drm_plane_state *old_fb) |
4aa3df71 TR |
491 | { |
492 | } | |
493 | ||
47802b09 TR |
494 | static int tegra_plane_state_add(struct tegra_plane *plane, |
495 | struct drm_plane_state *state) | |
496 | { | |
497 | struct drm_crtc_state *crtc_state; | |
498 | struct tegra_dc_state *tegra; | |
499 | ||
500 | /* Propagate errors from allocation or locking failures. */ | |
501 | crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); | |
502 | if (IS_ERR(crtc_state)) | |
503 | return PTR_ERR(crtc_state); | |
504 | ||
505 | tegra = to_dc_state(crtc_state); | |
506 | ||
507 | tegra->planes |= WIN_A_ACT_REQ << plane->index; | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
4aa3df71 TR |
512 | static int tegra_plane_atomic_check(struct drm_plane *plane, |
513 | struct drm_plane_state *state) | |
514 | { | |
8f604f8c TR |
515 | struct tegra_plane_state *plane_state = to_tegra_plane_state(state); |
516 | struct tegra_bo_tiling *tiling = &plane_state->tiling; | |
47802b09 | 517 | struct tegra_plane *tegra = to_tegra_plane(plane); |
4aa3df71 | 518 | struct tegra_dc *dc = to_tegra_dc(state->crtc); |
4aa3df71 TR |
519 | int err; |
520 | ||
521 | /* no need for further checks if the plane is being disabled */ | |
522 | if (!state->crtc) | |
523 | return 0; | |
524 | ||
8f604f8c TR |
525 | err = tegra_dc_format(state->fb->pixel_format, &plane_state->format, |
526 | &plane_state->swap); | |
4aa3df71 TR |
527 | if (err < 0) |
528 | return err; | |
529 | ||
8f604f8c TR |
530 | err = tegra_fb_get_tiling(state->fb, tiling); |
531 | if (err < 0) | |
532 | return err; | |
533 | ||
534 | if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && | |
4aa3df71 TR |
535 | !dc->soc->supports_block_linear) { |
536 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
537 | return -EINVAL; | |
538 | } | |
539 | ||
540 | /* | |
541 | * Tegra doesn't support different strides for U and V planes so we | |
542 | * error out if the user tries to display a framebuffer with such a | |
543 | * configuration. | |
544 | */ | |
545 | if (drm_format_num_planes(state->fb->pixel_format) > 2) { | |
546 | if (state->fb->pitches[2] != state->fb->pitches[1]) { | |
547 | DRM_ERROR("unsupported UV-plane configuration\n"); | |
548 | return -EINVAL; | |
549 | } | |
550 | } | |
551 | ||
47802b09 TR |
552 | err = tegra_plane_state_add(tegra, state); |
553 | if (err < 0) | |
554 | return err; | |
555 | ||
4aa3df71 TR |
556 | return 0; |
557 | } | |
558 | ||
559 | static void tegra_plane_atomic_update(struct drm_plane *plane, | |
560 | struct drm_plane_state *old_state) | |
561 | { | |
8f604f8c | 562 | struct tegra_plane_state *state = to_tegra_plane_state(plane->state); |
4aa3df71 TR |
563 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); |
564 | struct drm_framebuffer *fb = plane->state->fb; | |
c7679306 | 565 | struct tegra_plane *p = to_tegra_plane(plane); |
c7679306 | 566 | struct tegra_dc_window window; |
4aa3df71 | 567 | unsigned int i; |
c7679306 | 568 | |
4aa3df71 TR |
569 | /* rien ne va plus */ |
570 | if (!plane->state->crtc || !plane->state->fb) | |
571 | return; | |
572 | ||
c7679306 | 573 | memset(&window, 0, sizeof(window)); |
4aa3df71 TR |
574 | window.src.x = plane->state->src_x >> 16; |
575 | window.src.y = plane->state->src_y >> 16; | |
576 | window.src.w = plane->state->src_w >> 16; | |
577 | window.src.h = plane->state->src_h >> 16; | |
578 | window.dst.x = plane->state->crtc_x; | |
579 | window.dst.y = plane->state->crtc_y; | |
580 | window.dst.w = plane->state->crtc_w; | |
581 | window.dst.h = plane->state->crtc_h; | |
c7679306 TR |
582 | window.bits_per_pixel = fb->bits_per_pixel; |
583 | window.bottom_up = tegra_fb_is_bottom_up(fb); | |
584 | ||
8f604f8c TR |
585 | /* copy from state */ |
586 | window.tiling = state->tiling; | |
587 | window.format = state->format; | |
588 | window.swap = state->swap; | |
c7679306 | 589 | |
4aa3df71 TR |
590 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { |
591 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); | |
c7679306 | 592 | |
4aa3df71 TR |
593 | window.base[i] = bo->paddr + fb->offsets[i]; |
594 | window.stride[i] = fb->pitches[i]; | |
595 | } | |
10288eea | 596 | |
4aa3df71 | 597 | tegra_dc_setup_window(dc, p->index, &window); |
10288eea TR |
598 | } |
599 | ||
4aa3df71 TR |
600 | static void tegra_plane_atomic_disable(struct drm_plane *plane, |
601 | struct drm_plane_state *old_state) | |
c7679306 | 602 | { |
4aa3df71 TR |
603 | struct tegra_plane *p = to_tegra_plane(plane); |
604 | struct tegra_dc *dc; | |
605 | unsigned long flags; | |
606 | u32 value; | |
607 | ||
608 | /* rien ne va plus */ | |
609 | if (!old_state || !old_state->crtc) | |
610 | return; | |
611 | ||
612 | dc = to_tegra_dc(old_state->crtc); | |
613 | ||
614 | spin_lock_irqsave(&dc->lock, flags); | |
615 | ||
616 | value = WINDOW_A_SELECT << p->index; | |
617 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
618 | ||
619 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
620 | value &= ~WIN_ENABLE; | |
621 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
622 | ||
4aa3df71 | 623 | spin_unlock_irqrestore(&dc->lock, flags); |
c7679306 TR |
624 | } |
625 | ||
4aa3df71 TR |
626 | static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = { |
627 | .prepare_fb = tegra_plane_prepare_fb, | |
628 | .cleanup_fb = tegra_plane_cleanup_fb, | |
629 | .atomic_check = tegra_plane_atomic_check, | |
630 | .atomic_update = tegra_plane_atomic_update, | |
631 | .atomic_disable = tegra_plane_atomic_disable, | |
c7679306 TR |
632 | }; |
633 | ||
634 | static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, | |
635 | struct tegra_dc *dc) | |
636 | { | |
518e6227 TR |
637 | /* |
638 | * Ideally this would use drm_crtc_mask(), but that would require the | |
639 | * CRTC to already be in the mode_config's list of CRTCs. However, it | |
640 | * will only be added to that list in the drm_crtc_init_with_planes() | |
641 | * (in tegra_dc_init()), which in turn requires registration of these | |
642 | * planes. So we have ourselves a nice little chicken and egg problem | |
643 | * here. | |
644 | * | |
645 | * We work around this by manually creating the mask from the number | |
646 | * of CRTCs that have been registered, and should therefore always be | |
647 | * the same as drm_crtc_index() after registration. | |
648 | */ | |
649 | unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; | |
c7679306 TR |
650 | struct tegra_plane *plane; |
651 | unsigned int num_formats; | |
652 | const u32 *formats; | |
653 | int err; | |
654 | ||
655 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
656 | if (!plane) | |
657 | return ERR_PTR(-ENOMEM); | |
658 | ||
659 | num_formats = ARRAY_SIZE(tegra_primary_plane_formats); | |
660 | formats = tegra_primary_plane_formats; | |
661 | ||
518e6227 | 662 | err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, |
c7679306 | 663 | &tegra_primary_plane_funcs, formats, |
b0b3b795 VS |
664 | num_formats, DRM_PLANE_TYPE_PRIMARY, |
665 | NULL); | |
c7679306 TR |
666 | if (err < 0) { |
667 | kfree(plane); | |
668 | return ERR_PTR(err); | |
669 | } | |
670 | ||
4aa3df71 TR |
671 | drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs); |
672 | ||
c7679306 TR |
673 | return &plane->base; |
674 | } | |
675 | ||
676 | static const u32 tegra_cursor_plane_formats[] = { | |
677 | DRM_FORMAT_RGBA8888, | |
678 | }; | |
679 | ||
4aa3df71 TR |
680 | static int tegra_cursor_atomic_check(struct drm_plane *plane, |
681 | struct drm_plane_state *state) | |
c7679306 | 682 | { |
47802b09 TR |
683 | struct tegra_plane *tegra = to_tegra_plane(plane); |
684 | int err; | |
685 | ||
4aa3df71 TR |
686 | /* no need for further checks if the plane is being disabled */ |
687 | if (!state->crtc) | |
688 | return 0; | |
c7679306 TR |
689 | |
690 | /* scaling not supported for cursor */ | |
4aa3df71 TR |
691 | if ((state->src_w >> 16 != state->crtc_w) || |
692 | (state->src_h >> 16 != state->crtc_h)) | |
c7679306 TR |
693 | return -EINVAL; |
694 | ||
695 | /* only square cursors supported */ | |
4aa3df71 TR |
696 | if (state->src_w != state->src_h) |
697 | return -EINVAL; | |
698 | ||
699 | if (state->crtc_w != 32 && state->crtc_w != 64 && | |
700 | state->crtc_w != 128 && state->crtc_w != 256) | |
c7679306 TR |
701 | return -EINVAL; |
702 | ||
47802b09 TR |
703 | err = tegra_plane_state_add(tegra, state); |
704 | if (err < 0) | |
705 | return err; | |
706 | ||
4aa3df71 TR |
707 | return 0; |
708 | } | |
709 | ||
710 | static void tegra_cursor_atomic_update(struct drm_plane *plane, | |
711 | struct drm_plane_state *old_state) | |
712 | { | |
713 | struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); | |
714 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); | |
715 | struct drm_plane_state *state = plane->state; | |
716 | u32 value = CURSOR_CLIP_DISPLAY; | |
717 | ||
718 | /* rien ne va plus */ | |
719 | if (!plane->state->crtc || !plane->state->fb) | |
720 | return; | |
721 | ||
722 | switch (state->crtc_w) { | |
c7679306 TR |
723 | case 32: |
724 | value |= CURSOR_SIZE_32x32; | |
725 | break; | |
726 | ||
727 | case 64: | |
728 | value |= CURSOR_SIZE_64x64; | |
729 | break; | |
730 | ||
731 | case 128: | |
732 | value |= CURSOR_SIZE_128x128; | |
733 | break; | |
734 | ||
735 | case 256: | |
736 | value |= CURSOR_SIZE_256x256; | |
737 | break; | |
738 | ||
739 | default: | |
4aa3df71 TR |
740 | WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, |
741 | state->crtc_h); | |
742 | return; | |
c7679306 TR |
743 | } |
744 | ||
745 | value |= (bo->paddr >> 10) & 0x3fffff; | |
746 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); | |
747 | ||
748 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
749 | value = (bo->paddr >> 32) & 0x3; | |
750 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); | |
751 | #endif | |
752 | ||
753 | /* enable cursor and set blend mode */ | |
754 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
755 | value |= CURSOR_ENABLE; | |
756 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
757 | ||
758 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); | |
759 | value &= ~CURSOR_DST_BLEND_MASK; | |
760 | value &= ~CURSOR_SRC_BLEND_MASK; | |
761 | value |= CURSOR_MODE_NORMAL; | |
762 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; | |
763 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; | |
764 | value |= CURSOR_ALPHA; | |
765 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); | |
766 | ||
767 | /* position the cursor */ | |
4aa3df71 | 768 | value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); |
c7679306 | 769 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); |
c7679306 TR |
770 | } |
771 | ||
4aa3df71 TR |
772 | static void tegra_cursor_atomic_disable(struct drm_plane *plane, |
773 | struct drm_plane_state *old_state) | |
c7679306 | 774 | { |
4aa3df71 | 775 | struct tegra_dc *dc; |
c7679306 TR |
776 | u32 value; |
777 | ||
4aa3df71 TR |
778 | /* rien ne va plus */ |
779 | if (!old_state || !old_state->crtc) | |
780 | return; | |
781 | ||
782 | dc = to_tegra_dc(old_state->crtc); | |
c7679306 TR |
783 | |
784 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
785 | value &= ~CURSOR_ENABLE; | |
786 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
c7679306 TR |
787 | } |
788 | ||
789 | static const struct drm_plane_funcs tegra_cursor_plane_funcs = { | |
07866963 TR |
790 | .update_plane = drm_atomic_helper_update_plane, |
791 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 792 | .destroy = tegra_plane_destroy, |
8f604f8c TR |
793 | .reset = tegra_plane_reset, |
794 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
795 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
4aa3df71 TR |
796 | }; |
797 | ||
798 | static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { | |
799 | .prepare_fb = tegra_plane_prepare_fb, | |
800 | .cleanup_fb = tegra_plane_cleanup_fb, | |
801 | .atomic_check = tegra_cursor_atomic_check, | |
802 | .atomic_update = tegra_cursor_atomic_update, | |
803 | .atomic_disable = tegra_cursor_atomic_disable, | |
c7679306 TR |
804 | }; |
805 | ||
806 | static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, | |
807 | struct tegra_dc *dc) | |
808 | { | |
809 | struct tegra_plane *plane; | |
810 | unsigned int num_formats; | |
811 | const u32 *formats; | |
812 | int err; | |
813 | ||
814 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
815 | if (!plane) | |
816 | return ERR_PTR(-ENOMEM); | |
817 | ||
47802b09 | 818 | /* |
a1df3b24 TR |
819 | * This index is kind of fake. The cursor isn't a regular plane, but |
820 | * its update and activation request bits in DC_CMD_STATE_CONTROL do | |
821 | * use the same programming. Setting this fake index here allows the | |
822 | * code in tegra_add_plane_state() to do the right thing without the | |
823 | * need to special-casing the cursor plane. | |
47802b09 TR |
824 | */ |
825 | plane->index = 6; | |
826 | ||
c7679306 TR |
827 | num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); |
828 | formats = tegra_cursor_plane_formats; | |
829 | ||
830 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, | |
831 | &tegra_cursor_plane_funcs, formats, | |
b0b3b795 VS |
832 | num_formats, DRM_PLANE_TYPE_CURSOR, |
833 | NULL); | |
c7679306 TR |
834 | if (err < 0) { |
835 | kfree(plane); | |
836 | return ERR_PTR(err); | |
837 | } | |
838 | ||
4aa3df71 | 839 | drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); |
f34bc787 | 840 | |
4aa3df71 | 841 | return &plane->base; |
f34bc787 TR |
842 | } |
843 | ||
c7679306 | 844 | static void tegra_overlay_plane_destroy(struct drm_plane *plane) |
f34bc787 | 845 | { |
c7679306 | 846 | tegra_plane_destroy(plane); |
f34bc787 TR |
847 | } |
848 | ||
c7679306 | 849 | static const struct drm_plane_funcs tegra_overlay_plane_funcs = { |
07866963 TR |
850 | .update_plane = drm_atomic_helper_update_plane, |
851 | .disable_plane = drm_atomic_helper_disable_plane, | |
c7679306 | 852 | .destroy = tegra_overlay_plane_destroy, |
8f604f8c TR |
853 | .reset = tegra_plane_reset, |
854 | .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, | |
855 | .atomic_destroy_state = tegra_plane_atomic_destroy_state, | |
f34bc787 TR |
856 | }; |
857 | ||
c7679306 | 858 | static const uint32_t tegra_overlay_plane_formats[] = { |
dbe4d9a7 | 859 | DRM_FORMAT_XBGR8888, |
f34bc787 | 860 | DRM_FORMAT_XRGB8888, |
dbe4d9a7 | 861 | DRM_FORMAT_RGB565, |
f34bc787 | 862 | DRM_FORMAT_UYVY, |
f925390e | 863 | DRM_FORMAT_YUYV, |
f34bc787 TR |
864 | DRM_FORMAT_YUV420, |
865 | DRM_FORMAT_YUV422, | |
866 | }; | |
867 | ||
4aa3df71 TR |
868 | static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = { |
869 | .prepare_fb = tegra_plane_prepare_fb, | |
870 | .cleanup_fb = tegra_plane_cleanup_fb, | |
871 | .atomic_check = tegra_plane_atomic_check, | |
872 | .atomic_update = tegra_plane_atomic_update, | |
873 | .atomic_disable = tegra_plane_atomic_disable, | |
874 | }; | |
875 | ||
c7679306 TR |
876 | static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, |
877 | struct tegra_dc *dc, | |
878 | unsigned int index) | |
f34bc787 | 879 | { |
c7679306 TR |
880 | struct tegra_plane *plane; |
881 | unsigned int num_formats; | |
882 | const u32 *formats; | |
883 | int err; | |
f34bc787 | 884 | |
c7679306 TR |
885 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
886 | if (!plane) | |
887 | return ERR_PTR(-ENOMEM); | |
f34bc787 | 888 | |
c7679306 | 889 | plane->index = index; |
f34bc787 | 890 | |
c7679306 TR |
891 | num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); |
892 | formats = tegra_overlay_plane_formats; | |
f34bc787 | 893 | |
c7679306 TR |
894 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
895 | &tegra_overlay_plane_funcs, formats, | |
b0b3b795 VS |
896 | num_formats, DRM_PLANE_TYPE_OVERLAY, |
897 | NULL); | |
c7679306 TR |
898 | if (err < 0) { |
899 | kfree(plane); | |
900 | return ERR_PTR(err); | |
901 | } | |
902 | ||
4aa3df71 TR |
903 | drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs); |
904 | ||
c7679306 TR |
905 | return &plane->base; |
906 | } | |
907 | ||
908 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) | |
909 | { | |
910 | struct drm_plane *plane; | |
911 | unsigned int i; | |
912 | ||
913 | for (i = 0; i < 2; i++) { | |
914 | plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); | |
915 | if (IS_ERR(plane)) | |
916 | return PTR_ERR(plane); | |
f34bc787 TR |
917 | } |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
42e9ce05 TR |
922 | u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc) |
923 | { | |
924 | if (dc->syncpt) | |
925 | return host1x_syncpt_read(dc->syncpt); | |
926 | ||
927 | /* fallback to software emulated VBLANK counter */ | |
928 | return drm_crtc_vblank_count(&dc->base); | |
929 | } | |
930 | ||
6e5ff998 TR |
931 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
932 | { | |
933 | unsigned long value, flags; | |
934 | ||
935 | spin_lock_irqsave(&dc->lock, flags); | |
936 | ||
937 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
938 | value |= VBLANK_INT; | |
939 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
940 | ||
941 | spin_unlock_irqrestore(&dc->lock, flags); | |
942 | } | |
943 | ||
944 | void tegra_dc_disable_vblank(struct tegra_dc *dc) | |
945 | { | |
946 | unsigned long value, flags; | |
947 | ||
948 | spin_lock_irqsave(&dc->lock, flags); | |
949 | ||
950 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
951 | value &= ~VBLANK_INT; | |
952 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
953 | ||
954 | spin_unlock_irqrestore(&dc->lock, flags); | |
955 | } | |
956 | ||
3c03c46a TR |
957 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
958 | { | |
959 | struct drm_device *drm = dc->base.dev; | |
960 | struct drm_crtc *crtc = &dc->base; | |
3c03c46a | 961 | unsigned long flags, base; |
de2ba664 | 962 | struct tegra_bo *bo; |
3c03c46a | 963 | |
6b59cc1c TR |
964 | spin_lock_irqsave(&drm->event_lock, flags); |
965 | ||
966 | if (!dc->event) { | |
967 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a | 968 | return; |
6b59cc1c | 969 | } |
3c03c46a | 970 | |
f4510a27 | 971 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
3c03c46a | 972 | |
8643bc6d | 973 | spin_lock(&dc->lock); |
93396d0f | 974 | |
3c03c46a | 975 | /* check if new start address has been latched */ |
93396d0f | 976 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
3c03c46a TR |
977 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
978 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | |
979 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
980 | ||
8643bc6d | 981 | spin_unlock(&dc->lock); |
93396d0f | 982 | |
f4510a27 | 983 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
ed7dae58 TR |
984 | drm_crtc_send_vblank_event(crtc, dc->event); |
985 | drm_crtc_vblank_put(crtc); | |
3c03c46a | 986 | dc->event = NULL; |
3c03c46a | 987 | } |
6b59cc1c TR |
988 | |
989 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a TR |
990 | } |
991 | ||
f002abc1 TR |
992 | static void tegra_dc_destroy(struct drm_crtc *crtc) |
993 | { | |
994 | drm_crtc_cleanup(crtc); | |
f002abc1 TR |
995 | } |
996 | ||
ca915b10 TR |
997 | static void tegra_crtc_reset(struct drm_crtc *crtc) |
998 | { | |
999 | struct tegra_dc_state *state; | |
1000 | ||
3b59b7ac | 1001 | if (crtc->state) |
ec2dc6a0 | 1002 | __drm_atomic_helper_crtc_destroy_state(crtc->state); |
3b59b7ac | 1003 | |
ca915b10 TR |
1004 | kfree(crtc->state); |
1005 | crtc->state = NULL; | |
1006 | ||
1007 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
332bbe70 | 1008 | if (state) { |
ca915b10 | 1009 | crtc->state = &state->base; |
332bbe70 TR |
1010 | crtc->state->crtc = crtc; |
1011 | } | |
31930d4d TR |
1012 | |
1013 | drm_crtc_vblank_reset(crtc); | |
ca915b10 TR |
1014 | } |
1015 | ||
1016 | static struct drm_crtc_state * | |
1017 | tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) | |
1018 | { | |
1019 | struct tegra_dc_state *state = to_dc_state(crtc->state); | |
1020 | struct tegra_dc_state *copy; | |
1021 | ||
3b59b7ac | 1022 | copy = kmalloc(sizeof(*copy), GFP_KERNEL); |
ca915b10 TR |
1023 | if (!copy) |
1024 | return NULL; | |
1025 | ||
3b59b7ac TR |
1026 | __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); |
1027 | copy->clk = state->clk; | |
1028 | copy->pclk = state->pclk; | |
1029 | copy->div = state->div; | |
1030 | copy->planes = state->planes; | |
ca915b10 TR |
1031 | |
1032 | return ©->base; | |
1033 | } | |
1034 | ||
1035 | static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, | |
1036 | struct drm_crtc_state *state) | |
1037 | { | |
ec2dc6a0 | 1038 | __drm_atomic_helper_crtc_destroy_state(state); |
ca915b10 TR |
1039 | kfree(state); |
1040 | } | |
1041 | ||
d8f4a9ed | 1042 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
1503ca47 | 1043 | .page_flip = drm_atomic_helper_page_flip, |
74f48791 | 1044 | .set_config = drm_atomic_helper_set_config, |
f002abc1 | 1045 | .destroy = tegra_dc_destroy, |
ca915b10 TR |
1046 | .reset = tegra_crtc_reset, |
1047 | .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, | |
1048 | .atomic_destroy_state = tegra_crtc_atomic_destroy_state, | |
d8f4a9ed TR |
1049 | }; |
1050 | ||
d8f4a9ed TR |
1051 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
1052 | struct drm_display_mode *mode) | |
1053 | { | |
0444c0ff TR |
1054 | unsigned int h_ref_to_sync = 1; |
1055 | unsigned int v_ref_to_sync = 1; | |
d8f4a9ed TR |
1056 | unsigned long value; |
1057 | ||
1058 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); | |
1059 | ||
1060 | value = (v_ref_to_sync << 16) | h_ref_to_sync; | |
1061 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); | |
1062 | ||
1063 | value = ((mode->vsync_end - mode->vsync_start) << 16) | | |
1064 | ((mode->hsync_end - mode->hsync_start) << 0); | |
1065 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); | |
1066 | ||
d8f4a9ed TR |
1067 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
1068 | ((mode->htotal - mode->hsync_end) << 0); | |
40495089 LS |
1069 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
1070 | ||
1071 | value = ((mode->vsync_start - mode->vdisplay) << 16) | | |
1072 | ((mode->hsync_start - mode->hdisplay) << 0); | |
d8f4a9ed TR |
1073 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
1074 | ||
1075 | value = (mode->vdisplay << 16) | mode->hdisplay; | |
1076 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); | |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
9d910b60 TR |
1081 | /** |
1082 | * tegra_dc_state_setup_clock - check clock settings and store them in atomic | |
1083 | * state | |
1084 | * @dc: display controller | |
1085 | * @crtc_state: CRTC atomic state | |
1086 | * @clk: parent clock for display controller | |
1087 | * @pclk: pixel clock | |
1088 | * @div: shift clock divider | |
1089 | * | |
1090 | * Returns: | |
1091 | * 0 on success or a negative error-code on failure. | |
1092 | */ | |
ca915b10 TR |
1093 | int tegra_dc_state_setup_clock(struct tegra_dc *dc, |
1094 | struct drm_crtc_state *crtc_state, | |
1095 | struct clk *clk, unsigned long pclk, | |
1096 | unsigned int div) | |
1097 | { | |
1098 | struct tegra_dc_state *state = to_dc_state(crtc_state); | |
1099 | ||
d2982748 TR |
1100 | if (!clk_has_parent(dc->clk, clk)) |
1101 | return -EINVAL; | |
1102 | ||
ca915b10 TR |
1103 | state->clk = clk; |
1104 | state->pclk = pclk; | |
1105 | state->div = div; | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
76d59ed0 TR |
1110 | static void tegra_dc_commit_state(struct tegra_dc *dc, |
1111 | struct tegra_dc_state *state) | |
1112 | { | |
1113 | u32 value; | |
1114 | int err; | |
1115 | ||
1116 | err = clk_set_parent(dc->clk, state->clk); | |
1117 | if (err < 0) | |
1118 | dev_err(dc->dev, "failed to set parent clock: %d\n", err); | |
1119 | ||
1120 | /* | |
1121 | * Outputs may not want to change the parent clock rate. This is only | |
1122 | * relevant to Tegra20 where only a single display PLL is available. | |
1123 | * Since that PLL would typically be used for HDMI, an internal LVDS | |
1124 | * panel would need to be driven by some other clock such as PLL_P | |
1125 | * which is shared with other peripherals. Changing the clock rate | |
1126 | * should therefore be avoided. | |
1127 | */ | |
1128 | if (state->pclk > 0) { | |
1129 | err = clk_set_rate(state->clk, state->pclk); | |
1130 | if (err < 0) | |
1131 | dev_err(dc->dev, | |
1132 | "failed to set clock rate to %lu Hz\n", | |
1133 | state->pclk); | |
1134 | } | |
1135 | ||
1136 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), | |
1137 | state->div); | |
1138 | DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); | |
1139 | ||
1140 | value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; | |
1141 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); | |
1142 | } | |
1143 | ||
003fc848 TR |
1144 | static void tegra_dc_stop(struct tegra_dc *dc) |
1145 | { | |
1146 | u32 value; | |
1147 | ||
1148 | /* stop the display controller */ | |
1149 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1150 | value &= ~DISP_CTRL_MODE_MASK; | |
1151 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1152 | ||
1153 | tegra_dc_commit(dc); | |
1154 | } | |
1155 | ||
1156 | static bool tegra_dc_idle(struct tegra_dc *dc) | |
1157 | { | |
1158 | u32 value; | |
1159 | ||
1160 | value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); | |
1161 | ||
1162 | return (value & DISP_CTRL_MODE_MASK) == 0; | |
1163 | } | |
1164 | ||
1165 | static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) | |
1166 | { | |
1167 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1168 | ||
1169 | while (time_before(jiffies, timeout)) { | |
1170 | if (tegra_dc_idle(dc)) | |
1171 | return 0; | |
1172 | ||
1173 | usleep_range(1000, 2000); | |
1174 | } | |
1175 | ||
1176 | dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); | |
1177 | return -ETIMEDOUT; | |
1178 | } | |
1179 | ||
1180 | static void tegra_crtc_disable(struct drm_crtc *crtc) | |
1181 | { | |
1182 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1183 | u32 value; | |
1184 | ||
1185 | if (!tegra_dc_idle(dc)) { | |
1186 | tegra_dc_stop(dc); | |
1187 | ||
1188 | /* | |
1189 | * Ignore the return value, there isn't anything useful to do | |
1190 | * in case this fails. | |
1191 | */ | |
1192 | tegra_dc_wait_idle(dc, 100); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * This should really be part of the RGB encoder driver, but clearing | |
1197 | * these bits has the side-effect of stopping the display controller. | |
1198 | * When that happens no VBLANK interrupts will be raised. At the same | |
1199 | * time the encoder is disabled before the display controller, so the | |
1200 | * above code is always going to timeout waiting for the controller | |
1201 | * to go idle. | |
1202 | * | |
1203 | * Given the close coupling between the RGB encoder and the display | |
1204 | * controller doing it here is still kind of okay. None of the other | |
1205 | * encoder drivers require these bits to be cleared. | |
1206 | * | |
1207 | * XXX: Perhaps given that the display controller is switched off at | |
1208 | * this point anyway maybe clearing these bits isn't even useful for | |
1209 | * the RGB encoder? | |
1210 | */ | |
1211 | if (dc->rgb) { | |
1212 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1213 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1214 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); | |
1215 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1216 | } | |
1217 | ||
1218 | tegra_dc_stats_reset(&dc->stats); | |
1219 | drm_crtc_vblank_off(crtc); | |
33a8eb8d TR |
1220 | |
1221 | pm_runtime_put_sync(dc->dev); | |
003fc848 TR |
1222 | } |
1223 | ||
1224 | static void tegra_crtc_enable(struct drm_crtc *crtc) | |
d8f4a9ed | 1225 | { |
4aa3df71 | 1226 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
76d59ed0 | 1227 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
d8f4a9ed | 1228 | struct tegra_dc *dc = to_tegra_dc(crtc); |
dbb3f2f7 | 1229 | u32 value; |
d8f4a9ed | 1230 | |
33a8eb8d TR |
1231 | pm_runtime_get_sync(dc->dev); |
1232 | ||
1233 | /* initialize display controller */ | |
1234 | if (dc->syncpt) { | |
1235 | u32 syncpt = host1x_syncpt_id(dc->syncpt); | |
1236 | ||
1237 | value = SYNCPT_CNTRL_NO_STALL; | |
1238 | tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1239 | ||
1240 | value = SYNCPT_VSYNC_ENABLE | syncpt; | |
1241 | tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); | |
1242 | } | |
1243 | ||
1244 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1245 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1246 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); | |
1247 | ||
1248 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1249 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1250 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); | |
1251 | ||
1252 | /* initialize timer */ | |
1253 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | | |
1254 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); | |
1255 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1256 | ||
1257 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | | |
1258 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); | |
1259 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1260 | ||
1261 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1262 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1263 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); | |
1264 | ||
1265 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1266 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1267 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
1268 | ||
1269 | if (dc->soc->supports_border_color) | |
1270 | tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); | |
1271 | ||
1272 | /* apply PLL and pixel clock changes */ | |
76d59ed0 TR |
1273 | tegra_dc_commit_state(dc, state); |
1274 | ||
d8f4a9ed TR |
1275 | /* program display mode */ |
1276 | tegra_dc_set_timings(dc, mode); | |
1277 | ||
8620fc62 TR |
1278 | /* interlacing isn't supported yet, so disable it */ |
1279 | if (dc->soc->supports_interlacing) { | |
1280 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); | |
1281 | value &= ~INTERLACE_ENABLE; | |
1282 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); | |
1283 | } | |
666cb873 TR |
1284 | |
1285 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1286 | value &= ~DISP_CTRL_MODE_MASK; | |
1287 | value |= DISP_CTRL_MODE_C_DISPLAY; | |
1288 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1289 | ||
1290 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1291 | value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1292 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; | |
1293 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1294 | ||
1295 | tegra_dc_commit(dc); | |
d8f4a9ed | 1296 | |
8ff64c17 | 1297 | drm_crtc_vblank_on(crtc); |
d8f4a9ed TR |
1298 | } |
1299 | ||
4aa3df71 TR |
1300 | static int tegra_crtc_atomic_check(struct drm_crtc *crtc, |
1301 | struct drm_crtc_state *state) | |
1302 | { | |
1303 | return 0; | |
1304 | } | |
1305 | ||
613d2b27 ML |
1306 | static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, |
1307 | struct drm_crtc_state *old_crtc_state) | |
4aa3df71 | 1308 | { |
1503ca47 TR |
1309 | struct tegra_dc *dc = to_tegra_dc(crtc); |
1310 | ||
1311 | if (crtc->state->event) { | |
1312 | crtc->state->event->pipe = drm_crtc_index(crtc); | |
1313 | ||
1314 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
1315 | ||
1316 | dc->event = crtc->state->event; | |
1317 | crtc->state->event = NULL; | |
1318 | } | |
4aa3df71 TR |
1319 | } |
1320 | ||
613d2b27 ML |
1321 | static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, |
1322 | struct drm_crtc_state *old_crtc_state) | |
4aa3df71 | 1323 | { |
47802b09 TR |
1324 | struct tegra_dc_state *state = to_dc_state(crtc->state); |
1325 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1326 | ||
1327 | tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); | |
1328 | tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); | |
4aa3df71 TR |
1329 | } |
1330 | ||
d8f4a9ed | 1331 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { |
f34bc787 | 1332 | .disable = tegra_crtc_disable, |
003fc848 | 1333 | .enable = tegra_crtc_enable, |
4aa3df71 TR |
1334 | .atomic_check = tegra_crtc_atomic_check, |
1335 | .atomic_begin = tegra_crtc_atomic_begin, | |
1336 | .atomic_flush = tegra_crtc_atomic_flush, | |
d8f4a9ed TR |
1337 | }; |
1338 | ||
6e5ff998 | 1339 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
d8f4a9ed TR |
1340 | { |
1341 | struct tegra_dc *dc = data; | |
1342 | unsigned long status; | |
1343 | ||
1344 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); | |
1345 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); | |
1346 | ||
1347 | if (status & FRAME_END_INT) { | |
1348 | /* | |
1349 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); | |
1350 | */ | |
791ddb1e | 1351 | dc->stats.frames++; |
d8f4a9ed TR |
1352 | } |
1353 | ||
1354 | if (status & VBLANK_INT) { | |
1355 | /* | |
1356 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | |
1357 | */ | |
ed7dae58 | 1358 | drm_crtc_handle_vblank(&dc->base); |
3c03c46a | 1359 | tegra_dc_finish_page_flip(dc); |
791ddb1e | 1360 | dc->stats.vblank++; |
d8f4a9ed TR |
1361 | } |
1362 | ||
1363 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { | |
1364 | /* | |
1365 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); | |
1366 | */ | |
791ddb1e TR |
1367 | dc->stats.underflow++; |
1368 | } | |
1369 | ||
1370 | if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { | |
1371 | /* | |
1372 | dev_dbg(dc->dev, "%s(): overflow\n", __func__); | |
1373 | */ | |
1374 | dc->stats.overflow++; | |
d8f4a9ed TR |
1375 | } |
1376 | ||
1377 | return IRQ_HANDLED; | |
1378 | } | |
1379 | ||
1380 | static int tegra_dc_show_regs(struct seq_file *s, void *data) | |
1381 | { | |
1382 | struct drm_info_node *node = s->private; | |
1383 | struct tegra_dc *dc = node->info_ent->data; | |
003fc848 TR |
1384 | int err = 0; |
1385 | ||
1386 | drm_modeset_lock_crtc(&dc->base, NULL); | |
1387 | ||
1388 | if (!dc->base.state->active) { | |
1389 | err = -EBUSY; | |
1390 | goto unlock; | |
1391 | } | |
d8f4a9ed TR |
1392 | |
1393 | #define DUMP_REG(name) \ | |
03a60569 | 1394 | seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ |
d8f4a9ed TR |
1395 | tegra_dc_readl(dc, name)) |
1396 | ||
1397 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); | |
1398 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1399 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); | |
1400 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); | |
1401 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); | |
1402 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); | |
1403 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); | |
1404 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); | |
1405 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); | |
1406 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); | |
1407 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); | |
1408 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); | |
1409 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); | |
1410 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); | |
1411 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); | |
1412 | DUMP_REG(DC_CMD_SIGNAL_RAISE); | |
1413 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); | |
1414 | DUMP_REG(DC_CMD_INT_STATUS); | |
1415 | DUMP_REG(DC_CMD_INT_MASK); | |
1416 | DUMP_REG(DC_CMD_INT_ENABLE); | |
1417 | DUMP_REG(DC_CMD_INT_TYPE); | |
1418 | DUMP_REG(DC_CMD_INT_POLARITY); | |
1419 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); | |
1420 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); | |
1421 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); | |
1422 | DUMP_REG(DC_CMD_STATE_ACCESS); | |
1423 | DUMP_REG(DC_CMD_STATE_CONTROL); | |
1424 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); | |
1425 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); | |
1426 | DUMP_REG(DC_COM_CRC_CONTROL); | |
1427 | DUMP_REG(DC_COM_CRC_CHECKSUM); | |
1428 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); | |
1429 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); | |
1430 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); | |
1431 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); | |
1432 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); | |
1433 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); | |
1434 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); | |
1435 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); | |
1436 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); | |
1437 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); | |
1438 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); | |
1439 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); | |
1440 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); | |
1441 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); | |
1442 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); | |
1443 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); | |
1444 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); | |
1445 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); | |
1446 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); | |
1447 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); | |
1448 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); | |
1449 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); | |
1450 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); | |
1451 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); | |
1452 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); | |
1453 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); | |
1454 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); | |
1455 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); | |
1456 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); | |
1457 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); | |
1458 | DUMP_REG(DC_COM_SPI_CONTROL); | |
1459 | DUMP_REG(DC_COM_SPI_START_BYTE); | |
1460 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); | |
1461 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); | |
1462 | DUMP_REG(DC_COM_HSPI_CS_DC); | |
1463 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); | |
1464 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); | |
1465 | DUMP_REG(DC_COM_GPIO_CTRL); | |
1466 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); | |
1467 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); | |
1468 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); | |
1469 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); | |
1470 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); | |
1471 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1472 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1473 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); | |
1474 | DUMP_REG(DC_DISP_REF_TO_SYNC); | |
1475 | DUMP_REG(DC_DISP_SYNC_WIDTH); | |
1476 | DUMP_REG(DC_DISP_BACK_PORCH); | |
1477 | DUMP_REG(DC_DISP_ACTIVE); | |
1478 | DUMP_REG(DC_DISP_FRONT_PORCH); | |
1479 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); | |
1480 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); | |
1481 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); | |
1482 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); | |
1483 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); | |
1484 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); | |
1485 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); | |
1486 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); | |
1487 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); | |
1488 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); | |
1489 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); | |
1490 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); | |
1491 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); | |
1492 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); | |
1493 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); | |
1494 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); | |
1495 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); | |
1496 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); | |
1497 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); | |
1498 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); | |
1499 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); | |
1500 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); | |
1501 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); | |
1502 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); | |
1503 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); | |
1504 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); | |
1505 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); | |
1506 | DUMP_REG(DC_DISP_M0_CONTROL); | |
1507 | DUMP_REG(DC_DISP_M1_CONTROL); | |
1508 | DUMP_REG(DC_DISP_DI_CONTROL); | |
1509 | DUMP_REG(DC_DISP_PP_CONTROL); | |
1510 | DUMP_REG(DC_DISP_PP_SELECT_A); | |
1511 | DUMP_REG(DC_DISP_PP_SELECT_B); | |
1512 | DUMP_REG(DC_DISP_PP_SELECT_C); | |
1513 | DUMP_REG(DC_DISP_PP_SELECT_D); | |
1514 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); | |
1515 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); | |
1516 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); | |
1517 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); | |
1518 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); | |
1519 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); | |
1520 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); | |
1521 | DUMP_REG(DC_DISP_BORDER_COLOR); | |
1522 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); | |
1523 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); | |
1524 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); | |
1525 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); | |
1526 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); | |
1527 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); | |
1528 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); | |
1529 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); | |
1530 | DUMP_REG(DC_DISP_CURSOR_POSITION); | |
1531 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); | |
1532 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); | |
1533 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); | |
1534 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); | |
1535 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); | |
1536 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); | |
1537 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); | |
1538 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); | |
1539 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); | |
1540 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); | |
1541 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); | |
1542 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); | |
1543 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); | |
1544 | DUMP_REG(DC_DISP_SD_CONTROL); | |
1545 | DUMP_REG(DC_DISP_SD_CSC_COEFF); | |
1546 | DUMP_REG(DC_DISP_SD_LUT(0)); | |
1547 | DUMP_REG(DC_DISP_SD_LUT(1)); | |
1548 | DUMP_REG(DC_DISP_SD_LUT(2)); | |
1549 | DUMP_REG(DC_DISP_SD_LUT(3)); | |
1550 | DUMP_REG(DC_DISP_SD_LUT(4)); | |
1551 | DUMP_REG(DC_DISP_SD_LUT(5)); | |
1552 | DUMP_REG(DC_DISP_SD_LUT(6)); | |
1553 | DUMP_REG(DC_DISP_SD_LUT(7)); | |
1554 | DUMP_REG(DC_DISP_SD_LUT(8)); | |
1555 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); | |
1556 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); | |
1557 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); | |
1558 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); | |
1559 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); | |
1560 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); | |
1561 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); | |
1562 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); | |
1563 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); | |
1564 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); | |
1565 | DUMP_REG(DC_DISP_SD_BL_TF(0)); | |
1566 | DUMP_REG(DC_DISP_SD_BL_TF(1)); | |
1567 | DUMP_REG(DC_DISP_SD_BL_TF(2)); | |
1568 | DUMP_REG(DC_DISP_SD_BL_TF(3)); | |
1569 | DUMP_REG(DC_DISP_SD_BL_CONTROL); | |
1570 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); | |
1571 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); | |
e687651b TR |
1572 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
1573 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); | |
d8f4a9ed TR |
1574 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
1575 | DUMP_REG(DC_WIN_BYTE_SWAP); | |
1576 | DUMP_REG(DC_WIN_BUFFER_CONTROL); | |
1577 | DUMP_REG(DC_WIN_COLOR_DEPTH); | |
1578 | DUMP_REG(DC_WIN_POSITION); | |
1579 | DUMP_REG(DC_WIN_SIZE); | |
1580 | DUMP_REG(DC_WIN_PRESCALED_SIZE); | |
1581 | DUMP_REG(DC_WIN_H_INITIAL_DDA); | |
1582 | DUMP_REG(DC_WIN_V_INITIAL_DDA); | |
1583 | DUMP_REG(DC_WIN_DDA_INC); | |
1584 | DUMP_REG(DC_WIN_LINE_STRIDE); | |
1585 | DUMP_REG(DC_WIN_BUF_STRIDE); | |
1586 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); | |
1587 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); | |
1588 | DUMP_REG(DC_WIN_DV_CONTROL); | |
1589 | DUMP_REG(DC_WIN_BLEND_NOKEY); | |
1590 | DUMP_REG(DC_WIN_BLEND_1WIN); | |
1591 | DUMP_REG(DC_WIN_BLEND_2WIN_X); | |
1592 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); | |
f34bc787 | 1593 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
d8f4a9ed TR |
1594 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
1595 | DUMP_REG(DC_WINBUF_START_ADDR); | |
1596 | DUMP_REG(DC_WINBUF_START_ADDR_NS); | |
1597 | DUMP_REG(DC_WINBUF_START_ADDR_U); | |
1598 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); | |
1599 | DUMP_REG(DC_WINBUF_START_ADDR_V); | |
1600 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); | |
1601 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); | |
1602 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); | |
1603 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); | |
1604 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); | |
1605 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); | |
1606 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); | |
1607 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); | |
1608 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); | |
1609 | ||
1610 | #undef DUMP_REG | |
1611 | ||
003fc848 TR |
1612 | unlock: |
1613 | drm_modeset_unlock_crtc(&dc->base); | |
1614 | return err; | |
d8f4a9ed TR |
1615 | } |
1616 | ||
6ca1f62f TR |
1617 | static int tegra_dc_show_crc(struct seq_file *s, void *data) |
1618 | { | |
1619 | struct drm_info_node *node = s->private; | |
1620 | struct tegra_dc *dc = node->info_ent->data; | |
003fc848 | 1621 | int err = 0; |
6ca1f62f TR |
1622 | u32 value; |
1623 | ||
003fc848 TR |
1624 | drm_modeset_lock_crtc(&dc->base, NULL); |
1625 | ||
1626 | if (!dc->base.state->active) { | |
1627 | err = -EBUSY; | |
1628 | goto unlock; | |
1629 | } | |
1630 | ||
6ca1f62f TR |
1631 | value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; |
1632 | tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); | |
1633 | tegra_dc_commit(dc); | |
1634 | ||
1635 | drm_crtc_wait_one_vblank(&dc->base); | |
1636 | drm_crtc_wait_one_vblank(&dc->base); | |
1637 | ||
1638 | value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); | |
1639 | seq_printf(s, "%08x\n", value); | |
1640 | ||
1641 | tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); | |
1642 | ||
003fc848 TR |
1643 | unlock: |
1644 | drm_modeset_unlock_crtc(&dc->base); | |
1645 | return err; | |
6ca1f62f TR |
1646 | } |
1647 | ||
791ddb1e TR |
1648 | static int tegra_dc_show_stats(struct seq_file *s, void *data) |
1649 | { | |
1650 | struct drm_info_node *node = s->private; | |
1651 | struct tegra_dc *dc = node->info_ent->data; | |
1652 | ||
1653 | seq_printf(s, "frames: %lu\n", dc->stats.frames); | |
1654 | seq_printf(s, "vblank: %lu\n", dc->stats.vblank); | |
1655 | seq_printf(s, "underflow: %lu\n", dc->stats.underflow); | |
1656 | seq_printf(s, "overflow: %lu\n", dc->stats.overflow); | |
1657 | ||
d8f4a9ed TR |
1658 | return 0; |
1659 | } | |
1660 | ||
1661 | static struct drm_info_list debugfs_files[] = { | |
1662 | { "regs", tegra_dc_show_regs, 0, NULL }, | |
6ca1f62f | 1663 | { "crc", tegra_dc_show_crc, 0, NULL }, |
791ddb1e | 1664 | { "stats", tegra_dc_show_stats, 0, NULL }, |
d8f4a9ed TR |
1665 | }; |
1666 | ||
1667 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) | |
1668 | { | |
1669 | unsigned int i; | |
1670 | char *name; | |
1671 | int err; | |
1672 | ||
1673 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); | |
1674 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
1675 | kfree(name); | |
1676 | ||
1677 | if (!dc->debugfs) | |
1678 | return -ENOMEM; | |
1679 | ||
1680 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1681 | GFP_KERNEL); | |
1682 | if (!dc->debugfs_files) { | |
1683 | err = -ENOMEM; | |
1684 | goto remove; | |
1685 | } | |
1686 | ||
1687 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1688 | dc->debugfs_files[i].data = dc; | |
1689 | ||
1690 | err = drm_debugfs_create_files(dc->debugfs_files, | |
1691 | ARRAY_SIZE(debugfs_files), | |
1692 | dc->debugfs, minor); | |
1693 | if (err < 0) | |
1694 | goto free; | |
1695 | ||
1696 | dc->minor = minor; | |
1697 | ||
1698 | return 0; | |
1699 | ||
1700 | free: | |
1701 | kfree(dc->debugfs_files); | |
1702 | dc->debugfs_files = NULL; | |
1703 | remove: | |
1704 | debugfs_remove(dc->debugfs); | |
1705 | dc->debugfs = NULL; | |
1706 | ||
1707 | return err; | |
1708 | } | |
1709 | ||
1710 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) | |
1711 | { | |
1712 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1713 | dc->minor); | |
1714 | dc->minor = NULL; | |
1715 | ||
1716 | kfree(dc->debugfs_files); | |
1717 | dc->debugfs_files = NULL; | |
1718 | ||
1719 | debugfs_remove(dc->debugfs); | |
1720 | dc->debugfs = NULL; | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
53fa7f72 | 1725 | static int tegra_dc_init(struct host1x_client *client) |
d8f4a9ed | 1726 | { |
9910f5c4 | 1727 | struct drm_device *drm = dev_get_drvdata(client->parent); |
2bcdcbfa | 1728 | unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; |
776dc384 | 1729 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d1f3e1e0 | 1730 | struct tegra_drm *tegra = drm->dev_private; |
c7679306 TR |
1731 | struct drm_plane *primary = NULL; |
1732 | struct drm_plane *cursor = NULL; | |
d8f4a9ed TR |
1733 | int err; |
1734 | ||
2bcdcbfa TR |
1735 | dc->syncpt = host1x_syncpt_request(dc->dev, flags); |
1736 | if (!dc->syncpt) | |
1737 | dev_warn(dc->dev, "failed to allocate syncpoint\n"); | |
1738 | ||
df06b759 TR |
1739 | if (tegra->domain) { |
1740 | err = iommu_attach_device(tegra->domain, dc->dev); | |
1741 | if (err < 0) { | |
1742 | dev_err(dc->dev, "failed to attach to domain: %d\n", | |
1743 | err); | |
1744 | return err; | |
1745 | } | |
1746 | ||
1747 | dc->domain = tegra->domain; | |
1748 | } | |
1749 | ||
c7679306 TR |
1750 | primary = tegra_dc_primary_plane_create(drm, dc); |
1751 | if (IS_ERR(primary)) { | |
1752 | err = PTR_ERR(primary); | |
1753 | goto cleanup; | |
1754 | } | |
1755 | ||
1756 | if (dc->soc->supports_cursor) { | |
1757 | cursor = tegra_dc_cursor_plane_create(drm, dc); | |
1758 | if (IS_ERR(cursor)) { | |
1759 | err = PTR_ERR(cursor); | |
1760 | goto cleanup; | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, | |
f9882876 | 1765 | &tegra_crtc_funcs, NULL); |
c7679306 TR |
1766 | if (err < 0) |
1767 | goto cleanup; | |
1768 | ||
d8f4a9ed TR |
1769 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); |
1770 | ||
d1f3e1e0 TR |
1771 | /* |
1772 | * Keep track of the minimum pitch alignment across all display | |
1773 | * controllers. | |
1774 | */ | |
1775 | if (dc->soc->pitch_align > tegra->pitch_align) | |
1776 | tegra->pitch_align = dc->soc->pitch_align; | |
1777 | ||
9910f5c4 | 1778 | err = tegra_dc_rgb_init(drm, dc); |
d8f4a9ed TR |
1779 | if (err < 0 && err != -ENODEV) { |
1780 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); | |
c7679306 | 1781 | goto cleanup; |
d8f4a9ed TR |
1782 | } |
1783 | ||
9910f5c4 | 1784 | err = tegra_dc_add_planes(drm, dc); |
f34bc787 | 1785 | if (err < 0) |
c7679306 | 1786 | goto cleanup; |
f34bc787 | 1787 | |
d8f4a9ed | 1788 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
9910f5c4 | 1789 | err = tegra_dc_debugfs_init(dc, drm->primary); |
d8f4a9ed TR |
1790 | if (err < 0) |
1791 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); | |
1792 | } | |
1793 | ||
6e5ff998 | 1794 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
d8f4a9ed TR |
1795 | dev_name(dc->dev), dc); |
1796 | if (err < 0) { | |
1797 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, | |
1798 | err); | |
c7679306 | 1799 | goto cleanup; |
d8f4a9ed TR |
1800 | } |
1801 | ||
1802 | return 0; | |
c7679306 TR |
1803 | |
1804 | cleanup: | |
1805 | if (cursor) | |
1806 | drm_plane_cleanup(cursor); | |
1807 | ||
1808 | if (primary) | |
1809 | drm_plane_cleanup(primary); | |
1810 | ||
1811 | if (tegra->domain) { | |
1812 | iommu_detach_device(tegra->domain, dc->dev); | |
1813 | dc->domain = NULL; | |
1814 | } | |
1815 | ||
1816 | return err; | |
d8f4a9ed TR |
1817 | } |
1818 | ||
53fa7f72 | 1819 | static int tegra_dc_exit(struct host1x_client *client) |
d8f4a9ed | 1820 | { |
776dc384 | 1821 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d8f4a9ed TR |
1822 | int err; |
1823 | ||
1824 | devm_free_irq(dc->dev, dc->irq, dc); | |
1825 | ||
1826 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1827 | err = tegra_dc_debugfs_exit(dc); | |
1828 | if (err < 0) | |
1829 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); | |
1830 | } | |
1831 | ||
1832 | err = tegra_dc_rgb_exit(dc); | |
1833 | if (err) { | |
1834 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); | |
1835 | return err; | |
1836 | } | |
1837 | ||
df06b759 TR |
1838 | if (dc->domain) { |
1839 | iommu_detach_device(dc->domain, dc->dev); | |
1840 | dc->domain = NULL; | |
1841 | } | |
1842 | ||
2bcdcbfa TR |
1843 | host1x_syncpt_free(dc->syncpt); |
1844 | ||
d8f4a9ed TR |
1845 | return 0; |
1846 | } | |
1847 | ||
1848 | static const struct host1x_client_ops dc_client_ops = { | |
53fa7f72 TR |
1849 | .init = tegra_dc_init, |
1850 | .exit = tegra_dc_exit, | |
d8f4a9ed TR |
1851 | }; |
1852 | ||
8620fc62 | 1853 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
42d0659b | 1854 | .supports_border_color = true, |
8620fc62 | 1855 | .supports_interlacing = false, |
e687651b | 1856 | .supports_cursor = false, |
c134f019 | 1857 | .supports_block_linear = false, |
d1f3e1e0 | 1858 | .pitch_align = 8, |
9c012700 | 1859 | .has_powergate = false, |
8620fc62 TR |
1860 | }; |
1861 | ||
1862 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { | |
42d0659b | 1863 | .supports_border_color = true, |
8620fc62 | 1864 | .supports_interlacing = false, |
e687651b | 1865 | .supports_cursor = false, |
c134f019 | 1866 | .supports_block_linear = false, |
d1f3e1e0 | 1867 | .pitch_align = 8, |
9c012700 | 1868 | .has_powergate = false, |
d1f3e1e0 TR |
1869 | }; |
1870 | ||
1871 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { | |
42d0659b | 1872 | .supports_border_color = true, |
d1f3e1e0 TR |
1873 | .supports_interlacing = false, |
1874 | .supports_cursor = false, | |
1875 | .supports_block_linear = false, | |
1876 | .pitch_align = 64, | |
9c012700 | 1877 | .has_powergate = true, |
8620fc62 TR |
1878 | }; |
1879 | ||
1880 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { | |
42d0659b | 1881 | .supports_border_color = false, |
8620fc62 | 1882 | .supports_interlacing = true, |
e687651b | 1883 | .supports_cursor = true, |
c134f019 | 1884 | .supports_block_linear = true, |
d1f3e1e0 | 1885 | .pitch_align = 64, |
9c012700 | 1886 | .has_powergate = true, |
8620fc62 TR |
1887 | }; |
1888 | ||
5b4f516f TR |
1889 | static const struct tegra_dc_soc_info tegra210_dc_soc_info = { |
1890 | .supports_border_color = false, | |
1891 | .supports_interlacing = true, | |
1892 | .supports_cursor = true, | |
1893 | .supports_block_linear = true, | |
1894 | .pitch_align = 64, | |
1895 | .has_powergate = true, | |
1896 | }; | |
1897 | ||
8620fc62 TR |
1898 | static const struct of_device_id tegra_dc_of_match[] = { |
1899 | { | |
5b4f516f TR |
1900 | .compatible = "nvidia,tegra210-dc", |
1901 | .data = &tegra210_dc_soc_info, | |
1902 | }, { | |
8620fc62 TR |
1903 | .compatible = "nvidia,tegra124-dc", |
1904 | .data = &tegra124_dc_soc_info, | |
9c012700 TR |
1905 | }, { |
1906 | .compatible = "nvidia,tegra114-dc", | |
1907 | .data = &tegra114_dc_soc_info, | |
8620fc62 TR |
1908 | }, { |
1909 | .compatible = "nvidia,tegra30-dc", | |
1910 | .data = &tegra30_dc_soc_info, | |
1911 | }, { | |
1912 | .compatible = "nvidia,tegra20-dc", | |
1913 | .data = &tegra20_dc_soc_info, | |
1914 | }, { | |
1915 | /* sentinel */ | |
1916 | } | |
1917 | }; | |
ef70728c | 1918 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
8620fc62 | 1919 | |
13411ddd TR |
1920 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
1921 | { | |
1922 | struct device_node *np; | |
1923 | u32 value = 0; | |
1924 | int err; | |
1925 | ||
1926 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); | |
1927 | if (err < 0) { | |
1928 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); | |
1929 | ||
1930 | /* | |
1931 | * If the nvidia,head property isn't present, try to find the | |
1932 | * correct head number by looking up the position of this | |
1933 | * display controller's node within the device tree. Assuming | |
1934 | * that the nodes are ordered properly in the DTS file and | |
1935 | * that the translation into a flattened device tree blob | |
1936 | * preserves that ordering this will actually yield the right | |
1937 | * head number. | |
1938 | * | |
1939 | * If those assumptions don't hold, this will still work for | |
1940 | * cases where only a single display controller is used. | |
1941 | */ | |
1942 | for_each_matching_node(np, tegra_dc_of_match) { | |
cf6b1744 JL |
1943 | if (np == dc->dev->of_node) { |
1944 | of_node_put(np); | |
13411ddd | 1945 | break; |
cf6b1744 | 1946 | } |
13411ddd TR |
1947 | |
1948 | value++; | |
1949 | } | |
1950 | } | |
1951 | ||
1952 | dc->pipe = value; | |
1953 | ||
1954 | return 0; | |
1955 | } | |
1956 | ||
d8f4a9ed TR |
1957 | static int tegra_dc_probe(struct platform_device *pdev) |
1958 | { | |
8620fc62 | 1959 | const struct of_device_id *id; |
d8f4a9ed TR |
1960 | struct resource *regs; |
1961 | struct tegra_dc *dc; | |
1962 | int err; | |
1963 | ||
1964 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); | |
1965 | if (!dc) | |
1966 | return -ENOMEM; | |
1967 | ||
8620fc62 TR |
1968 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
1969 | if (!id) | |
1970 | return -ENODEV; | |
1971 | ||
6e5ff998 | 1972 | spin_lock_init(&dc->lock); |
d8f4a9ed TR |
1973 | INIT_LIST_HEAD(&dc->list); |
1974 | dc->dev = &pdev->dev; | |
8620fc62 | 1975 | dc->soc = id->data; |
d8f4a9ed | 1976 | |
13411ddd TR |
1977 | err = tegra_dc_parse_dt(dc); |
1978 | if (err < 0) | |
1979 | return err; | |
1980 | ||
d8f4a9ed TR |
1981 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
1982 | if (IS_ERR(dc->clk)) { | |
1983 | dev_err(&pdev->dev, "failed to get clock\n"); | |
1984 | return PTR_ERR(dc->clk); | |
1985 | } | |
1986 | ||
ca48080a SW |
1987 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
1988 | if (IS_ERR(dc->rst)) { | |
1989 | dev_err(&pdev->dev, "failed to get reset\n"); | |
1990 | return PTR_ERR(dc->rst); | |
1991 | } | |
1992 | ||
33a8eb8d TR |
1993 | reset_control_assert(dc->rst); |
1994 | ||
9c012700 TR |
1995 | if (dc->soc->has_powergate) { |
1996 | if (dc->pipe == 0) | |
1997 | dc->powergate = TEGRA_POWERGATE_DIS; | |
1998 | else | |
1999 | dc->powergate = TEGRA_POWERGATE_DISB; | |
2000 | ||
33a8eb8d | 2001 | tegra_powergate_power_off(dc->powergate); |
9c012700 | 2002 | } |
d8f4a9ed TR |
2003 | |
2004 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
2005 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
2006 | if (IS_ERR(dc->regs)) | |
2007 | return PTR_ERR(dc->regs); | |
d8f4a9ed TR |
2008 | |
2009 | dc->irq = platform_get_irq(pdev, 0); | |
2010 | if (dc->irq < 0) { | |
2011 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
2012 | return -ENXIO; | |
2013 | } | |
2014 | ||
d8f4a9ed TR |
2015 | err = tegra_dc_rgb_probe(dc); |
2016 | if (err < 0 && err != -ENODEV) { | |
2017 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); | |
2018 | return err; | |
2019 | } | |
2020 | ||
33a8eb8d TR |
2021 | platform_set_drvdata(pdev, dc); |
2022 | pm_runtime_enable(&pdev->dev); | |
2023 | ||
2024 | INIT_LIST_HEAD(&dc->client.list); | |
2025 | dc->client.ops = &dc_client_ops; | |
2026 | dc->client.dev = &pdev->dev; | |
2027 | ||
776dc384 | 2028 | err = host1x_client_register(&dc->client); |
d8f4a9ed TR |
2029 | if (err < 0) { |
2030 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
2031 | err); | |
2032 | return err; | |
2033 | } | |
2034 | ||
d8f4a9ed TR |
2035 | return 0; |
2036 | } | |
2037 | ||
2038 | static int tegra_dc_remove(struct platform_device *pdev) | |
2039 | { | |
d8f4a9ed TR |
2040 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
2041 | int err; | |
2042 | ||
776dc384 | 2043 | err = host1x_client_unregister(&dc->client); |
d8f4a9ed TR |
2044 | if (err < 0) { |
2045 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
2046 | err); | |
2047 | return err; | |
2048 | } | |
2049 | ||
59d29c0e TR |
2050 | err = tegra_dc_rgb_remove(dc); |
2051 | if (err < 0) { | |
2052 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); | |
2053 | return err; | |
2054 | } | |
2055 | ||
33a8eb8d TR |
2056 | pm_runtime_disable(&pdev->dev); |
2057 | ||
2058 | return 0; | |
2059 | } | |
2060 | ||
2061 | #ifdef CONFIG_PM | |
2062 | static int tegra_dc_suspend(struct device *dev) | |
2063 | { | |
2064 | struct tegra_dc *dc = dev_get_drvdata(dev); | |
2065 | int err; | |
2066 | ||
2067 | err = reset_control_assert(dc->rst); | |
2068 | if (err < 0) { | |
2069 | dev_err(dev, "failed to assert reset: %d\n", err); | |
2070 | return err; | |
2071 | } | |
9c012700 TR |
2072 | |
2073 | if (dc->soc->has_powergate) | |
2074 | tegra_powergate_power_off(dc->powergate); | |
2075 | ||
d8f4a9ed TR |
2076 | clk_disable_unprepare(dc->clk); |
2077 | ||
2078 | return 0; | |
2079 | } | |
2080 | ||
33a8eb8d TR |
2081 | static int tegra_dc_resume(struct device *dev) |
2082 | { | |
2083 | struct tegra_dc *dc = dev_get_drvdata(dev); | |
2084 | int err; | |
2085 | ||
2086 | if (dc->soc->has_powergate) { | |
2087 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, | |
2088 | dc->rst); | |
2089 | if (err < 0) { | |
2090 | dev_err(dev, "failed to power partition: %d\n", err); | |
2091 | return err; | |
2092 | } | |
2093 | } else { | |
2094 | err = clk_prepare_enable(dc->clk); | |
2095 | if (err < 0) { | |
2096 | dev_err(dev, "failed to enable clock: %d\n", err); | |
2097 | return err; | |
2098 | } | |
2099 | ||
2100 | err = reset_control_deassert(dc->rst); | |
2101 | if (err < 0) { | |
2102 | dev_err(dev, "failed to deassert reset: %d\n", err); | |
2103 | return err; | |
2104 | } | |
2105 | } | |
2106 | ||
2107 | return 0; | |
2108 | } | |
2109 | #endif | |
2110 | ||
2111 | static const struct dev_pm_ops tegra_dc_pm_ops = { | |
2112 | SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL) | |
2113 | }; | |
2114 | ||
d8f4a9ed TR |
2115 | struct platform_driver tegra_dc_driver = { |
2116 | .driver = { | |
2117 | .name = "tegra-dc", | |
d8f4a9ed | 2118 | .of_match_table = tegra_dc_of_match, |
33a8eb8d | 2119 | .pm = &tegra_dc_pm_ops, |
d8f4a9ed TR |
2120 | }, |
2121 | .probe = tegra_dc_probe, | |
2122 | .remove = tegra_dc_remove, | |
2123 | }; |