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drm/tegra: Remove host1x drm_bus implementation
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
ca48080a 12#include <linux/reset.h>
d8f4a9ed 13
de2ba664
AM		 14#include "dc.h"
15#include "drm.h"
16#include "gem.h"
d8f4a9ed 17
8620fc62
TR		 18struct tegra_dc_soc_info {
19 bool supports_interlacing;
20};
21
f34bc787
TR		 22struct tegra_plane {
23 struct drm_plane base;
24 unsigned int index;
d8f4a9ed
TR		 25};
26
f34bc787
TR		 27static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
28{
29 return container_of(plane, struct tegra_plane, base);
30}
31
10288eea
TR		 32static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
33{
34 /* assume no swapping of fetched data */
35 if (swap)
36 *swap = BYTE_SWAP_NOSWAP;
37
38 switch (format) {
39 case DRM_FORMAT_XBGR8888:
40 return WIN_COLOR_DEPTH_R8G8B8A8;
41
42 case DRM_FORMAT_XRGB8888:
43 return WIN_COLOR_DEPTH_B8G8R8A8;
44
45 case DRM_FORMAT_RGB565:
46 return WIN_COLOR_DEPTH_B5G6R5;
47
48 case DRM_FORMAT_UYVY:
49 return WIN_COLOR_DEPTH_YCbCr422;
50
51 case DRM_FORMAT_YUYV:
52 if (swap)
53 *swap = BYTE_SWAP_SWAP2;
54
55 return WIN_COLOR_DEPTH_YCbCr422;
56
57 case DRM_FORMAT_YUV420:
58 return WIN_COLOR_DEPTH_YCbCr420P;
59
60 case DRM_FORMAT_YUV422:
61 return WIN_COLOR_DEPTH_YCbCr422P;
62
63 default:
64 break;
65 }
66
67 WARN(1, "unsupported pixel format %u, using default\n", format);
68 return WIN_COLOR_DEPTH_B8G8R8A8;
69}
70
71static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
72{
73 switch (format) {
74 case WIN_COLOR_DEPTH_YCbCr422:
75 case WIN_COLOR_DEPTH_YUV422:
76 if (planar)
77 *planar = false;
78
79 return true;
80
81 case WIN_COLOR_DEPTH_YCbCr420P:
82 case WIN_COLOR_DEPTH_YUV420P:
83 case WIN_COLOR_DEPTH_YCbCr422P:
84 case WIN_COLOR_DEPTH_YUV422P:
85 case WIN_COLOR_DEPTH_YCbCr422R:
86 case WIN_COLOR_DEPTH_YUV422R:
87 case WIN_COLOR_DEPTH_YCbCr422RA:
88 case WIN_COLOR_DEPTH_YUV422RA:
89 if (planar)
90 *planar = true;
91
92 return true;
93 }
94
95 return false;
96}
97
98static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
99 unsigned int bpp)
100{
101 fixed20_12 outf = dfixed_init(out);
102 fixed20_12 inf = dfixed_init(in);
103 u32 dda_inc;
104 int max;
105
106 if (v)
107 max = 15;
108 else {
109 switch (bpp) {
110 case 2:
111 max = 8;
112 break;
113
114 default:
115 WARN_ON_ONCE(1);
116 /* fallthrough */
117 case 4:
118 max = 4;
119 break;
120 }
121 }
122
123 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
124 inf.full -= dfixed_const(1);
125
126 dda_inc = dfixed_div(inf, outf);
127 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
128
129 return dda_inc;
130}
131
132static inline u32 compute_initial_dda(unsigned int in)
133{
134 fixed20_12 inf = dfixed_init(in);
135 return dfixed_frac(inf);
136}
137
138static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
139 const struct tegra_dc_window *window)
140{
141 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
142 unsigned long value;
143 bool yuv, planar;
144
145 /*
146 * For YUV planar modes, the number of bytes per pixel takes into
147 * account only the luma component and therefore is 1.
148 */
149 yuv = tegra_dc_format_is_yuv(window->format, &planar);
150 if (!yuv)
151 bpp = window->bits_per_pixel / 8;
152 else
153 bpp = planar ? 1 : 2;
154
155 value = WINDOW_A_SELECT << index;
156 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
157
158 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
159 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
160
161 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
162 tegra_dc_writel(dc, value, DC_WIN_POSITION);
163
164 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
165 tegra_dc_writel(dc, value, DC_WIN_SIZE);
166
167 h_offset = window->src.x * bpp;
168 v_offset = window->src.y;
169 h_size = window->src.w * bpp;
170 v_size = window->src.h;
171
172 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
173 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
174
175 /*
176 * For DDA computations the number of bytes per pixel for YUV planar
177 * modes needs to take into account all Y, U and V components.
178 */
179 if (yuv && planar)
180 bpp = 2;
181
182 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
183 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
184
185 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
186 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
187
188 h_dda = compute_initial_dda(window->src.x);
189 v_dda = compute_initial_dda(window->src.y);
190
191 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
192 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
193
194 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
195 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
196
197 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
198
199 if (yuv && planar) {
200 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
201 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
202 value = window->stride[1] << 16 | window->stride[0];
203 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
204 } else {
205 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
206 }
207
208 if (window->bottom_up)
209 v_offset += window->src.h - 1;
210
211 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
212 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
213
214 if (window->tiled) {
215 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
216 DC_WIN_BUFFER_ADDR_MODE_TILE;
217 } else {
218 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
219 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
220 }
221
222 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
223
224 value = WIN_ENABLE;
225
226 if (yuv) {
227 /* setup default colorspace conversion coefficients */
228 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
229 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
230 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
231 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
232 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
233 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
234 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
235 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
236
237 value |= CSC_ENABLE;
238 } else if (window->bits_per_pixel < 24) {
239 value |= COLOR_EXPAND;
240 }
241
242 if (window->bottom_up)
243 value |= V_DIRECTION;
244
245 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
246
247 /*
248 * Disable blending and assume Window A is the bottom-most window,
249 * Window C is the top-most window and Window B is in the middle.
250 */
251 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
252 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
253
254 switch (index) {
255 case 0:
256 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
257 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
258 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
259 break;
260
261 case 1:
262 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
263 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
264 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
265 break;
266
267 case 2:
268 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
269 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
270 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
271 break;
272 }
273
274 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
275 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
276
277 return 0;
278}
279
f34bc787
TR		 280static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
281 struct drm_framebuffer *fb, int crtc_x,
282 int crtc_y, unsigned int crtc_w,
283 unsigned int crtc_h, uint32_t src_x,
284 uint32_t src_y, uint32_t src_w, uint32_t src_h)
285{
286 struct tegra_plane *p = to_tegra_plane(plane);
287 struct tegra_dc *dc = to_tegra_dc(crtc);
288 struct tegra_dc_window window;
289 unsigned int i;
290
291 memset(&window, 0, sizeof(window));
292 window.src.x = src_x >> 16;
293 window.src.y = src_y >> 16;
294 window.src.w = src_w >> 16;
295 window.src.h = src_h >> 16;
296 window.dst.x = crtc_x;
297 window.dst.y = crtc_y;
298 window.dst.w = crtc_w;
299 window.dst.h = crtc_h;
f925390e 300 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
f34bc787 301 window.bits_per_pixel = fb->bits_per_pixel;
db7fbdfd 302 window.bottom_up = tegra_fb_is_bottom_up(fb);
773af77f 303 window.tiled = tegra_fb_is_tiled(fb);
f34bc787
TR		 304
305 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 306 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 307
de2ba664 308 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 309
310 /*
311 * Tegra doesn't support different strides for U and V planes
312 * so we display a warning if the user tries to display a
313 * framebuffer with such a configuration.
314 */
315 if (i >= 2) {
316 if (fb->pitches[i] != window.stride[1])
317 DRM_ERROR("unsupported UV-plane configuration\n");
318 } else {
319 window.stride[i] = fb->pitches[i];
320 }
321 }
322
323 return tegra_dc_setup_window(dc, p->index, &window);
324}
325
326static int tegra_plane_disable(struct drm_plane *plane)
327{
328 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
329 struct tegra_plane *p = to_tegra_plane(plane);
330 unsigned long value;
331
2678aeba
TR		 332 if (!plane->crtc)
333 return 0;
334
f34bc787
TR		 335 value = WINDOW_A_SELECT << p->index;
336 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
337
338 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
339 value &= ~WIN_ENABLE;
340 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
341
342 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
343 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
344
345 return 0;
346}
347
348static void tegra_plane_destroy(struct drm_plane *plane)
349{
f002abc1
TR		 350 struct tegra_plane *p = to_tegra_plane(plane);
351
f34bc787
TR		 352 tegra_plane_disable(plane);
353 drm_plane_cleanup(plane);
f002abc1 354 kfree(p);
f34bc787
TR		 355}
356
357static const struct drm_plane_funcs tegra_plane_funcs = {
358 .update_plane = tegra_plane_update,
359 .disable_plane = tegra_plane_disable,
360 .destroy = tegra_plane_destroy,
361};
362
363static const uint32_t plane_formats[] = {
dbe4d9a7 364 DRM_FORMAT_XBGR8888,
f34bc787 365 DRM_FORMAT_XRGB8888,
dbe4d9a7 366 DRM_FORMAT_RGB565,
f34bc787 367 DRM_FORMAT_UYVY,
f925390e 368 DRM_FORMAT_YUYV,
f34bc787
TR		 369 DRM_FORMAT_YUV420,
370 DRM_FORMAT_YUV422,
371};
372
373static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
374{
375 unsigned int i;
376 int err = 0;
377
378 for (i = 0; i < 2; i++) {
379 struct tegra_plane *plane;
380
f002abc1 381 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
f34bc787
TR		 382 if (!plane)
383 return -ENOMEM;
384
385 plane->index = 1 + i;
386
387 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
388 &tegra_plane_funcs, plane_formats,
389 ARRAY_SIZE(plane_formats), false);
f002abc1
TR		 390 if (err < 0) {
391 kfree(plane);
f34bc787 392 return err;
f002abc1 393 }
f34bc787
TR		 394 }
395
396 return 0;
397}
398
23fb4740
TR		 399static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
400 struct drm_framebuffer *fb)
401{
de2ba664 402 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
db7fbdfd 403 unsigned int h_offset = 0, v_offset = 0;
f925390e 404 unsigned int format, swap;
23fb4740
TR		 405 unsigned long value;
406
407 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
408
409 value = fb->offsets[0] + y * fb->pitches[0] +
410 x * fb->bits_per_pixel / 8;
411
de2ba664 412 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 413 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
f925390e
TR		 414
415 format = tegra_dc_format(fb->pixel_format, &swap);
ed683aea 416 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
f925390e 417 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
23fb4740 418
773af77f
TR		 419 if (tegra_fb_is_tiled(fb)) {
420 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
421 DC_WIN_BUFFER_ADDR_MODE_TILE;
422 } else {
423 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
424 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
425 }
426
427 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
428
db7fbdfd
TR		 429 /* make sure bottom-up buffers are properly displayed */
430 if (tegra_fb_is_bottom_up(fb)) {
431 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 432 value |= V_DIRECTION;
db7fbdfd
TR		 433 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
434
435 v_offset += fb->height - 1;
436 } else {
437 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 438 value &= ~V_DIRECTION;
db7fbdfd
TR		 439 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
440 }
441
442 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
443 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
444
23fb4740
TR		 445 value = GENERAL_UPDATE | WIN_A_UPDATE;
446 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
447
448 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
449 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
450
451 return 0;
452}
453
6e5ff998
TR		 454void tegra_dc_enable_vblank(struct tegra_dc *dc)
455{
456 unsigned long value, flags;
457
458 spin_lock_irqsave(&dc->lock, flags);
459
460 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
461 value |= VBLANK_INT;
462 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
463
464 spin_unlock_irqrestore(&dc->lock, flags);
465}
466
467void tegra_dc_disable_vblank(struct tegra_dc *dc)
468{
469 unsigned long value, flags;
470
471 spin_lock_irqsave(&dc->lock, flags);
472
473 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
474 value &= ~VBLANK_INT;
475 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
476
477 spin_unlock_irqrestore(&dc->lock, flags);
478}
479
3c03c46a
TR		 480static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
481{
482 struct drm_device *drm = dc->base.dev;
483 struct drm_crtc *crtc = &dc->base;
3c03c46a 484 unsigned long flags, base;
de2ba664 485 struct tegra_bo *bo;
3c03c46a
TR		 486
487 if (!dc->event)
488 return;
489
f4510a27 490 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a
TR		 491
492 /* check if new start address has been latched */
493 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
494 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
495 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
496
f4510a27 497 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
3c03c46a
TR		 498 spin_lock_irqsave(&drm->event_lock, flags);
499 drm_send_vblank_event(drm, dc->pipe, dc->event);
500 drm_vblank_put(drm, dc->pipe);
501 dc->event = NULL;
502 spin_unlock_irqrestore(&drm->event_lock, flags);
503 }
504}
505
506void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
507{
508 struct tegra_dc *dc = to_tegra_dc(crtc);
509 struct drm_device *drm = crtc->dev;
510 unsigned long flags;
511
512 spin_lock_irqsave(&drm->event_lock, flags);
513
514 if (dc->event && dc->event->base.file_priv == file) {
515 dc->event->base.destroy(&dc->event->base);
516 drm_vblank_put(drm, dc->pipe);
517 dc->event = NULL;
518 }
519
520 spin_unlock_irqrestore(&drm->event_lock, flags);
521}
522
523static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 524 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a
TR		 525{
526 struct tegra_dc *dc = to_tegra_dc(crtc);
527 struct drm_device *drm = crtc->dev;
528
529 if (dc->event)
530 return -EBUSY;
531
532 if (event) {
533 event->pipe = dc->pipe;
534 dc->event = event;
535 drm_vblank_get(drm, dc->pipe);
536 }
537
538 tegra_dc_set_base(dc, 0, 0, fb);
f4510a27 539 crtc->primary->fb = fb;
3c03c46a
TR		 540
541 return 0;
542}
543
f002abc1
TR		 544static void drm_crtc_clear(struct drm_crtc *crtc)
545{
546 memset(crtc, 0, sizeof(*crtc));
547}
548
549static void tegra_dc_destroy(struct drm_crtc *crtc)
550{
551 drm_crtc_cleanup(crtc);
552 drm_crtc_clear(crtc);
553}
554
d8f4a9ed 555static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 556 .page_flip = tegra_dc_page_flip,
d8f4a9ed 557 .set_config = drm_crtc_helper_set_config,
f002abc1 558 .destroy = tegra_dc_destroy,
d8f4a9ed
TR		 559};
560
f34bc787 561static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 562{
f002abc1 563 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787
TR		 564 struct drm_device *drm = crtc->dev;
565 struct drm_plane *plane;
566
2b4c3661 567 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
f34bc787
TR		 568 if (plane->crtc == crtc) {
569 tegra_plane_disable(plane);
570 plane->crtc = NULL;
571
572 if (plane->fb) {
573 drm_framebuffer_unreference(plane->fb);
574 plane->fb = NULL;
575 }
576 }
577 }
f002abc1
TR		 578
579 drm_vblank_off(drm, dc->pipe);
d8f4a9ed
TR		 580}
581
582static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
583 const struct drm_display_mode *mode,
584 struct drm_display_mode *adjusted)
585{
586 return true;
587}
588
d8f4a9ed
TR		 589static int tegra_dc_set_timings(struct tegra_dc *dc,
590 struct drm_display_mode *mode)
591{
0444c0ff
TR		 592 unsigned int h_ref_to_sync = 1;
593 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 594 unsigned long value;
595
596 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
597
598 value = (v_ref_to_sync << 16) | h_ref_to_sync;
599 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
600
601 value = ((mode->vsync_end - mode->vsync_start) << 16) |
602 ((mode->hsync_end - mode->hsync_start) << 0);
603 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
604
d8f4a9ed
TR		 605 value = ((mode->vtotal - mode->vsync_end) << 16) |
606 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 607 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
608
609 value = ((mode->vsync_start - mode->vdisplay) << 16) |
610 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 611 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
612
613 value = (mode->vdisplay << 16) | mode->hdisplay;
614 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
615
616 return 0;
617}
618
619static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
dbb3f2f7 620 struct drm_display_mode *mode)
d8f4a9ed 621{
91eded9b 622 unsigned long pclk = mode->clock * 1000;
d8f4a9ed
TR		 623 struct tegra_dc *dc = to_tegra_dc(crtc);
624 struct tegra_output *output = NULL;
625 struct drm_encoder *encoder;
dbb3f2f7
TR		 626 unsigned int div;
627 u32 value;
d8f4a9ed
TR		 628 long err;
629
630 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
631 if (encoder->crtc == crtc) {
632 output = encoder_to_output(encoder);
633 break;
634 }
635
636 if (!output)
637 return -ENODEV;
638
639 /*
91eded9b
TR		 640 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
641 * respectively, each of which divides the base pll_d by 2.
d8f4a9ed 642 */
91eded9b 643 err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
d8f4a9ed
TR		 644 if (err < 0) {
645 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
646 return err;
647 }
648
91eded9b 649 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
d8f4a9ed 650
dbb3f2f7
TR		 651 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
652 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
d8f4a9ed
TR		 653
654 return 0;
655}
656
657static int tegra_crtc_mode_set(struct drm_crtc *crtc,
658 struct drm_display_mode *mode,
659 struct drm_display_mode *adjusted,
660 int x, int y, struct drm_framebuffer *old_fb)
661{
f4510a27 662 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
d8f4a9ed 663 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 664 struct tegra_dc_window window;
dbb3f2f7 665 u32 value;
d8f4a9ed
TR		 666 int err;
667
6e5ff998
TR		 668 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
669
dbb3f2f7 670 err = tegra_crtc_setup_clk(crtc, mode);
d8f4a9ed
TR		 671 if (err) {
672 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
673 return err;
674 }
675
676 /* program display mode */
677 tegra_dc_set_timings(dc, mode);
678
8620fc62
TR		 679 /* interlacing isn't supported yet, so disable it */
680 if (dc->soc->supports_interlacing) {
681 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
682 value &= ~INTERLACE_ENABLE;
683 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
684 }
685
d8f4a9ed 686 /* setup window parameters */
f34bc787
TR		 687 memset(&window, 0, sizeof(window));
688 window.src.x = 0;
689 window.src.y = 0;
690 window.src.w = mode->hdisplay;
691 window.src.h = mode->vdisplay;
692 window.dst.x = 0;
693 window.dst.y = 0;
694 window.dst.w = mode->hdisplay;
695 window.dst.h = mode->vdisplay;
f925390e
TR		 696 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
697 &window.swap);
f4510a27
MR		 698 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
699 window.stride[0] = crtc->primary->fb->pitches[0];
de2ba664 700 window.base[0] = bo->paddr;
f34bc787
TR		 701
702 err = tegra_dc_setup_window(dc, 0, &window);
703 if (err < 0)
704 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 705
d8f4a9ed
TR		 706 return 0;
707}
d8f4a9ed 708
23fb4740
TR		 709static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
710 struct drm_framebuffer *old_fb)
711{
712 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 713
f4510a27 714 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
d8f4a9ed
TR		 715}
716
717static void tegra_crtc_prepare(struct drm_crtc *crtc)
718{
719 struct tegra_dc *dc = to_tegra_dc(crtc);
720 unsigned int syncpt;
721 unsigned long value;
722
723 /* hardware initialization */
ca48080a 724 reset_control_deassert(dc->rst);
d8f4a9ed
TR		 725 usleep_range(10000, 20000);
726
727 if (dc->pipe)
728 syncpt = SYNCPT_VBLANK1;
729 else
730 syncpt = SYNCPT_VBLANK0;
731
732 /* initialize display controller */
733 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
734 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
735
736 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
737 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
738
739 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
740 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
741 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
742
d8f4a9ed
TR		 743 /* initialize timer */
744 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
745 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
746 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
747
748 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
749 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
750 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
751
d8f4a9ed
TR		 752 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
753 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 754
755 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
756 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 757}
758
759static void tegra_crtc_commit(struct drm_crtc *crtc)
760{
761 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 762 unsigned long value;
763
3b9e71ea
TR		 764 value = GENERAL_UPDATE | WIN_A_UPDATE;
765 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 766
3b9e71ea 767 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 768 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 769
6e5ff998 770 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 771}
772
773static void tegra_crtc_load_lut(struct drm_crtc *crtc)
774{
775}
776
777static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 778 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 779 .mode_fixup = tegra_crtc_mode_fixup,
780 .mode_set = tegra_crtc_mode_set,
23fb4740 781 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 782 .prepare = tegra_crtc_prepare,
783 .commit = tegra_crtc_commit,
784 .load_lut = tegra_crtc_load_lut,
785};
786
6e5ff998 787static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 788{
789 struct tegra_dc *dc = data;
790 unsigned long status;
791
792 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
793 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
794
795 if (status & FRAME_END_INT) {
796 /*
797 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
798 */
799 }
800
801 if (status & VBLANK_INT) {
802 /*
803 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
804 */
805 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 806 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 807 }
808
809 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
810 /*
811 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
812 */
813 }
814
815 return IRQ_HANDLED;
816}
817
818static int tegra_dc_show_regs(struct seq_file *s, void *data)
819{
820 struct drm_info_node *node = s->private;
821 struct tegra_dc *dc = node->info_ent->data;
822
823#define DUMP_REG(name) \
824 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
825 tegra_dc_readl(dc, name))
826
827 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
828 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
829 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
830 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
831 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
832 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
833 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
834 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
835 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
836 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
837 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
838 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
839 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
840 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
841 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
842 DUMP_REG(DC_CMD_SIGNAL_RAISE);
843 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
844 DUMP_REG(DC_CMD_INT_STATUS);
845 DUMP_REG(DC_CMD_INT_MASK);
846 DUMP_REG(DC_CMD_INT_ENABLE);
847 DUMP_REG(DC_CMD_INT_TYPE);
848 DUMP_REG(DC_CMD_INT_POLARITY);
849 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
850 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
851 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
852 DUMP_REG(DC_CMD_STATE_ACCESS);
853 DUMP_REG(DC_CMD_STATE_CONTROL);
854 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
855 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
856 DUMP_REG(DC_COM_CRC_CONTROL);
857 DUMP_REG(DC_COM_CRC_CHECKSUM);
858 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
859 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
860 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
861 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
862 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
863 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
864 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
865 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
866 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
867 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
868 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
869 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
870 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
871 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
872 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
873 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
874 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
875 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
876 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
877 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
878 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
879 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
880 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
881 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
882 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
883 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
884 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
885 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
886 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
887 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
888 DUMP_REG(DC_COM_SPI_CONTROL);
889 DUMP_REG(DC_COM_SPI_START_BYTE);
890 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
891 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
892 DUMP_REG(DC_COM_HSPI_CS_DC);
893 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
894 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
895 DUMP_REG(DC_COM_GPIO_CTRL);
896 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
897 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
898 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
899 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
900 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
901 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
902 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
903 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
904 DUMP_REG(DC_DISP_REF_TO_SYNC);
905 DUMP_REG(DC_DISP_SYNC_WIDTH);
906 DUMP_REG(DC_DISP_BACK_PORCH);
907 DUMP_REG(DC_DISP_ACTIVE);
908 DUMP_REG(DC_DISP_FRONT_PORCH);
909 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
910 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
911 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
912 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
913 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
914 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
915 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
916 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
917 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
918 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
919 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
920 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
921 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
922 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
923 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
924 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
925 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
926 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
927 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
928 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
929 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
930 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
931 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
932 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
933 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
934 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
935 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
936 DUMP_REG(DC_DISP_M0_CONTROL);
937 DUMP_REG(DC_DISP_M1_CONTROL);
938 DUMP_REG(DC_DISP_DI_CONTROL);
939 DUMP_REG(DC_DISP_PP_CONTROL);
940 DUMP_REG(DC_DISP_PP_SELECT_A);
941 DUMP_REG(DC_DISP_PP_SELECT_B);
942 DUMP_REG(DC_DISP_PP_SELECT_C);
943 DUMP_REG(DC_DISP_PP_SELECT_D);
944 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
945 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
946 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
947 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
948 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
949 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
950 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
951 DUMP_REG(DC_DISP_BORDER_COLOR);
952 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
953 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
954 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
955 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
956 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
957 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
958 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
959 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
960 DUMP_REG(DC_DISP_CURSOR_POSITION);
961 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
962 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
963 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
964 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
965 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
966 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
967 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
968 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
969 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
970 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
971 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
972 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
973 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
974 DUMP_REG(DC_DISP_SD_CONTROL);
975 DUMP_REG(DC_DISP_SD_CSC_COEFF);
976 DUMP_REG(DC_DISP_SD_LUT(0));
977 DUMP_REG(DC_DISP_SD_LUT(1));
978 DUMP_REG(DC_DISP_SD_LUT(2));
979 DUMP_REG(DC_DISP_SD_LUT(3));
980 DUMP_REG(DC_DISP_SD_LUT(4));
981 DUMP_REG(DC_DISP_SD_LUT(5));
982 DUMP_REG(DC_DISP_SD_LUT(6));
983 DUMP_REG(DC_DISP_SD_LUT(7));
984 DUMP_REG(DC_DISP_SD_LUT(8));
985 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
986 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
987 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
988 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
989 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
990 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
991 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
992 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
993 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
994 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
995 DUMP_REG(DC_DISP_SD_BL_TF(0));
996 DUMP_REG(DC_DISP_SD_BL_TF(1));
997 DUMP_REG(DC_DISP_SD_BL_TF(2));
998 DUMP_REG(DC_DISP_SD_BL_TF(3));
999 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1000 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1001 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1002 DUMP_REG(DC_WIN_WIN_OPTIONS);
1003 DUMP_REG(DC_WIN_BYTE_SWAP);
1004 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1005 DUMP_REG(DC_WIN_COLOR_DEPTH);
1006 DUMP_REG(DC_WIN_POSITION);
1007 DUMP_REG(DC_WIN_SIZE);
1008 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1009 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1010 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1011 DUMP_REG(DC_WIN_DDA_INC);
1012 DUMP_REG(DC_WIN_LINE_STRIDE);
1013 DUMP_REG(DC_WIN_BUF_STRIDE);
1014 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1015 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1016 DUMP_REG(DC_WIN_DV_CONTROL);
1017 DUMP_REG(DC_WIN_BLEND_NOKEY);
1018 DUMP_REG(DC_WIN_BLEND_1WIN);
1019 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1020 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1021 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1022 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1023 DUMP_REG(DC_WINBUF_START_ADDR);
1024 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1025 DUMP_REG(DC_WINBUF_START_ADDR_U);
1026 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1027 DUMP_REG(DC_WINBUF_START_ADDR_V);
1028 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1029 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1030 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1031 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1032 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1033 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1034 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1035 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1036 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1037
1038#undef DUMP_REG
1039
1040 return 0;
1041}
1042
1043static struct drm_info_list debugfs_files[] = {
1044 { "regs", tegra_dc_show_regs, 0, NULL },
1045};
1046
1047static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1048{
1049 unsigned int i;
1050 char *name;
1051 int err;
1052
1053 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1054 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1055 kfree(name);
1056
1057 if (!dc->debugfs)
1058 return -ENOMEM;
1059
1060 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1061 GFP_KERNEL);
1062 if (!dc->debugfs_files) {
1063 err = -ENOMEM;
1064 goto remove;
1065 }
1066
1067 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1068 dc->debugfs_files[i].data = dc;
1069
1070 err = drm_debugfs_create_files(dc->debugfs_files,
1071 ARRAY_SIZE(debugfs_files),
1072 dc->debugfs, minor);
1073 if (err < 0)
1074 goto free;
1075
1076 dc->minor = minor;
1077
1078 return 0;
1079
1080free:
1081 kfree(dc->debugfs_files);
1082 dc->debugfs_files = NULL;
1083remove:
1084 debugfs_remove(dc->debugfs);
1085 dc->debugfs = NULL;
1086
1087 return err;
1088}
1089
1090static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1091{
1092 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1093 dc->minor);
1094 dc->minor = NULL;
1095
1096 kfree(dc->debugfs_files);
1097 dc->debugfs_files = NULL;
1098
1099 debugfs_remove(dc->debugfs);
1100 dc->debugfs = NULL;
1101
1102 return 0;
1103}
1104
53fa7f72 1105static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1106{
9910f5c4 1107 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1108 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1109 int err;
1110
9910f5c4 1111 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
d8f4a9ed
TR		 1112 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1113 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1114
9910f5c4 1115 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1116 if (err < 0 && err != -ENODEV) {
1117 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1118 return err;
1119 }
1120
9910f5c4 1121 err = tegra_dc_add_planes(drm, dc);
f34bc787
TR		 1122 if (err < 0)
1123 return err;
1124
d8f4a9ed 1125 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1126 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1127 if (err < 0)
1128 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1129 }
1130
6e5ff998 1131 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1132 dev_name(dc->dev), dc);
1133 if (err < 0) {
1134 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1135 err);
1136 return err;
1137 }
1138
1139 return 0;
1140}
1141
53fa7f72 1142static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1143{
776dc384 1144 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1145 int err;
1146
1147 devm_free_irq(dc->dev, dc->irq, dc);
1148
1149 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1150 err = tegra_dc_debugfs_exit(dc);
1151 if (err < 0)
1152 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1153 }
1154
1155 err = tegra_dc_rgb_exit(dc);
1156 if (err) {
1157 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1158 return err;
1159 }
1160
1161 return 0;
1162}
1163
1164static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1165 .init = tegra_dc_init,
1166 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1167};
1168
8620fc62
TR		 1169static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1170 .supports_interlacing = false,
1171};
1172
1173static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1174 .supports_interlacing = false,
1175};
1176
1177static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1178 .supports_interlacing = true,
1179};
1180
1181static const struct of_device_id tegra_dc_of_match[] = {
1182 {
1183 .compatible = "nvidia,tegra124-dc",
1184 .data = &tegra124_dc_soc_info,
1185 }, {
1186 .compatible = "nvidia,tegra30-dc",
1187 .data = &tegra30_dc_soc_info,
1188 }, {
1189 .compatible = "nvidia,tegra20-dc",
1190 .data = &tegra20_dc_soc_info,
1191 }, {
1192 /* sentinel */
1193 }
1194};
1195
13411ddd
TR		 1196static int tegra_dc_parse_dt(struct tegra_dc *dc)
1197{
1198 struct device_node *np;
1199 u32 value = 0;
1200 int err;
1201
1202 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1203 if (err < 0) {
1204 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1205
1206 /*
1207 * If the nvidia,head property isn't present, try to find the
1208 * correct head number by looking up the position of this
1209 * display controller's node within the device tree. Assuming
1210 * that the nodes are ordered properly in the DTS file and
1211 * that the translation into a flattened device tree blob
1212 * preserves that ordering this will actually yield the right
1213 * head number.
1214 *
1215 * If those assumptions don't hold, this will still work for
1216 * cases where only a single display controller is used.
1217 */
1218 for_each_matching_node(np, tegra_dc_of_match) {
1219 if (np == dc->dev->of_node)
1220 break;
1221
1222 value++;
1223 }
1224 }
1225
1226 dc->pipe = value;
1227
1228 return 0;
1229}
1230
d8f4a9ed
TR		 1231static int tegra_dc_probe(struct platform_device *pdev)
1232{
8620fc62 1233 const struct of_device_id *id;
d8f4a9ed
TR		 1234 struct resource *regs;
1235 struct tegra_dc *dc;
1236 int err;
1237
1238 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1239 if (!dc)
1240 return -ENOMEM;
1241
8620fc62
TR		 1242 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1243 if (!id)
1244 return -ENODEV;
1245
6e5ff998 1246 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1247 INIT_LIST_HEAD(&dc->list);
1248 dc->dev = &pdev->dev;
8620fc62 1249 dc->soc = id->data;
d8f4a9ed 1250
13411ddd
TR		 1251 err = tegra_dc_parse_dt(dc);
1252 if (err < 0)
1253 return err;
1254
d8f4a9ed
TR		 1255 dc->clk = devm_clk_get(&pdev->dev, NULL);
1256 if (IS_ERR(dc->clk)) {
1257 dev_err(&pdev->dev, "failed to get clock\n");
1258 return PTR_ERR(dc->clk);
1259 }
1260
ca48080a
SW		 1261 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1262 if (IS_ERR(dc->rst)) {
1263 dev_err(&pdev->dev, "failed to get reset\n");
1264 return PTR_ERR(dc->rst);
1265 }
1266
d8f4a9ed
TR		 1267 err = clk_prepare_enable(dc->clk);
1268 if (err < 0)
1269 return err;
1270
1271 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1272 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1273 if (IS_ERR(dc->regs))
1274 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1275
1276 dc->irq = platform_get_irq(pdev, 0);
1277 if (dc->irq < 0) {
1278 dev_err(&pdev->dev, "failed to get IRQ\n");
1279 return -ENXIO;
1280 }
1281
776dc384
TR		 1282 INIT_LIST_HEAD(&dc->client.list);
1283 dc->client.ops = &dc_client_ops;
1284 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1285
1286 err = tegra_dc_rgb_probe(dc);
1287 if (err < 0 && err != -ENODEV) {
1288 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1289 return err;
1290 }
1291
776dc384 1292 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1293 if (err < 0) {
1294 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1295 err);
1296 return err;
1297 }
1298
1299 platform_set_drvdata(pdev, dc);
1300
1301 return 0;
1302}
1303
1304static int tegra_dc_remove(struct platform_device *pdev)
1305{
d8f4a9ed
TR		 1306 struct tegra_dc *dc = platform_get_drvdata(pdev);
1307 int err;
1308
776dc384 1309 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1310 if (err < 0) {
1311 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1312 err);
1313 return err;
1314 }
1315
59d29c0e
TR		 1316 err = tegra_dc_rgb_remove(dc);
1317 if (err < 0) {
1318 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1319 return err;
1320 }
1321
d8f4a9ed
TR		 1322 clk_disable_unprepare(dc->clk);
1323
1324 return 0;
1325}
1326
d8f4a9ed
TR		 1327struct platform_driver tegra_dc_driver = {
1328 .driver = {
1329 .name = "tegra-dc",
1330 .owner = THIS_MODULE,
1331 .of_match_table = tegra_dc_of_match,
1332 },
1333 .probe = tegra_dc_probe,
1334 .remove = tegra_dc_remove,
1335};
Linux kernel - Deliverables
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