Commit | Line | Data |
---|---|---|
d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
9eb9b220 | 11 | #include <linux/debugfs.h> |
df06b759 | 12 | #include <linux/iommu.h> |
ca48080a | 13 | #include <linux/reset.h> |
d8f4a9ed | 14 | |
9c012700 TR |
15 | #include <soc/tegra/pmc.h> |
16 | ||
de2ba664 AM |
17 | #include "dc.h" |
18 | #include "drm.h" | |
19 | #include "gem.h" | |
d8f4a9ed | 20 | |
9d44189f | 21 | #include <drm/drm_atomic.h> |
4aa3df71 | 22 | #include <drm/drm_atomic_helper.h> |
3cb9ae4f DV |
23 | #include <drm/drm_plane_helper.h> |
24 | ||
8620fc62 | 25 | struct tegra_dc_soc_info { |
42d0659b | 26 | bool supports_border_color; |
8620fc62 | 27 | bool supports_interlacing; |
e687651b | 28 | bool supports_cursor; |
c134f019 | 29 | bool supports_block_linear; |
d1f3e1e0 | 30 | unsigned int pitch_align; |
9c012700 | 31 | bool has_powergate; |
8620fc62 TR |
32 | }; |
33 | ||
f34bc787 TR |
34 | struct tegra_plane { |
35 | struct drm_plane base; | |
36 | unsigned int index; | |
d8f4a9ed TR |
37 | }; |
38 | ||
f34bc787 TR |
39 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
40 | { | |
41 | return container_of(plane, struct tegra_plane, base); | |
42 | } | |
43 | ||
205d48ed TR |
44 | static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index) |
45 | { | |
46 | u32 value = WIN_A_ACT_REQ << index; | |
47 | ||
48 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); | |
49 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); | |
50 | } | |
51 | ||
52 | static void tegra_dc_cursor_commit(struct tegra_dc *dc) | |
53 | { | |
54 | tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
55 | tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL); | |
56 | } | |
57 | ||
86df256f TR |
58 | /* |
59 | * Reads the active copy of a register. This takes the dc->lock spinlock to | |
60 | * prevent races with the VBLANK processing which also needs access to the | |
61 | * active copy of some registers. | |
62 | */ | |
63 | static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) | |
64 | { | |
65 | unsigned long flags; | |
66 | u32 value; | |
67 | ||
68 | spin_lock_irqsave(&dc->lock, flags); | |
69 | ||
70 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | |
71 | value = tegra_dc_readl(dc, offset); | |
72 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
73 | ||
74 | spin_unlock_irqrestore(&dc->lock, flags); | |
75 | return value; | |
76 | } | |
77 | ||
d700ba7a TR |
78 | /* |
79 | * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the | |
80 | * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. | |
81 | * Latching happens mmediately if the display controller is in STOP mode or | |
82 | * on the next frame boundary otherwise. | |
83 | * | |
84 | * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The | |
85 | * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits | |
86 | * are written. When the *_ACT_REQ bits are written, the ARM copy is latched | |
87 | * into the ACTIVE copy, either immediately if the display controller is in | |
88 | * STOP mode, or at the next frame boundary otherwise. | |
89 | */ | |
62b9e063 | 90 | void tegra_dc_commit(struct tegra_dc *dc) |
205d48ed TR |
91 | { |
92 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
93 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
94 | } | |
95 | ||
10288eea TR |
96 | static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap) |
97 | { | |
98 | /* assume no swapping of fetched data */ | |
99 | if (swap) | |
100 | *swap = BYTE_SWAP_NOSWAP; | |
101 | ||
102 | switch (format) { | |
103 | case DRM_FORMAT_XBGR8888: | |
104 | return WIN_COLOR_DEPTH_R8G8B8A8; | |
105 | ||
106 | case DRM_FORMAT_XRGB8888: | |
107 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
108 | ||
109 | case DRM_FORMAT_RGB565: | |
110 | return WIN_COLOR_DEPTH_B5G6R5; | |
111 | ||
112 | case DRM_FORMAT_UYVY: | |
113 | return WIN_COLOR_DEPTH_YCbCr422; | |
114 | ||
115 | case DRM_FORMAT_YUYV: | |
116 | if (swap) | |
117 | *swap = BYTE_SWAP_SWAP2; | |
118 | ||
119 | return WIN_COLOR_DEPTH_YCbCr422; | |
120 | ||
121 | case DRM_FORMAT_YUV420: | |
122 | return WIN_COLOR_DEPTH_YCbCr420P; | |
123 | ||
124 | case DRM_FORMAT_YUV422: | |
125 | return WIN_COLOR_DEPTH_YCbCr422P; | |
126 | ||
127 | default: | |
128 | break; | |
129 | } | |
130 | ||
131 | WARN(1, "unsupported pixel format %u, using default\n", format); | |
132 | return WIN_COLOR_DEPTH_B8G8R8A8; | |
133 | } | |
134 | ||
135 | static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) | |
136 | { | |
137 | switch (format) { | |
138 | case WIN_COLOR_DEPTH_YCbCr422: | |
139 | case WIN_COLOR_DEPTH_YUV422: | |
140 | if (planar) | |
141 | *planar = false; | |
142 | ||
143 | return true; | |
144 | ||
145 | case WIN_COLOR_DEPTH_YCbCr420P: | |
146 | case WIN_COLOR_DEPTH_YUV420P: | |
147 | case WIN_COLOR_DEPTH_YCbCr422P: | |
148 | case WIN_COLOR_DEPTH_YUV422P: | |
149 | case WIN_COLOR_DEPTH_YCbCr422R: | |
150 | case WIN_COLOR_DEPTH_YUV422R: | |
151 | case WIN_COLOR_DEPTH_YCbCr422RA: | |
152 | case WIN_COLOR_DEPTH_YUV422RA: | |
153 | if (planar) | |
154 | *planar = true; | |
155 | ||
156 | return true; | |
157 | } | |
158 | ||
fb35c6b6 TR |
159 | if (planar) |
160 | *planar = false; | |
161 | ||
10288eea TR |
162 | return false; |
163 | } | |
164 | ||
165 | static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, | |
166 | unsigned int bpp) | |
167 | { | |
168 | fixed20_12 outf = dfixed_init(out); | |
169 | fixed20_12 inf = dfixed_init(in); | |
170 | u32 dda_inc; | |
171 | int max; | |
172 | ||
173 | if (v) | |
174 | max = 15; | |
175 | else { | |
176 | switch (bpp) { | |
177 | case 2: | |
178 | max = 8; | |
179 | break; | |
180 | ||
181 | default: | |
182 | WARN_ON_ONCE(1); | |
183 | /* fallthrough */ | |
184 | case 4: | |
185 | max = 4; | |
186 | break; | |
187 | } | |
188 | } | |
189 | ||
190 | outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); | |
191 | inf.full -= dfixed_const(1); | |
192 | ||
193 | dda_inc = dfixed_div(inf, outf); | |
194 | dda_inc = min_t(u32, dda_inc, dfixed_const(max)); | |
195 | ||
196 | return dda_inc; | |
197 | } | |
198 | ||
199 | static inline u32 compute_initial_dda(unsigned int in) | |
200 | { | |
201 | fixed20_12 inf = dfixed_init(in); | |
202 | return dfixed_frac(inf); | |
203 | } | |
204 | ||
4aa3df71 TR |
205 | static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
206 | const struct tegra_dc_window *window) | |
10288eea TR |
207 | { |
208 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | |
93396d0f | 209 | unsigned long value, flags; |
10288eea TR |
210 | bool yuv, planar; |
211 | ||
212 | /* | |
213 | * For YUV planar modes, the number of bytes per pixel takes into | |
214 | * account only the luma component and therefore is 1. | |
215 | */ | |
216 | yuv = tegra_dc_format_is_yuv(window->format, &planar); | |
217 | if (!yuv) | |
218 | bpp = window->bits_per_pixel / 8; | |
219 | else | |
220 | bpp = planar ? 1 : 2; | |
221 | ||
93396d0f SP |
222 | spin_lock_irqsave(&dc->lock, flags); |
223 | ||
10288eea TR |
224 | value = WINDOW_A_SELECT << index; |
225 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
226 | ||
227 | tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); | |
228 | tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); | |
229 | ||
230 | value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); | |
231 | tegra_dc_writel(dc, value, DC_WIN_POSITION); | |
232 | ||
233 | value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); | |
234 | tegra_dc_writel(dc, value, DC_WIN_SIZE); | |
235 | ||
236 | h_offset = window->src.x * bpp; | |
237 | v_offset = window->src.y; | |
238 | h_size = window->src.w * bpp; | |
239 | v_size = window->src.h; | |
240 | ||
241 | value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); | |
242 | tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); | |
243 | ||
244 | /* | |
245 | * For DDA computations the number of bytes per pixel for YUV planar | |
246 | * modes needs to take into account all Y, U and V components. | |
247 | */ | |
248 | if (yuv && planar) | |
249 | bpp = 2; | |
250 | ||
251 | h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); | |
252 | v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); | |
253 | ||
254 | value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); | |
255 | tegra_dc_writel(dc, value, DC_WIN_DDA_INC); | |
256 | ||
257 | h_dda = compute_initial_dda(window->src.x); | |
258 | v_dda = compute_initial_dda(window->src.y); | |
259 | ||
260 | tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); | |
261 | tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); | |
262 | ||
263 | tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); | |
264 | tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); | |
265 | ||
266 | tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); | |
267 | ||
268 | if (yuv && planar) { | |
269 | tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); | |
270 | tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); | |
271 | value = window->stride[1] << 16 | window->stride[0]; | |
272 | tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); | |
273 | } else { | |
274 | tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); | |
275 | } | |
276 | ||
277 | if (window->bottom_up) | |
278 | v_offset += window->src.h - 1; | |
279 | ||
280 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
281 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
282 | ||
c134f019 TR |
283 | if (dc->soc->supports_block_linear) { |
284 | unsigned long height = window->tiling.value; | |
285 | ||
286 | switch (window->tiling.mode) { | |
287 | case TEGRA_BO_TILING_MODE_PITCH: | |
288 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
289 | break; | |
290 | ||
291 | case TEGRA_BO_TILING_MODE_TILED: | |
292 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
293 | break; | |
294 | ||
295 | case TEGRA_BO_TILING_MODE_BLOCK: | |
296 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
297 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
298 | break; | |
299 | } | |
300 | ||
301 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
10288eea | 302 | } else { |
c134f019 TR |
303 | switch (window->tiling.mode) { |
304 | case TEGRA_BO_TILING_MODE_PITCH: | |
305 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
306 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
307 | break; | |
10288eea | 308 | |
c134f019 TR |
309 | case TEGRA_BO_TILING_MODE_TILED: |
310 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
311 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
312 | break; | |
313 | ||
314 | case TEGRA_BO_TILING_MODE_BLOCK: | |
4aa3df71 TR |
315 | /* |
316 | * No need to handle this here because ->atomic_check | |
317 | * will already have filtered it out. | |
318 | */ | |
319 | break; | |
c134f019 TR |
320 | } |
321 | ||
322 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
323 | } | |
10288eea TR |
324 | |
325 | value = WIN_ENABLE; | |
326 | ||
327 | if (yuv) { | |
328 | /* setup default colorspace conversion coefficients */ | |
329 | tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); | |
330 | tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); | |
331 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); | |
332 | tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); | |
333 | tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); | |
334 | tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); | |
335 | tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); | |
336 | tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); | |
337 | ||
338 | value |= CSC_ENABLE; | |
339 | } else if (window->bits_per_pixel < 24) { | |
340 | value |= COLOR_EXPAND; | |
341 | } | |
342 | ||
343 | if (window->bottom_up) | |
344 | value |= V_DIRECTION; | |
345 | ||
346 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
347 | ||
348 | /* | |
349 | * Disable blending and assume Window A is the bottom-most window, | |
350 | * Window C is the top-most window and Window B is in the middle. | |
351 | */ | |
352 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); | |
353 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); | |
354 | ||
355 | switch (index) { | |
356 | case 0: | |
357 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); | |
358 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
359 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
360 | break; | |
361 | ||
362 | case 1: | |
363 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
364 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); | |
365 | tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); | |
366 | break; | |
367 | ||
368 | case 2: | |
369 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); | |
370 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); | |
371 | tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); | |
372 | break; | |
373 | } | |
374 | ||
205d48ed | 375 | tegra_dc_window_commit(dc, index); |
10288eea | 376 | |
93396d0f | 377 | spin_unlock_irqrestore(&dc->lock, flags); |
c7679306 TR |
378 | } |
379 | ||
380 | static void tegra_plane_destroy(struct drm_plane *plane) | |
381 | { | |
382 | struct tegra_plane *p = to_tegra_plane(plane); | |
383 | ||
384 | drm_plane_cleanup(plane); | |
385 | kfree(p); | |
386 | } | |
387 | ||
388 | static const u32 tegra_primary_plane_formats[] = { | |
389 | DRM_FORMAT_XBGR8888, | |
390 | DRM_FORMAT_XRGB8888, | |
391 | DRM_FORMAT_RGB565, | |
392 | }; | |
393 | ||
4aa3df71 | 394 | static void tegra_primary_plane_destroy(struct drm_plane *plane) |
c7679306 | 395 | { |
4aa3df71 TR |
396 | tegra_plane_destroy(plane); |
397 | } | |
398 | ||
399 | static const struct drm_plane_funcs tegra_primary_plane_funcs = { | |
400 | .update_plane = drm_plane_helper_update, | |
401 | .disable_plane = drm_plane_helper_disable, | |
402 | .destroy = tegra_primary_plane_destroy, | |
9d44189f TR |
403 | .reset = drm_atomic_helper_plane_reset, |
404 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
4aa3df71 TR |
405 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
406 | }; | |
407 | ||
408 | static int tegra_plane_prepare_fb(struct drm_plane *plane, | |
409 | struct drm_framebuffer *fb) | |
410 | { | |
411 | return 0; | |
412 | } | |
413 | ||
414 | static void tegra_plane_cleanup_fb(struct drm_plane *plane, | |
415 | struct drm_framebuffer *fb) | |
416 | { | |
417 | } | |
418 | ||
419 | static int tegra_plane_atomic_check(struct drm_plane *plane, | |
420 | struct drm_plane_state *state) | |
421 | { | |
422 | struct tegra_dc *dc = to_tegra_dc(state->crtc); | |
423 | struct tegra_bo_tiling tiling; | |
424 | int err; | |
425 | ||
426 | /* no need for further checks if the plane is being disabled */ | |
427 | if (!state->crtc) | |
428 | return 0; | |
429 | ||
430 | err = tegra_fb_get_tiling(state->fb, &tiling); | |
431 | if (err < 0) | |
432 | return err; | |
433 | ||
434 | if (tiling.mode == TEGRA_BO_TILING_MODE_BLOCK && | |
435 | !dc->soc->supports_block_linear) { | |
436 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
437 | return -EINVAL; | |
438 | } | |
439 | ||
440 | /* | |
441 | * Tegra doesn't support different strides for U and V planes so we | |
442 | * error out if the user tries to display a framebuffer with such a | |
443 | * configuration. | |
444 | */ | |
445 | if (drm_format_num_planes(state->fb->pixel_format) > 2) { | |
446 | if (state->fb->pitches[2] != state->fb->pitches[1]) { | |
447 | DRM_ERROR("unsupported UV-plane configuration\n"); | |
448 | return -EINVAL; | |
449 | } | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static void tegra_plane_atomic_update(struct drm_plane *plane, | |
456 | struct drm_plane_state *old_state) | |
457 | { | |
458 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); | |
459 | struct drm_framebuffer *fb = plane->state->fb; | |
c7679306 | 460 | struct tegra_plane *p = to_tegra_plane(plane); |
c7679306 | 461 | struct tegra_dc_window window; |
4aa3df71 | 462 | unsigned int i; |
c7679306 TR |
463 | int err; |
464 | ||
4aa3df71 TR |
465 | /* rien ne va plus */ |
466 | if (!plane->state->crtc || !plane->state->fb) | |
467 | return; | |
468 | ||
c7679306 | 469 | memset(&window, 0, sizeof(window)); |
4aa3df71 TR |
470 | window.src.x = plane->state->src_x >> 16; |
471 | window.src.y = plane->state->src_y >> 16; | |
472 | window.src.w = plane->state->src_w >> 16; | |
473 | window.src.h = plane->state->src_h >> 16; | |
474 | window.dst.x = plane->state->crtc_x; | |
475 | window.dst.y = plane->state->crtc_y; | |
476 | window.dst.w = plane->state->crtc_w; | |
477 | window.dst.h = plane->state->crtc_h; | |
c7679306 TR |
478 | window.format = tegra_dc_format(fb->pixel_format, &window.swap); |
479 | window.bits_per_pixel = fb->bits_per_pixel; | |
480 | window.bottom_up = tegra_fb_is_bottom_up(fb); | |
481 | ||
482 | err = tegra_fb_get_tiling(fb, &window.tiling); | |
4aa3df71 | 483 | WARN_ON(err < 0); |
c7679306 | 484 | |
4aa3df71 TR |
485 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { |
486 | struct tegra_bo *bo = tegra_fb_get_plane(fb, i); | |
c7679306 | 487 | |
4aa3df71 TR |
488 | window.base[i] = bo->paddr + fb->offsets[i]; |
489 | window.stride[i] = fb->pitches[i]; | |
490 | } | |
10288eea | 491 | |
4aa3df71 | 492 | tegra_dc_setup_window(dc, p->index, &window); |
10288eea TR |
493 | } |
494 | ||
4aa3df71 TR |
495 | static void tegra_plane_atomic_disable(struct drm_plane *plane, |
496 | struct drm_plane_state *old_state) | |
c7679306 | 497 | { |
4aa3df71 TR |
498 | struct tegra_plane *p = to_tegra_plane(plane); |
499 | struct tegra_dc *dc; | |
500 | unsigned long flags; | |
501 | u32 value; | |
502 | ||
503 | /* rien ne va plus */ | |
504 | if (!old_state || !old_state->crtc) | |
505 | return; | |
506 | ||
507 | dc = to_tegra_dc(old_state->crtc); | |
508 | ||
509 | spin_lock_irqsave(&dc->lock, flags); | |
510 | ||
511 | value = WINDOW_A_SELECT << p->index; | |
512 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | |
513 | ||
514 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
515 | value &= ~WIN_ENABLE; | |
516 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); | |
517 | ||
518 | tegra_dc_window_commit(dc, p->index); | |
519 | ||
520 | spin_unlock_irqrestore(&dc->lock, flags); | |
c7679306 TR |
521 | } |
522 | ||
4aa3df71 TR |
523 | static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = { |
524 | .prepare_fb = tegra_plane_prepare_fb, | |
525 | .cleanup_fb = tegra_plane_cleanup_fb, | |
526 | .atomic_check = tegra_plane_atomic_check, | |
527 | .atomic_update = tegra_plane_atomic_update, | |
528 | .atomic_disable = tegra_plane_atomic_disable, | |
c7679306 TR |
529 | }; |
530 | ||
531 | static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm, | |
532 | struct tegra_dc *dc) | |
533 | { | |
518e6227 TR |
534 | /* |
535 | * Ideally this would use drm_crtc_mask(), but that would require the | |
536 | * CRTC to already be in the mode_config's list of CRTCs. However, it | |
537 | * will only be added to that list in the drm_crtc_init_with_planes() | |
538 | * (in tegra_dc_init()), which in turn requires registration of these | |
539 | * planes. So we have ourselves a nice little chicken and egg problem | |
540 | * here. | |
541 | * | |
542 | * We work around this by manually creating the mask from the number | |
543 | * of CRTCs that have been registered, and should therefore always be | |
544 | * the same as drm_crtc_index() after registration. | |
545 | */ | |
546 | unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; | |
c7679306 TR |
547 | struct tegra_plane *plane; |
548 | unsigned int num_formats; | |
549 | const u32 *formats; | |
550 | int err; | |
551 | ||
552 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
553 | if (!plane) | |
554 | return ERR_PTR(-ENOMEM); | |
555 | ||
556 | num_formats = ARRAY_SIZE(tegra_primary_plane_formats); | |
557 | formats = tegra_primary_plane_formats; | |
558 | ||
518e6227 | 559 | err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, |
c7679306 TR |
560 | &tegra_primary_plane_funcs, formats, |
561 | num_formats, DRM_PLANE_TYPE_PRIMARY); | |
562 | if (err < 0) { | |
563 | kfree(plane); | |
564 | return ERR_PTR(err); | |
565 | } | |
566 | ||
4aa3df71 TR |
567 | drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs); |
568 | ||
c7679306 TR |
569 | return &plane->base; |
570 | } | |
571 | ||
572 | static const u32 tegra_cursor_plane_formats[] = { | |
573 | DRM_FORMAT_RGBA8888, | |
574 | }; | |
575 | ||
4aa3df71 TR |
576 | static int tegra_cursor_atomic_check(struct drm_plane *plane, |
577 | struct drm_plane_state *state) | |
c7679306 | 578 | { |
4aa3df71 TR |
579 | /* no need for further checks if the plane is being disabled */ |
580 | if (!state->crtc) | |
581 | return 0; | |
c7679306 TR |
582 | |
583 | /* scaling not supported for cursor */ | |
4aa3df71 TR |
584 | if ((state->src_w >> 16 != state->crtc_w) || |
585 | (state->src_h >> 16 != state->crtc_h)) | |
c7679306 TR |
586 | return -EINVAL; |
587 | ||
588 | /* only square cursors supported */ | |
4aa3df71 TR |
589 | if (state->src_w != state->src_h) |
590 | return -EINVAL; | |
591 | ||
592 | if (state->crtc_w != 32 && state->crtc_w != 64 && | |
593 | state->crtc_w != 128 && state->crtc_w != 256) | |
c7679306 TR |
594 | return -EINVAL; |
595 | ||
4aa3df71 TR |
596 | return 0; |
597 | } | |
598 | ||
599 | static void tegra_cursor_atomic_update(struct drm_plane *plane, | |
600 | struct drm_plane_state *old_state) | |
601 | { | |
602 | struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); | |
603 | struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); | |
604 | struct drm_plane_state *state = plane->state; | |
605 | u32 value = CURSOR_CLIP_DISPLAY; | |
606 | ||
607 | /* rien ne va plus */ | |
608 | if (!plane->state->crtc || !plane->state->fb) | |
609 | return; | |
610 | ||
611 | switch (state->crtc_w) { | |
c7679306 TR |
612 | case 32: |
613 | value |= CURSOR_SIZE_32x32; | |
614 | break; | |
615 | ||
616 | case 64: | |
617 | value |= CURSOR_SIZE_64x64; | |
618 | break; | |
619 | ||
620 | case 128: | |
621 | value |= CURSOR_SIZE_128x128; | |
622 | break; | |
623 | ||
624 | case 256: | |
625 | value |= CURSOR_SIZE_256x256; | |
626 | break; | |
627 | ||
628 | default: | |
4aa3df71 TR |
629 | WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, |
630 | state->crtc_h); | |
631 | return; | |
c7679306 TR |
632 | } |
633 | ||
634 | value |= (bo->paddr >> 10) & 0x3fffff; | |
635 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); | |
636 | ||
637 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
638 | value = (bo->paddr >> 32) & 0x3; | |
639 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); | |
640 | #endif | |
641 | ||
642 | /* enable cursor and set blend mode */ | |
643 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
644 | value |= CURSOR_ENABLE; | |
645 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
646 | ||
647 | value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); | |
648 | value &= ~CURSOR_DST_BLEND_MASK; | |
649 | value &= ~CURSOR_SRC_BLEND_MASK; | |
650 | value |= CURSOR_MODE_NORMAL; | |
651 | value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; | |
652 | value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; | |
653 | value |= CURSOR_ALPHA; | |
654 | tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); | |
655 | ||
656 | /* position the cursor */ | |
4aa3df71 | 657 | value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); |
c7679306 TR |
658 | tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); |
659 | ||
660 | /* apply changes */ | |
661 | tegra_dc_cursor_commit(dc); | |
662 | tegra_dc_commit(dc); | |
c7679306 TR |
663 | } |
664 | ||
4aa3df71 TR |
665 | static void tegra_cursor_atomic_disable(struct drm_plane *plane, |
666 | struct drm_plane_state *old_state) | |
c7679306 | 667 | { |
4aa3df71 | 668 | struct tegra_dc *dc; |
c7679306 TR |
669 | u32 value; |
670 | ||
4aa3df71 TR |
671 | /* rien ne va plus */ |
672 | if (!old_state || !old_state->crtc) | |
673 | return; | |
674 | ||
675 | dc = to_tegra_dc(old_state->crtc); | |
c7679306 TR |
676 | |
677 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
678 | value &= ~CURSOR_ENABLE; | |
679 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
680 | ||
681 | tegra_dc_cursor_commit(dc); | |
682 | tegra_dc_commit(dc); | |
c7679306 TR |
683 | } |
684 | ||
685 | static const struct drm_plane_funcs tegra_cursor_plane_funcs = { | |
4aa3df71 TR |
686 | .update_plane = drm_plane_helper_update, |
687 | .disable_plane = drm_plane_helper_disable, | |
c7679306 | 688 | .destroy = tegra_plane_destroy, |
9d44189f TR |
689 | .reset = drm_atomic_helper_plane_reset, |
690 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
4aa3df71 TR |
691 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
692 | }; | |
693 | ||
694 | static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { | |
695 | .prepare_fb = tegra_plane_prepare_fb, | |
696 | .cleanup_fb = tegra_plane_cleanup_fb, | |
697 | .atomic_check = tegra_cursor_atomic_check, | |
698 | .atomic_update = tegra_cursor_atomic_update, | |
699 | .atomic_disable = tegra_cursor_atomic_disable, | |
c7679306 TR |
700 | }; |
701 | ||
702 | static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, | |
703 | struct tegra_dc *dc) | |
704 | { | |
705 | struct tegra_plane *plane; | |
706 | unsigned int num_formats; | |
707 | const u32 *formats; | |
708 | int err; | |
709 | ||
710 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
711 | if (!plane) | |
712 | return ERR_PTR(-ENOMEM); | |
713 | ||
714 | num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); | |
715 | formats = tegra_cursor_plane_formats; | |
716 | ||
717 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, | |
718 | &tegra_cursor_plane_funcs, formats, | |
719 | num_formats, DRM_PLANE_TYPE_CURSOR); | |
720 | if (err < 0) { | |
721 | kfree(plane); | |
722 | return ERR_PTR(err); | |
723 | } | |
724 | ||
4aa3df71 | 725 | drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); |
f34bc787 | 726 | |
4aa3df71 | 727 | return &plane->base; |
f34bc787 TR |
728 | } |
729 | ||
c7679306 | 730 | static void tegra_overlay_plane_destroy(struct drm_plane *plane) |
f34bc787 | 731 | { |
c7679306 | 732 | tegra_plane_destroy(plane); |
f34bc787 TR |
733 | } |
734 | ||
c7679306 | 735 | static const struct drm_plane_funcs tegra_overlay_plane_funcs = { |
4aa3df71 TR |
736 | .update_plane = drm_plane_helper_update, |
737 | .disable_plane = drm_plane_helper_disable, | |
c7679306 | 738 | .destroy = tegra_overlay_plane_destroy, |
9d44189f TR |
739 | .reset = drm_atomic_helper_plane_reset, |
740 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
4aa3df71 | 741 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
f34bc787 TR |
742 | }; |
743 | ||
c7679306 | 744 | static const uint32_t tegra_overlay_plane_formats[] = { |
dbe4d9a7 | 745 | DRM_FORMAT_XBGR8888, |
f34bc787 | 746 | DRM_FORMAT_XRGB8888, |
dbe4d9a7 | 747 | DRM_FORMAT_RGB565, |
f34bc787 | 748 | DRM_FORMAT_UYVY, |
f925390e | 749 | DRM_FORMAT_YUYV, |
f34bc787 TR |
750 | DRM_FORMAT_YUV420, |
751 | DRM_FORMAT_YUV422, | |
752 | }; | |
753 | ||
4aa3df71 TR |
754 | static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = { |
755 | .prepare_fb = tegra_plane_prepare_fb, | |
756 | .cleanup_fb = tegra_plane_cleanup_fb, | |
757 | .atomic_check = tegra_plane_atomic_check, | |
758 | .atomic_update = tegra_plane_atomic_update, | |
759 | .atomic_disable = tegra_plane_atomic_disable, | |
760 | }; | |
761 | ||
c7679306 TR |
762 | static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, |
763 | struct tegra_dc *dc, | |
764 | unsigned int index) | |
f34bc787 | 765 | { |
c7679306 TR |
766 | struct tegra_plane *plane; |
767 | unsigned int num_formats; | |
768 | const u32 *formats; | |
769 | int err; | |
f34bc787 | 770 | |
c7679306 TR |
771 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); |
772 | if (!plane) | |
773 | return ERR_PTR(-ENOMEM); | |
f34bc787 | 774 | |
c7679306 | 775 | plane->index = index; |
f34bc787 | 776 | |
c7679306 TR |
777 | num_formats = ARRAY_SIZE(tegra_overlay_plane_formats); |
778 | formats = tegra_overlay_plane_formats; | |
f34bc787 | 779 | |
c7679306 TR |
780 | err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, |
781 | &tegra_overlay_plane_funcs, formats, | |
782 | num_formats, DRM_PLANE_TYPE_OVERLAY); | |
783 | if (err < 0) { | |
784 | kfree(plane); | |
785 | return ERR_PTR(err); | |
786 | } | |
787 | ||
4aa3df71 TR |
788 | drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs); |
789 | ||
c7679306 TR |
790 | return &plane->base; |
791 | } | |
792 | ||
793 | static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) | |
794 | { | |
795 | struct drm_plane *plane; | |
796 | unsigned int i; | |
797 | ||
798 | for (i = 0; i < 2; i++) { | |
799 | plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); | |
800 | if (IS_ERR(plane)) | |
801 | return PTR_ERR(plane); | |
f34bc787 TR |
802 | } |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
23fb4740 TR |
807 | static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, |
808 | struct drm_framebuffer *fb) | |
809 | { | |
de2ba664 | 810 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); |
db7fbdfd | 811 | unsigned int h_offset = 0, v_offset = 0; |
c134f019 | 812 | struct tegra_bo_tiling tiling; |
93396d0f | 813 | unsigned long value, flags; |
f925390e | 814 | unsigned int format, swap; |
c134f019 TR |
815 | int err; |
816 | ||
817 | err = tegra_fb_get_tiling(fb, &tiling); | |
818 | if (err < 0) | |
819 | return err; | |
23fb4740 | 820 | |
93396d0f SP |
821 | spin_lock_irqsave(&dc->lock, flags); |
822 | ||
23fb4740 TR |
823 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
824 | ||
825 | value = fb->offsets[0] + y * fb->pitches[0] + | |
826 | x * fb->bits_per_pixel / 8; | |
827 | ||
de2ba664 | 828 | tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); |
23fb4740 | 829 | tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); |
f925390e TR |
830 | |
831 | format = tegra_dc_format(fb->pixel_format, &swap); | |
ed683aea | 832 | tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); |
f925390e | 833 | tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP); |
23fb4740 | 834 | |
c134f019 TR |
835 | if (dc->soc->supports_block_linear) { |
836 | unsigned long height = tiling.value; | |
837 | ||
838 | switch (tiling.mode) { | |
839 | case TEGRA_BO_TILING_MODE_PITCH: | |
840 | value = DC_WINBUF_SURFACE_KIND_PITCH; | |
841 | break; | |
842 | ||
843 | case TEGRA_BO_TILING_MODE_TILED: | |
844 | value = DC_WINBUF_SURFACE_KIND_TILED; | |
845 | break; | |
846 | ||
847 | case TEGRA_BO_TILING_MODE_BLOCK: | |
848 | value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | | |
849 | DC_WINBUF_SURFACE_KIND_BLOCK; | |
850 | break; | |
851 | } | |
852 | ||
853 | tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); | |
773af77f | 854 | } else { |
c134f019 TR |
855 | switch (tiling.mode) { |
856 | case TEGRA_BO_TILING_MODE_PITCH: | |
857 | value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | | |
858 | DC_WIN_BUFFER_ADDR_MODE_LINEAR; | |
859 | break; | |
773af77f | 860 | |
c134f019 TR |
861 | case TEGRA_BO_TILING_MODE_TILED: |
862 | value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | | |
863 | DC_WIN_BUFFER_ADDR_MODE_TILE; | |
864 | break; | |
865 | ||
866 | case TEGRA_BO_TILING_MODE_BLOCK: | |
867 | DRM_ERROR("hardware doesn't support block linear mode\n"); | |
93396d0f | 868 | spin_unlock_irqrestore(&dc->lock, flags); |
c134f019 TR |
869 | return -EINVAL; |
870 | } | |
871 | ||
872 | tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); | |
873 | } | |
773af77f | 874 | |
db7fbdfd TR |
875 | /* make sure bottom-up buffers are properly displayed */ |
876 | if (tegra_fb_is_bottom_up(fb)) { | |
877 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 878 | value |= V_DIRECTION; |
db7fbdfd TR |
879 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
880 | ||
881 | v_offset += fb->height - 1; | |
882 | } else { | |
883 | value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); | |
eba66501 | 884 | value &= ~V_DIRECTION; |
db7fbdfd TR |
885 | tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); |
886 | } | |
887 | ||
888 | tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); | |
889 | tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); | |
890 | ||
23fb4740 | 891 | value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
205d48ed | 892 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); |
23fb4740 TR |
893 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
894 | ||
93396d0f SP |
895 | spin_unlock_irqrestore(&dc->lock, flags); |
896 | ||
23fb4740 TR |
897 | return 0; |
898 | } | |
899 | ||
6e5ff998 TR |
900 | void tegra_dc_enable_vblank(struct tegra_dc *dc) |
901 | { | |
902 | unsigned long value, flags; | |
903 | ||
904 | spin_lock_irqsave(&dc->lock, flags); | |
905 | ||
906 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
907 | value |= VBLANK_INT; | |
908 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
909 | ||
910 | spin_unlock_irqrestore(&dc->lock, flags); | |
911 | } | |
912 | ||
913 | void tegra_dc_disable_vblank(struct tegra_dc *dc) | |
914 | { | |
915 | unsigned long value, flags; | |
916 | ||
917 | spin_lock_irqsave(&dc->lock, flags); | |
918 | ||
919 | value = tegra_dc_readl(dc, DC_CMD_INT_MASK); | |
920 | value &= ~VBLANK_INT; | |
921 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
922 | ||
923 | spin_unlock_irqrestore(&dc->lock, flags); | |
924 | } | |
925 | ||
3c03c46a TR |
926 | static void tegra_dc_finish_page_flip(struct tegra_dc *dc) |
927 | { | |
928 | struct drm_device *drm = dc->base.dev; | |
929 | struct drm_crtc *crtc = &dc->base; | |
3c03c46a | 930 | unsigned long flags, base; |
de2ba664 | 931 | struct tegra_bo *bo; |
3c03c46a | 932 | |
6b59cc1c TR |
933 | spin_lock_irqsave(&drm->event_lock, flags); |
934 | ||
935 | if (!dc->event) { | |
936 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a | 937 | return; |
6b59cc1c | 938 | } |
3c03c46a | 939 | |
f4510a27 | 940 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
3c03c46a | 941 | |
8643bc6d | 942 | spin_lock(&dc->lock); |
93396d0f | 943 | |
3c03c46a | 944 | /* check if new start address has been latched */ |
93396d0f | 945 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
3c03c46a TR |
946 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
947 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | |
948 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | |
949 | ||
8643bc6d | 950 | spin_unlock(&dc->lock); |
93396d0f | 951 | |
f4510a27 | 952 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
ed7dae58 TR |
953 | drm_crtc_send_vblank_event(crtc, dc->event); |
954 | drm_crtc_vblank_put(crtc); | |
3c03c46a | 955 | dc->event = NULL; |
3c03c46a | 956 | } |
6b59cc1c TR |
957 | |
958 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
3c03c46a TR |
959 | } |
960 | ||
961 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | |
962 | { | |
963 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
964 | struct drm_device *drm = crtc->dev; | |
965 | unsigned long flags; | |
966 | ||
967 | spin_lock_irqsave(&drm->event_lock, flags); | |
968 | ||
969 | if (dc->event && dc->event->base.file_priv == file) { | |
970 | dc->event->base.destroy(&dc->event->base); | |
ed7dae58 | 971 | drm_crtc_vblank_put(crtc); |
3c03c46a TR |
972 | dc->event = NULL; |
973 | } | |
974 | ||
975 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
976 | } | |
977 | ||
978 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
a5b6f74e | 979 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
3c03c46a | 980 | { |
ed7dae58 | 981 | unsigned int pipe = drm_crtc_index(crtc); |
3c03c46a | 982 | struct tegra_dc *dc = to_tegra_dc(crtc); |
3c03c46a TR |
983 | |
984 | if (dc->event) | |
985 | return -EBUSY; | |
986 | ||
987 | if (event) { | |
ed7dae58 | 988 | event->pipe = pipe; |
3c03c46a | 989 | dc->event = event; |
ed7dae58 | 990 | drm_crtc_vblank_get(crtc); |
3c03c46a TR |
991 | } |
992 | ||
9d44189f TR |
993 | if (crtc->primary->state) |
994 | drm_atomic_set_fb_for_plane(crtc->primary->state, fb); | |
995 | ||
3c03c46a | 996 | tegra_dc_set_base(dc, 0, 0, fb); |
f4510a27 | 997 | crtc->primary->fb = fb; |
3c03c46a TR |
998 | |
999 | return 0; | |
1000 | } | |
1001 | ||
f002abc1 TR |
1002 | static void tegra_dc_destroy(struct drm_crtc *crtc) |
1003 | { | |
1004 | drm_crtc_cleanup(crtc); | |
f002abc1 TR |
1005 | } |
1006 | ||
d8f4a9ed | 1007 | static const struct drm_crtc_funcs tegra_crtc_funcs = { |
3c03c46a | 1008 | .page_flip = tegra_dc_page_flip, |
d8f4a9ed | 1009 | .set_config = drm_crtc_helper_set_config, |
f002abc1 | 1010 | .destroy = tegra_dc_destroy, |
9d44189f TR |
1011 | .reset = drm_atomic_helper_crtc_reset, |
1012 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
4aa3df71 | 1013 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, |
d8f4a9ed TR |
1014 | }; |
1015 | ||
86df256f TR |
1016 | static void tegra_dc_stop(struct tegra_dc *dc) |
1017 | { | |
1018 | u32 value; | |
1019 | ||
1020 | /* stop the display controller */ | |
1021 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1022 | value &= ~DISP_CTRL_MODE_MASK; | |
1023 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1024 | ||
1025 | tegra_dc_commit(dc); | |
1026 | } | |
1027 | ||
1028 | static bool tegra_dc_idle(struct tegra_dc *dc) | |
1029 | { | |
1030 | u32 value; | |
1031 | ||
1032 | value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); | |
1033 | ||
1034 | return (value & DISP_CTRL_MODE_MASK) == 0; | |
1035 | } | |
1036 | ||
1037 | static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) | |
1038 | { | |
1039 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1040 | ||
1041 | while (time_before(jiffies, timeout)) { | |
1042 | if (tegra_dc_idle(dc)) | |
1043 | return 0; | |
1044 | ||
1045 | usleep_range(1000, 2000); | |
1046 | } | |
1047 | ||
1048 | dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); | |
1049 | return -ETIMEDOUT; | |
1050 | } | |
1051 | ||
f34bc787 | 1052 | static void tegra_crtc_disable(struct drm_crtc *crtc) |
d8f4a9ed | 1053 | { |
f002abc1 | 1054 | struct tegra_dc *dc = to_tegra_dc(crtc); |
3b0e5855 | 1055 | u32 value; |
f002abc1 | 1056 | |
86df256f TR |
1057 | if (!tegra_dc_idle(dc)) { |
1058 | tegra_dc_stop(dc); | |
1059 | ||
1060 | /* | |
1061 | * Ignore the return value, there isn't anything useful to do | |
1062 | * in case this fails. | |
1063 | */ | |
1064 | tegra_dc_wait_idle(dc, 100); | |
1065 | } | |
36904adf | 1066 | |
3b0e5855 TR |
1067 | /* |
1068 | * This should really be part of the RGB encoder driver, but clearing | |
1069 | * these bits has the side-effect of stopping the display controller. | |
1070 | * When that happens no VBLANK interrupts will be raised. At the same | |
1071 | * time the encoder is disabled before the display controller, so the | |
1072 | * above code is always going to timeout waiting for the controller | |
1073 | * to go idle. | |
1074 | * | |
1075 | * Given the close coupling between the RGB encoder and the display | |
1076 | * controller doing it here is still kind of okay. None of the other | |
1077 | * encoder drivers require these bits to be cleared. | |
1078 | * | |
1079 | * XXX: Perhaps given that the display controller is switched off at | |
1080 | * this point anyway maybe clearing these bits isn't even useful for | |
1081 | * the RGB encoder? | |
1082 | */ | |
1083 | if (dc->rgb) { | |
1084 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); | |
1085 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1086 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); | |
1087 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
1088 | } | |
1089 | ||
8ff64c17 | 1090 | drm_crtc_vblank_off(crtc); |
c7679306 | 1091 | tegra_dc_commit(dc); |
d8f4a9ed TR |
1092 | } |
1093 | ||
1094 | static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, | |
1095 | const struct drm_display_mode *mode, | |
1096 | struct drm_display_mode *adjusted) | |
1097 | { | |
1098 | return true; | |
1099 | } | |
1100 | ||
d8f4a9ed TR |
1101 | static int tegra_dc_set_timings(struct tegra_dc *dc, |
1102 | struct drm_display_mode *mode) | |
1103 | { | |
0444c0ff TR |
1104 | unsigned int h_ref_to_sync = 1; |
1105 | unsigned int v_ref_to_sync = 1; | |
d8f4a9ed TR |
1106 | unsigned long value; |
1107 | ||
1108 | tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); | |
1109 | ||
1110 | value = (v_ref_to_sync << 16) | h_ref_to_sync; | |
1111 | tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); | |
1112 | ||
1113 | value = ((mode->vsync_end - mode->vsync_start) << 16) | | |
1114 | ((mode->hsync_end - mode->hsync_start) << 0); | |
1115 | tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); | |
1116 | ||
d8f4a9ed TR |
1117 | value = ((mode->vtotal - mode->vsync_end) << 16) | |
1118 | ((mode->htotal - mode->hsync_end) << 0); | |
40495089 LS |
1119 | tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); |
1120 | ||
1121 | value = ((mode->vsync_start - mode->vdisplay) << 16) | | |
1122 | ((mode->hsync_start - mode->hdisplay) << 0); | |
d8f4a9ed TR |
1123 | tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); |
1124 | ||
1125 | value = (mode->vdisplay << 16) | mode->hdisplay; | |
1126 | tegra_dc_writel(dc, value, DC_DISP_ACTIVE); | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
c5a107d3 TR |
1131 | int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent, |
1132 | unsigned long pclk, unsigned int div) | |
1133 | { | |
1134 | u32 value; | |
1135 | int err; | |
1136 | ||
1137 | err = clk_set_parent(dc->clk, parent); | |
1138 | if (err < 0) { | |
1139 | dev_err(dc->dev, "failed to set parent clock: %d\n", err); | |
1140 | return err; | |
1141 | } | |
1142 | ||
1143 | DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); | |
1144 | ||
1145 | value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; | |
1146 | tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
4aa3df71 | 1151 | static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc) |
d8f4a9ed | 1152 | { |
4aa3df71 | 1153 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
d8f4a9ed | 1154 | struct tegra_dc *dc = to_tegra_dc(crtc); |
dbb3f2f7 | 1155 | u32 value; |
d8f4a9ed | 1156 | |
d8f4a9ed TR |
1157 | /* program display mode */ |
1158 | tegra_dc_set_timings(dc, mode); | |
1159 | ||
42d0659b TR |
1160 | if (dc->soc->supports_border_color) |
1161 | tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); | |
1162 | ||
8620fc62 TR |
1163 | /* interlacing isn't supported yet, so disable it */ |
1164 | if (dc->soc->supports_interlacing) { | |
1165 | value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); | |
1166 | value &= ~INTERLACE_ENABLE; | |
1167 | tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); | |
1168 | } | |
d8f4a9ed TR |
1169 | } |
1170 | ||
1171 | static void tegra_crtc_prepare(struct drm_crtc *crtc) | |
1172 | { | |
1173 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
1174 | unsigned int syncpt; | |
1175 | unsigned long value; | |
1176 | ||
8ff64c17 TR |
1177 | drm_crtc_vblank_off(crtc); |
1178 | ||
d8f4a9ed TR |
1179 | if (dc->pipe) |
1180 | syncpt = SYNCPT_VBLANK1; | |
1181 | else | |
1182 | syncpt = SYNCPT_VBLANK0; | |
1183 | ||
1184 | /* initialize display controller */ | |
1185 | tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1186 | tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); | |
1187 | ||
1188 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; | |
1189 | tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); | |
1190 | ||
1191 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | | |
1192 | WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; | |
1193 | tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); | |
1194 | ||
d8f4a9ed TR |
1195 | /* initialize timer */ |
1196 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | | |
1197 | WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); | |
1198 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1199 | ||
1200 | value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | | |
1201 | WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); | |
1202 | tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1203 | ||
d8f4a9ed TR |
1204 | value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; |
1205 | tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); | |
6e5ff998 TR |
1206 | |
1207 | value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; | |
1208 | tegra_dc_writel(dc, value, DC_CMD_INT_MASK); | |
d8f4a9ed TR |
1209 | } |
1210 | ||
1211 | static void tegra_crtc_commit(struct drm_crtc *crtc) | |
1212 | { | |
1213 | struct tegra_dc *dc = to_tegra_dc(crtc); | |
d8f4a9ed | 1214 | |
8ff64c17 | 1215 | drm_crtc_vblank_on(crtc); |
205d48ed | 1216 | tegra_dc_commit(dc); |
d8f4a9ed TR |
1217 | } |
1218 | ||
4aa3df71 TR |
1219 | static int tegra_crtc_atomic_check(struct drm_crtc *crtc, |
1220 | struct drm_crtc_state *state) | |
1221 | { | |
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | static void tegra_crtc_atomic_begin(struct drm_crtc *crtc) | |
1226 | { | |
1227 | } | |
1228 | ||
1229 | static void tegra_crtc_atomic_flush(struct drm_crtc *crtc) | |
1230 | { | |
1231 | } | |
1232 | ||
d8f4a9ed | 1233 | static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { |
f34bc787 | 1234 | .disable = tegra_crtc_disable, |
d8f4a9ed | 1235 | .mode_fixup = tegra_crtc_mode_fixup, |
4aa3df71 TR |
1236 | .mode_set = drm_helper_crtc_mode_set, |
1237 | .mode_set_nofb = tegra_crtc_mode_set_nofb, | |
1238 | .mode_set_base = drm_helper_crtc_mode_set_base, | |
d8f4a9ed TR |
1239 | .prepare = tegra_crtc_prepare, |
1240 | .commit = tegra_crtc_commit, | |
4aa3df71 TR |
1241 | .atomic_check = tegra_crtc_atomic_check, |
1242 | .atomic_begin = tegra_crtc_atomic_begin, | |
1243 | .atomic_flush = tegra_crtc_atomic_flush, | |
d8f4a9ed TR |
1244 | }; |
1245 | ||
6e5ff998 | 1246 | static irqreturn_t tegra_dc_irq(int irq, void *data) |
d8f4a9ed TR |
1247 | { |
1248 | struct tegra_dc *dc = data; | |
1249 | unsigned long status; | |
1250 | ||
1251 | status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); | |
1252 | tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); | |
1253 | ||
1254 | if (status & FRAME_END_INT) { | |
1255 | /* | |
1256 | dev_dbg(dc->dev, "%s(): frame end\n", __func__); | |
1257 | */ | |
1258 | } | |
1259 | ||
1260 | if (status & VBLANK_INT) { | |
1261 | /* | |
1262 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | |
1263 | */ | |
ed7dae58 | 1264 | drm_crtc_handle_vblank(&dc->base); |
3c03c46a | 1265 | tegra_dc_finish_page_flip(dc); |
d8f4a9ed TR |
1266 | } |
1267 | ||
1268 | if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { | |
1269 | /* | |
1270 | dev_dbg(dc->dev, "%s(): underflow\n", __func__); | |
1271 | */ | |
1272 | } | |
1273 | ||
1274 | return IRQ_HANDLED; | |
1275 | } | |
1276 | ||
1277 | static int tegra_dc_show_regs(struct seq_file *s, void *data) | |
1278 | { | |
1279 | struct drm_info_node *node = s->private; | |
1280 | struct tegra_dc *dc = node->info_ent->data; | |
1281 | ||
1282 | #define DUMP_REG(name) \ | |
03a60569 | 1283 | seq_printf(s, "%-40s %#05x %08x\n", #name, name, \ |
d8f4a9ed TR |
1284 | tegra_dc_readl(dc, name)) |
1285 | ||
1286 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); | |
1287 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); | |
1288 | DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); | |
1289 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); | |
1290 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); | |
1291 | DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); | |
1292 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); | |
1293 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); | |
1294 | DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); | |
1295 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); | |
1296 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); | |
1297 | DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); | |
1298 | DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); | |
1299 | DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); | |
1300 | DUMP_REG(DC_CMD_DISPLAY_COMMAND); | |
1301 | DUMP_REG(DC_CMD_SIGNAL_RAISE); | |
1302 | DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); | |
1303 | DUMP_REG(DC_CMD_INT_STATUS); | |
1304 | DUMP_REG(DC_CMD_INT_MASK); | |
1305 | DUMP_REG(DC_CMD_INT_ENABLE); | |
1306 | DUMP_REG(DC_CMD_INT_TYPE); | |
1307 | DUMP_REG(DC_CMD_INT_POLARITY); | |
1308 | DUMP_REG(DC_CMD_SIGNAL_RAISE1); | |
1309 | DUMP_REG(DC_CMD_SIGNAL_RAISE2); | |
1310 | DUMP_REG(DC_CMD_SIGNAL_RAISE3); | |
1311 | DUMP_REG(DC_CMD_STATE_ACCESS); | |
1312 | DUMP_REG(DC_CMD_STATE_CONTROL); | |
1313 | DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); | |
1314 | DUMP_REG(DC_CMD_REG_ACT_CONTROL); | |
1315 | DUMP_REG(DC_COM_CRC_CONTROL); | |
1316 | DUMP_REG(DC_COM_CRC_CHECKSUM); | |
1317 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); | |
1318 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); | |
1319 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); | |
1320 | DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); | |
1321 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); | |
1322 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); | |
1323 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); | |
1324 | DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); | |
1325 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); | |
1326 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); | |
1327 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); | |
1328 | DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); | |
1329 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); | |
1330 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); | |
1331 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); | |
1332 | DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); | |
1333 | DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); | |
1334 | DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); | |
1335 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); | |
1336 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); | |
1337 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); | |
1338 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); | |
1339 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); | |
1340 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); | |
1341 | DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); | |
1342 | DUMP_REG(DC_COM_PIN_MISC_CONTROL); | |
1343 | DUMP_REG(DC_COM_PIN_PM0_CONTROL); | |
1344 | DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); | |
1345 | DUMP_REG(DC_COM_PIN_PM1_CONTROL); | |
1346 | DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); | |
1347 | DUMP_REG(DC_COM_SPI_CONTROL); | |
1348 | DUMP_REG(DC_COM_SPI_START_BYTE); | |
1349 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); | |
1350 | DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); | |
1351 | DUMP_REG(DC_COM_HSPI_CS_DC); | |
1352 | DUMP_REG(DC_COM_SCRATCH_REGISTER_A); | |
1353 | DUMP_REG(DC_COM_SCRATCH_REGISTER_B); | |
1354 | DUMP_REG(DC_COM_GPIO_CTRL); | |
1355 | DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); | |
1356 | DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); | |
1357 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); | |
1358 | DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); | |
1359 | DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); | |
1360 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); | |
1361 | DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); | |
1362 | DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); | |
1363 | DUMP_REG(DC_DISP_REF_TO_SYNC); | |
1364 | DUMP_REG(DC_DISP_SYNC_WIDTH); | |
1365 | DUMP_REG(DC_DISP_BACK_PORCH); | |
1366 | DUMP_REG(DC_DISP_ACTIVE); | |
1367 | DUMP_REG(DC_DISP_FRONT_PORCH); | |
1368 | DUMP_REG(DC_DISP_H_PULSE0_CONTROL); | |
1369 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); | |
1370 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); | |
1371 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); | |
1372 | DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); | |
1373 | DUMP_REG(DC_DISP_H_PULSE1_CONTROL); | |
1374 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); | |
1375 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); | |
1376 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); | |
1377 | DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); | |
1378 | DUMP_REG(DC_DISP_H_PULSE2_CONTROL); | |
1379 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); | |
1380 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); | |
1381 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); | |
1382 | DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); | |
1383 | DUMP_REG(DC_DISP_V_PULSE0_CONTROL); | |
1384 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); | |
1385 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); | |
1386 | DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); | |
1387 | DUMP_REG(DC_DISP_V_PULSE1_CONTROL); | |
1388 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); | |
1389 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); | |
1390 | DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); | |
1391 | DUMP_REG(DC_DISP_V_PULSE2_CONTROL); | |
1392 | DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); | |
1393 | DUMP_REG(DC_DISP_V_PULSE3_CONTROL); | |
1394 | DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); | |
1395 | DUMP_REG(DC_DISP_M0_CONTROL); | |
1396 | DUMP_REG(DC_DISP_M1_CONTROL); | |
1397 | DUMP_REG(DC_DISP_DI_CONTROL); | |
1398 | DUMP_REG(DC_DISP_PP_CONTROL); | |
1399 | DUMP_REG(DC_DISP_PP_SELECT_A); | |
1400 | DUMP_REG(DC_DISP_PP_SELECT_B); | |
1401 | DUMP_REG(DC_DISP_PP_SELECT_C); | |
1402 | DUMP_REG(DC_DISP_PP_SELECT_D); | |
1403 | DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); | |
1404 | DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); | |
1405 | DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); | |
1406 | DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); | |
1407 | DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); | |
1408 | DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); | |
1409 | DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); | |
1410 | DUMP_REG(DC_DISP_BORDER_COLOR); | |
1411 | DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); | |
1412 | DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); | |
1413 | DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); | |
1414 | DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); | |
1415 | DUMP_REG(DC_DISP_CURSOR_FOREGROUND); | |
1416 | DUMP_REG(DC_DISP_CURSOR_BACKGROUND); | |
1417 | DUMP_REG(DC_DISP_CURSOR_START_ADDR); | |
1418 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); | |
1419 | DUMP_REG(DC_DISP_CURSOR_POSITION); | |
1420 | DUMP_REG(DC_DISP_CURSOR_POSITION_NS); | |
1421 | DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); | |
1422 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); | |
1423 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); | |
1424 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); | |
1425 | DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); | |
1426 | DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); | |
1427 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); | |
1428 | DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); | |
1429 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); | |
1430 | DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); | |
1431 | DUMP_REG(DC_DISP_DAC_CRT_CTRL); | |
1432 | DUMP_REG(DC_DISP_DISP_MISC_CONTROL); | |
1433 | DUMP_REG(DC_DISP_SD_CONTROL); | |
1434 | DUMP_REG(DC_DISP_SD_CSC_COEFF); | |
1435 | DUMP_REG(DC_DISP_SD_LUT(0)); | |
1436 | DUMP_REG(DC_DISP_SD_LUT(1)); | |
1437 | DUMP_REG(DC_DISP_SD_LUT(2)); | |
1438 | DUMP_REG(DC_DISP_SD_LUT(3)); | |
1439 | DUMP_REG(DC_DISP_SD_LUT(4)); | |
1440 | DUMP_REG(DC_DISP_SD_LUT(5)); | |
1441 | DUMP_REG(DC_DISP_SD_LUT(6)); | |
1442 | DUMP_REG(DC_DISP_SD_LUT(7)); | |
1443 | DUMP_REG(DC_DISP_SD_LUT(8)); | |
1444 | DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); | |
1445 | DUMP_REG(DC_DISP_DC_PIXEL_COUNT); | |
1446 | DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); | |
1447 | DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); | |
1448 | DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); | |
1449 | DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); | |
1450 | DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); | |
1451 | DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); | |
1452 | DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); | |
1453 | DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); | |
1454 | DUMP_REG(DC_DISP_SD_BL_TF(0)); | |
1455 | DUMP_REG(DC_DISP_SD_BL_TF(1)); | |
1456 | DUMP_REG(DC_DISP_SD_BL_TF(2)); | |
1457 | DUMP_REG(DC_DISP_SD_BL_TF(3)); | |
1458 | DUMP_REG(DC_DISP_SD_BL_CONTROL); | |
1459 | DUMP_REG(DC_DISP_SD_HW_K_VALUES); | |
1460 | DUMP_REG(DC_DISP_SD_MAN_K_VALUES); | |
e687651b TR |
1461 | DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI); |
1462 | DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL); | |
d8f4a9ed TR |
1463 | DUMP_REG(DC_WIN_WIN_OPTIONS); |
1464 | DUMP_REG(DC_WIN_BYTE_SWAP); | |
1465 | DUMP_REG(DC_WIN_BUFFER_CONTROL); | |
1466 | DUMP_REG(DC_WIN_COLOR_DEPTH); | |
1467 | DUMP_REG(DC_WIN_POSITION); | |
1468 | DUMP_REG(DC_WIN_SIZE); | |
1469 | DUMP_REG(DC_WIN_PRESCALED_SIZE); | |
1470 | DUMP_REG(DC_WIN_H_INITIAL_DDA); | |
1471 | DUMP_REG(DC_WIN_V_INITIAL_DDA); | |
1472 | DUMP_REG(DC_WIN_DDA_INC); | |
1473 | DUMP_REG(DC_WIN_LINE_STRIDE); | |
1474 | DUMP_REG(DC_WIN_BUF_STRIDE); | |
1475 | DUMP_REG(DC_WIN_UV_BUF_STRIDE); | |
1476 | DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); | |
1477 | DUMP_REG(DC_WIN_DV_CONTROL); | |
1478 | DUMP_REG(DC_WIN_BLEND_NOKEY); | |
1479 | DUMP_REG(DC_WIN_BLEND_1WIN); | |
1480 | DUMP_REG(DC_WIN_BLEND_2WIN_X); | |
1481 | DUMP_REG(DC_WIN_BLEND_2WIN_Y); | |
f34bc787 | 1482 | DUMP_REG(DC_WIN_BLEND_3WIN_XY); |
d8f4a9ed TR |
1483 | DUMP_REG(DC_WIN_HP_FETCH_CONTROL); |
1484 | DUMP_REG(DC_WINBUF_START_ADDR); | |
1485 | DUMP_REG(DC_WINBUF_START_ADDR_NS); | |
1486 | DUMP_REG(DC_WINBUF_START_ADDR_U); | |
1487 | DUMP_REG(DC_WINBUF_START_ADDR_U_NS); | |
1488 | DUMP_REG(DC_WINBUF_START_ADDR_V); | |
1489 | DUMP_REG(DC_WINBUF_START_ADDR_V_NS); | |
1490 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); | |
1491 | DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); | |
1492 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); | |
1493 | DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); | |
1494 | DUMP_REG(DC_WINBUF_UFLOW_STATUS); | |
1495 | DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); | |
1496 | DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); | |
1497 | DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); | |
1498 | ||
1499 | #undef DUMP_REG | |
1500 | ||
1501 | return 0; | |
1502 | } | |
1503 | ||
1504 | static struct drm_info_list debugfs_files[] = { | |
1505 | { "regs", tegra_dc_show_regs, 0, NULL }, | |
1506 | }; | |
1507 | ||
1508 | static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) | |
1509 | { | |
1510 | unsigned int i; | |
1511 | char *name; | |
1512 | int err; | |
1513 | ||
1514 | name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); | |
1515 | dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); | |
1516 | kfree(name); | |
1517 | ||
1518 | if (!dc->debugfs) | |
1519 | return -ENOMEM; | |
1520 | ||
1521 | dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1522 | GFP_KERNEL); | |
1523 | if (!dc->debugfs_files) { | |
1524 | err = -ENOMEM; | |
1525 | goto remove; | |
1526 | } | |
1527 | ||
1528 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1529 | dc->debugfs_files[i].data = dc; | |
1530 | ||
1531 | err = drm_debugfs_create_files(dc->debugfs_files, | |
1532 | ARRAY_SIZE(debugfs_files), | |
1533 | dc->debugfs, minor); | |
1534 | if (err < 0) | |
1535 | goto free; | |
1536 | ||
1537 | dc->minor = minor; | |
1538 | ||
1539 | return 0; | |
1540 | ||
1541 | free: | |
1542 | kfree(dc->debugfs_files); | |
1543 | dc->debugfs_files = NULL; | |
1544 | remove: | |
1545 | debugfs_remove(dc->debugfs); | |
1546 | dc->debugfs = NULL; | |
1547 | ||
1548 | return err; | |
1549 | } | |
1550 | ||
1551 | static int tegra_dc_debugfs_exit(struct tegra_dc *dc) | |
1552 | { | |
1553 | drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1554 | dc->minor); | |
1555 | dc->minor = NULL; | |
1556 | ||
1557 | kfree(dc->debugfs_files); | |
1558 | dc->debugfs_files = NULL; | |
1559 | ||
1560 | debugfs_remove(dc->debugfs); | |
1561 | dc->debugfs = NULL; | |
1562 | ||
1563 | return 0; | |
1564 | } | |
1565 | ||
53fa7f72 | 1566 | static int tegra_dc_init(struct host1x_client *client) |
d8f4a9ed | 1567 | { |
9910f5c4 | 1568 | struct drm_device *drm = dev_get_drvdata(client->parent); |
776dc384 | 1569 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d1f3e1e0 | 1570 | struct tegra_drm *tegra = drm->dev_private; |
c7679306 TR |
1571 | struct drm_plane *primary = NULL; |
1572 | struct drm_plane *cursor = NULL; | |
d8f4a9ed TR |
1573 | int err; |
1574 | ||
df06b759 TR |
1575 | if (tegra->domain) { |
1576 | err = iommu_attach_device(tegra->domain, dc->dev); | |
1577 | if (err < 0) { | |
1578 | dev_err(dc->dev, "failed to attach to domain: %d\n", | |
1579 | err); | |
1580 | return err; | |
1581 | } | |
1582 | ||
1583 | dc->domain = tegra->domain; | |
1584 | } | |
1585 | ||
c7679306 TR |
1586 | primary = tegra_dc_primary_plane_create(drm, dc); |
1587 | if (IS_ERR(primary)) { | |
1588 | err = PTR_ERR(primary); | |
1589 | goto cleanup; | |
1590 | } | |
1591 | ||
1592 | if (dc->soc->supports_cursor) { | |
1593 | cursor = tegra_dc_cursor_plane_create(drm, dc); | |
1594 | if (IS_ERR(cursor)) { | |
1595 | err = PTR_ERR(cursor); | |
1596 | goto cleanup; | |
1597 | } | |
1598 | } | |
1599 | ||
1600 | err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, | |
1601 | &tegra_crtc_funcs); | |
1602 | if (err < 0) | |
1603 | goto cleanup; | |
1604 | ||
d8f4a9ed TR |
1605 | drm_mode_crtc_set_gamma_size(&dc->base, 256); |
1606 | drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); | |
1607 | ||
d1f3e1e0 TR |
1608 | /* |
1609 | * Keep track of the minimum pitch alignment across all display | |
1610 | * controllers. | |
1611 | */ | |
1612 | if (dc->soc->pitch_align > tegra->pitch_align) | |
1613 | tegra->pitch_align = dc->soc->pitch_align; | |
1614 | ||
9910f5c4 | 1615 | err = tegra_dc_rgb_init(drm, dc); |
d8f4a9ed TR |
1616 | if (err < 0 && err != -ENODEV) { |
1617 | dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); | |
c7679306 | 1618 | goto cleanup; |
d8f4a9ed TR |
1619 | } |
1620 | ||
9910f5c4 | 1621 | err = tegra_dc_add_planes(drm, dc); |
f34bc787 | 1622 | if (err < 0) |
c7679306 | 1623 | goto cleanup; |
f34bc787 | 1624 | |
d8f4a9ed | 1625 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
9910f5c4 | 1626 | err = tegra_dc_debugfs_init(dc, drm->primary); |
d8f4a9ed TR |
1627 | if (err < 0) |
1628 | dev_err(dc->dev, "debugfs setup failed: %d\n", err); | |
1629 | } | |
1630 | ||
6e5ff998 | 1631 | err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, |
d8f4a9ed TR |
1632 | dev_name(dc->dev), dc); |
1633 | if (err < 0) { | |
1634 | dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, | |
1635 | err); | |
c7679306 | 1636 | goto cleanup; |
d8f4a9ed TR |
1637 | } |
1638 | ||
1639 | return 0; | |
c7679306 TR |
1640 | |
1641 | cleanup: | |
1642 | if (cursor) | |
1643 | drm_plane_cleanup(cursor); | |
1644 | ||
1645 | if (primary) | |
1646 | drm_plane_cleanup(primary); | |
1647 | ||
1648 | if (tegra->domain) { | |
1649 | iommu_detach_device(tegra->domain, dc->dev); | |
1650 | dc->domain = NULL; | |
1651 | } | |
1652 | ||
1653 | return err; | |
d8f4a9ed TR |
1654 | } |
1655 | ||
53fa7f72 | 1656 | static int tegra_dc_exit(struct host1x_client *client) |
d8f4a9ed | 1657 | { |
776dc384 | 1658 | struct tegra_dc *dc = host1x_client_to_dc(client); |
d8f4a9ed TR |
1659 | int err; |
1660 | ||
1661 | devm_free_irq(dc->dev, dc->irq, dc); | |
1662 | ||
1663 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1664 | err = tegra_dc_debugfs_exit(dc); | |
1665 | if (err < 0) | |
1666 | dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); | |
1667 | } | |
1668 | ||
1669 | err = tegra_dc_rgb_exit(dc); | |
1670 | if (err) { | |
1671 | dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); | |
1672 | return err; | |
1673 | } | |
1674 | ||
df06b759 TR |
1675 | if (dc->domain) { |
1676 | iommu_detach_device(dc->domain, dc->dev); | |
1677 | dc->domain = NULL; | |
1678 | } | |
1679 | ||
d8f4a9ed TR |
1680 | return 0; |
1681 | } | |
1682 | ||
1683 | static const struct host1x_client_ops dc_client_ops = { | |
53fa7f72 TR |
1684 | .init = tegra_dc_init, |
1685 | .exit = tegra_dc_exit, | |
d8f4a9ed TR |
1686 | }; |
1687 | ||
8620fc62 | 1688 | static const struct tegra_dc_soc_info tegra20_dc_soc_info = { |
42d0659b | 1689 | .supports_border_color = true, |
8620fc62 | 1690 | .supports_interlacing = false, |
e687651b | 1691 | .supports_cursor = false, |
c134f019 | 1692 | .supports_block_linear = false, |
d1f3e1e0 | 1693 | .pitch_align = 8, |
9c012700 | 1694 | .has_powergate = false, |
8620fc62 TR |
1695 | }; |
1696 | ||
1697 | static const struct tegra_dc_soc_info tegra30_dc_soc_info = { | |
42d0659b | 1698 | .supports_border_color = true, |
8620fc62 | 1699 | .supports_interlacing = false, |
e687651b | 1700 | .supports_cursor = false, |
c134f019 | 1701 | .supports_block_linear = false, |
d1f3e1e0 | 1702 | .pitch_align = 8, |
9c012700 | 1703 | .has_powergate = false, |
d1f3e1e0 TR |
1704 | }; |
1705 | ||
1706 | static const struct tegra_dc_soc_info tegra114_dc_soc_info = { | |
42d0659b | 1707 | .supports_border_color = true, |
d1f3e1e0 TR |
1708 | .supports_interlacing = false, |
1709 | .supports_cursor = false, | |
1710 | .supports_block_linear = false, | |
1711 | .pitch_align = 64, | |
9c012700 | 1712 | .has_powergate = true, |
8620fc62 TR |
1713 | }; |
1714 | ||
1715 | static const struct tegra_dc_soc_info tegra124_dc_soc_info = { | |
42d0659b | 1716 | .supports_border_color = false, |
8620fc62 | 1717 | .supports_interlacing = true, |
e687651b | 1718 | .supports_cursor = true, |
c134f019 | 1719 | .supports_block_linear = true, |
d1f3e1e0 | 1720 | .pitch_align = 64, |
9c012700 | 1721 | .has_powergate = true, |
8620fc62 TR |
1722 | }; |
1723 | ||
1724 | static const struct of_device_id tegra_dc_of_match[] = { | |
1725 | { | |
1726 | .compatible = "nvidia,tegra124-dc", | |
1727 | .data = &tegra124_dc_soc_info, | |
9c012700 TR |
1728 | }, { |
1729 | .compatible = "nvidia,tegra114-dc", | |
1730 | .data = &tegra114_dc_soc_info, | |
8620fc62 TR |
1731 | }, { |
1732 | .compatible = "nvidia,tegra30-dc", | |
1733 | .data = &tegra30_dc_soc_info, | |
1734 | }, { | |
1735 | .compatible = "nvidia,tegra20-dc", | |
1736 | .data = &tegra20_dc_soc_info, | |
1737 | }, { | |
1738 | /* sentinel */ | |
1739 | } | |
1740 | }; | |
ef70728c | 1741 | MODULE_DEVICE_TABLE(of, tegra_dc_of_match); |
8620fc62 | 1742 | |
13411ddd TR |
1743 | static int tegra_dc_parse_dt(struct tegra_dc *dc) |
1744 | { | |
1745 | struct device_node *np; | |
1746 | u32 value = 0; | |
1747 | int err; | |
1748 | ||
1749 | err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); | |
1750 | if (err < 0) { | |
1751 | dev_err(dc->dev, "missing \"nvidia,head\" property\n"); | |
1752 | ||
1753 | /* | |
1754 | * If the nvidia,head property isn't present, try to find the | |
1755 | * correct head number by looking up the position of this | |
1756 | * display controller's node within the device tree. Assuming | |
1757 | * that the nodes are ordered properly in the DTS file and | |
1758 | * that the translation into a flattened device tree blob | |
1759 | * preserves that ordering this will actually yield the right | |
1760 | * head number. | |
1761 | * | |
1762 | * If those assumptions don't hold, this will still work for | |
1763 | * cases where only a single display controller is used. | |
1764 | */ | |
1765 | for_each_matching_node(np, tegra_dc_of_match) { | |
1766 | if (np == dc->dev->of_node) | |
1767 | break; | |
1768 | ||
1769 | value++; | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | dc->pipe = value; | |
1774 | ||
1775 | return 0; | |
1776 | } | |
1777 | ||
d8f4a9ed TR |
1778 | static int tegra_dc_probe(struct platform_device *pdev) |
1779 | { | |
8620fc62 | 1780 | const struct of_device_id *id; |
d8f4a9ed TR |
1781 | struct resource *regs; |
1782 | struct tegra_dc *dc; | |
1783 | int err; | |
1784 | ||
1785 | dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); | |
1786 | if (!dc) | |
1787 | return -ENOMEM; | |
1788 | ||
8620fc62 TR |
1789 | id = of_match_node(tegra_dc_of_match, pdev->dev.of_node); |
1790 | if (!id) | |
1791 | return -ENODEV; | |
1792 | ||
6e5ff998 | 1793 | spin_lock_init(&dc->lock); |
d8f4a9ed TR |
1794 | INIT_LIST_HEAD(&dc->list); |
1795 | dc->dev = &pdev->dev; | |
8620fc62 | 1796 | dc->soc = id->data; |
d8f4a9ed | 1797 | |
13411ddd TR |
1798 | err = tegra_dc_parse_dt(dc); |
1799 | if (err < 0) | |
1800 | return err; | |
1801 | ||
d8f4a9ed TR |
1802 | dc->clk = devm_clk_get(&pdev->dev, NULL); |
1803 | if (IS_ERR(dc->clk)) { | |
1804 | dev_err(&pdev->dev, "failed to get clock\n"); | |
1805 | return PTR_ERR(dc->clk); | |
1806 | } | |
1807 | ||
ca48080a SW |
1808 | dc->rst = devm_reset_control_get(&pdev->dev, "dc"); |
1809 | if (IS_ERR(dc->rst)) { | |
1810 | dev_err(&pdev->dev, "failed to get reset\n"); | |
1811 | return PTR_ERR(dc->rst); | |
1812 | } | |
1813 | ||
9c012700 TR |
1814 | if (dc->soc->has_powergate) { |
1815 | if (dc->pipe == 0) | |
1816 | dc->powergate = TEGRA_POWERGATE_DIS; | |
1817 | else | |
1818 | dc->powergate = TEGRA_POWERGATE_DISB; | |
1819 | ||
1820 | err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, | |
1821 | dc->rst); | |
1822 | if (err < 0) { | |
1823 | dev_err(&pdev->dev, "failed to power partition: %d\n", | |
1824 | err); | |
1825 | return err; | |
1826 | } | |
1827 | } else { | |
1828 | err = clk_prepare_enable(dc->clk); | |
1829 | if (err < 0) { | |
1830 | dev_err(&pdev->dev, "failed to enable clock: %d\n", | |
1831 | err); | |
1832 | return err; | |
1833 | } | |
1834 | ||
1835 | err = reset_control_deassert(dc->rst); | |
1836 | if (err < 0) { | |
1837 | dev_err(&pdev->dev, "failed to deassert reset: %d\n", | |
1838 | err); | |
1839 | return err; | |
1840 | } | |
1841 | } | |
d8f4a9ed TR |
1842 | |
1843 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1844 | dc->regs = devm_ioremap_resource(&pdev->dev, regs); |
1845 | if (IS_ERR(dc->regs)) | |
1846 | return PTR_ERR(dc->regs); | |
d8f4a9ed TR |
1847 | |
1848 | dc->irq = platform_get_irq(pdev, 0); | |
1849 | if (dc->irq < 0) { | |
1850 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
1851 | return -ENXIO; | |
1852 | } | |
1853 | ||
776dc384 TR |
1854 | INIT_LIST_HEAD(&dc->client.list); |
1855 | dc->client.ops = &dc_client_ops; | |
1856 | dc->client.dev = &pdev->dev; | |
d8f4a9ed TR |
1857 | |
1858 | err = tegra_dc_rgb_probe(dc); | |
1859 | if (err < 0 && err != -ENODEV) { | |
1860 | dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); | |
1861 | return err; | |
1862 | } | |
1863 | ||
776dc384 | 1864 | err = host1x_client_register(&dc->client); |
d8f4a9ed TR |
1865 | if (err < 0) { |
1866 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1867 | err); | |
1868 | return err; | |
1869 | } | |
1870 | ||
1871 | platform_set_drvdata(pdev, dc); | |
1872 | ||
1873 | return 0; | |
1874 | } | |
1875 | ||
1876 | static int tegra_dc_remove(struct platform_device *pdev) | |
1877 | { | |
d8f4a9ed TR |
1878 | struct tegra_dc *dc = platform_get_drvdata(pdev); |
1879 | int err; | |
1880 | ||
776dc384 | 1881 | err = host1x_client_unregister(&dc->client); |
d8f4a9ed TR |
1882 | if (err < 0) { |
1883 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1884 | err); | |
1885 | return err; | |
1886 | } | |
1887 | ||
59d29c0e TR |
1888 | err = tegra_dc_rgb_remove(dc); |
1889 | if (err < 0) { | |
1890 | dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); | |
1891 | return err; | |
1892 | } | |
1893 | ||
5482d75a | 1894 | reset_control_assert(dc->rst); |
9c012700 TR |
1895 | |
1896 | if (dc->soc->has_powergate) | |
1897 | tegra_powergate_power_off(dc->powergate); | |
1898 | ||
d8f4a9ed TR |
1899 | clk_disable_unprepare(dc->clk); |
1900 | ||
1901 | return 0; | |
1902 | } | |
1903 | ||
d8f4a9ed TR |
1904 | struct platform_driver tegra_dc_driver = { |
1905 | .driver = { | |
1906 | .name = "tegra-dc", | |
1907 | .owner = THIS_MODULE, | |
1908 | .of_match_table = tegra_dc_of_match, | |
1909 | }, | |
1910 | .probe = tegra_dc_probe, | |
1911 | .remove = tegra_dc_remove, | |
1912 | }; |