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drm/tegra: fb: Remove gratuituous blank line
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
ca48080a 13#include <linux/reset.h>
d8f4a9ed 14
9c012700
TR		 15#include <soc/tegra/pmc.h>
16
de2ba664
AM		 17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
d8f4a9ed 20
9d44189f 21#include <drm/drm_atomic.h>
4aa3df71 22#include <drm/drm_atomic_helper.h>
3cb9ae4f
DV		 23#include <drm/drm_plane_helper.h>
24
8620fc62 25struct tegra_dc_soc_info {
42d0659b 26 bool supports_border_color;
8620fc62 27 bool supports_interlacing;
e687651b 28 bool supports_cursor;
c134f019 29 bool supports_block_linear;
d1f3e1e0 30 unsigned int pitch_align;
9c012700 31 bool has_powergate;
8620fc62
TR		 32};
33
f34bc787
TR		 34struct tegra_plane {
35 struct drm_plane base;
36 unsigned int index;
d8f4a9ed
TR		 37};
38
f34bc787
TR		 39static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
40{
41 return container_of(plane, struct tegra_plane, base);
42}
43
ca915b10
TR		 44struct tegra_dc_state {
45 struct drm_crtc_state base;
46
47 struct clk *clk;
48 unsigned long pclk;
49 unsigned int div;
47802b09
TR		 50
51 u32 planes;
ca915b10
TR		 52};
53
54static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
55{
56 if (state)
57 return container_of(state, struct tegra_dc_state, base);
58
59 return NULL;
60}
61
8f604f8c
TR		 62struct tegra_plane_state {
63 struct drm_plane_state base;
64
65 struct tegra_bo_tiling tiling;
66 u32 format;
67 u32 swap;
68};
69
70static inline struct tegra_plane_state *
71to_tegra_plane_state(struct drm_plane_state *state)
72{
73 if (state)
74 return container_of(state, struct tegra_plane_state, base);
75
76 return NULL;
77}
78
791ddb1e
TR		 79static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
80{
81 stats->frames = 0;
82 stats->vblank = 0;
83 stats->underflow = 0;
84 stats->overflow = 0;
85}
86
86df256f
TR		 87/*
88 * Reads the active copy of a register. This takes the dc->lock spinlock to
89 * prevent races with the VBLANK processing which also needs access to the
90 * active copy of some registers.
91 */
92static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
93{
94 unsigned long flags;
95 u32 value;
96
97 spin_lock_irqsave(&dc->lock, flags);
98
99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
100 value = tegra_dc_readl(dc, offset);
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
102
103 spin_unlock_irqrestore(&dc->lock, flags);
104 return value;
105}
106
d700ba7a
TR		 107/*
108 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
109 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
110 * Latching happens mmediately if the display controller is in STOP mode or
111 * on the next frame boundary otherwise.
112 *
113 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
114 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
115 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
116 * into the ACTIVE copy, either immediately if the display controller is in
117 * STOP mode, or at the next frame boundary otherwise.
118 */
62b9e063 119void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 120{
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
123}
124
8f604f8c 125static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
10288eea
TR		 126{
127 /* assume no swapping of fetched data */
128 if (swap)
129 *swap = BYTE_SWAP_NOSWAP;
130
8f604f8c 131 switch (fourcc) {
10288eea 132 case DRM_FORMAT_XBGR8888:
8f604f8c
TR		 133 *format = WIN_COLOR_DEPTH_R8G8B8A8;
134 break;
10288eea
TR		 135
136 case DRM_FORMAT_XRGB8888:
8f604f8c
TR		 137 *format = WIN_COLOR_DEPTH_B8G8R8A8;
138 break;
10288eea
TR		 139
140 case DRM_FORMAT_RGB565:
8f604f8c
TR		 141 *format = WIN_COLOR_DEPTH_B5G6R5;
142 break;
10288eea
TR		 143
144 case DRM_FORMAT_UYVY:
8f604f8c
TR		 145 *format = WIN_COLOR_DEPTH_YCbCr422;
146 break;
10288eea
TR		 147
148 case DRM_FORMAT_YUYV:
149 if (swap)
150 *swap = BYTE_SWAP_SWAP2;
151
8f604f8c
TR		 152 *format = WIN_COLOR_DEPTH_YCbCr422;
153 break;
10288eea
TR		 154
155 case DRM_FORMAT_YUV420:
8f604f8c
TR		 156 *format = WIN_COLOR_DEPTH_YCbCr420P;
157 break;
10288eea
TR		 158
159 case DRM_FORMAT_YUV422:
8f604f8c
TR		 160 *format = WIN_COLOR_DEPTH_YCbCr422P;
161 break;
10288eea
TR		 162
163 default:
8f604f8c 164 return -EINVAL;
10288eea
TR		 165 }
166
8f604f8c 167 return 0;
10288eea
TR		 168}
169
170static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
171{
172 switch (format) {
173 case WIN_COLOR_DEPTH_YCbCr422:
174 case WIN_COLOR_DEPTH_YUV422:
175 if (planar)
176 *planar = false;
177
178 return true;
179
180 case WIN_COLOR_DEPTH_YCbCr420P:
181 case WIN_COLOR_DEPTH_YUV420P:
182 case WIN_COLOR_DEPTH_YCbCr422P:
183 case WIN_COLOR_DEPTH_YUV422P:
184 case WIN_COLOR_DEPTH_YCbCr422R:
185 case WIN_COLOR_DEPTH_YUV422R:
186 case WIN_COLOR_DEPTH_YCbCr422RA:
187 case WIN_COLOR_DEPTH_YUV422RA:
188 if (planar)
189 *planar = true;
190
191 return true;
192 }
193
fb35c6b6
TR		 194 if (planar)
195 *planar = false;
196
10288eea
TR		 197 return false;
198}
199
200static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
201 unsigned int bpp)
202{
203 fixed20_12 outf = dfixed_init(out);
204 fixed20_12 inf = dfixed_init(in);
205 u32 dda_inc;
206 int max;
207
208 if (v)
209 max = 15;
210 else {
211 switch (bpp) {
212 case 2:
213 max = 8;
214 break;
215
216 default:
217 WARN_ON_ONCE(1);
218 /* fallthrough */
219 case 4:
220 max = 4;
221 break;
222 }
223 }
224
225 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
226 inf.full -= dfixed_const(1);
227
228 dda_inc = dfixed_div(inf, outf);
229 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
230
231 return dda_inc;
232}
233
234static inline u32 compute_initial_dda(unsigned int in)
235{
236 fixed20_12 inf = dfixed_init(in);
237 return dfixed_frac(inf);
238}
239
4aa3df71
TR		 240static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
241 const struct tegra_dc_window *window)
10288eea
TR		 242{
243 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 244 unsigned long value, flags;
10288eea
TR		 245 bool yuv, planar;
246
247 /*
248 * For YUV planar modes, the number of bytes per pixel takes into
249 * account only the luma component and therefore is 1.
250 */
251 yuv = tegra_dc_format_is_yuv(window->format, &planar);
252 if (!yuv)
253 bpp = window->bits_per_pixel / 8;
254 else
255 bpp = planar ? 1 : 2;
256
93396d0f
SP		 257 spin_lock_irqsave(&dc->lock, flags);
258
10288eea
TR		 259 value = WINDOW_A_SELECT << index;
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
261
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
264
265 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
266 tegra_dc_writel(dc, value, DC_WIN_POSITION);
267
268 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
269 tegra_dc_writel(dc, value, DC_WIN_SIZE);
270
271 h_offset = window->src.x * bpp;
272 v_offset = window->src.y;
273 h_size = window->src.w * bpp;
274 v_size = window->src.h;
275
276 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
278
279 /*
280 * For DDA computations the number of bytes per pixel for YUV planar
281 * modes needs to take into account all Y, U and V components.
282 */
283 if (yuv && planar)
284 bpp = 2;
285
286 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
287 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
288
289 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
290 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
291
292 h_dda = compute_initial_dda(window->src.x);
293 v_dda = compute_initial_dda(window->src.y);
294
295 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
296 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
297
298 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
299 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
300
301 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
302
303 if (yuv && planar) {
304 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
305 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
306 value = window->stride[1] << 16 | window->stride[0];
307 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
308 } else {
309 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
310 }
311
312 if (window->bottom_up)
313 v_offset += window->src.h - 1;
314
315 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
316 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
317
c134f019
TR		 318 if (dc->soc->supports_block_linear) {
319 unsigned long height = window->tiling.value;
320
321 switch (window->tiling.mode) {
322 case TEGRA_BO_TILING_MODE_PITCH:
323 value = DC_WINBUF_SURFACE_KIND_PITCH;
324 break;
325
326 case TEGRA_BO_TILING_MODE_TILED:
327 value = DC_WINBUF_SURFACE_KIND_TILED;
328 break;
329
330 case TEGRA_BO_TILING_MODE_BLOCK:
331 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
332 DC_WINBUF_SURFACE_KIND_BLOCK;
333 break;
334 }
335
336 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 337 } else {
c134f019
TR		 338 switch (window->tiling.mode) {
339 case TEGRA_BO_TILING_MODE_PITCH:
340 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
341 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
342 break;
10288eea 343
c134f019
TR		 344 case TEGRA_BO_TILING_MODE_TILED:
345 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
346 DC_WIN_BUFFER_ADDR_MODE_TILE;
347 break;
348
349 case TEGRA_BO_TILING_MODE_BLOCK:
4aa3df71
TR		 350 /*
351 * No need to handle this here because ->atomic_check
352 * will already have filtered it out.
353 */
354 break;
c134f019
TR		 355 }
356
357 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
358 }
10288eea
TR		 359
360 value = WIN_ENABLE;
361
362 if (yuv) {
363 /* setup default colorspace conversion coefficients */
364 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
365 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
366 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
367 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
368 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
369 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
370 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
371 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
372
373 value |= CSC_ENABLE;
374 } else if (window->bits_per_pixel < 24) {
375 value |= COLOR_EXPAND;
376 }
377
378 if (window->bottom_up)
379 value |= V_DIRECTION;
380
381 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
382
383 /*
384 * Disable blending and assume Window A is the bottom-most window,
385 * Window C is the top-most window and Window B is in the middle.
386 */
387 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
389
390 switch (index) {
391 case 0:
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
395 break;
396
397 case 1:
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
399 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
401 break;
402
403 case 2:
404 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
407 break;
408 }
409
93396d0f 410 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 411}
412
413static void tegra_plane_destroy(struct drm_plane *plane)
414{
415 struct tegra_plane *p = to_tegra_plane(plane);
416
417 drm_plane_cleanup(plane);
418 kfree(p);
419}
420
421static const u32 tegra_primary_plane_formats[] = {
422 DRM_FORMAT_XBGR8888,
423 DRM_FORMAT_XRGB8888,
424 DRM_FORMAT_RGB565,
425};
426
4aa3df71 427static void tegra_primary_plane_destroy(struct drm_plane *plane)
c7679306 428{
4aa3df71
TR		 429 tegra_plane_destroy(plane);
430}
431
8f604f8c
TR		 432static void tegra_plane_reset(struct drm_plane *plane)
433{
434 struct tegra_plane_state *state;
435
3b59b7ac
TR		 436 if (plane->state)
437 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
8f604f8c
TR		 438
439 kfree(plane->state);
440 plane->state = NULL;
441
442 state = kzalloc(sizeof(*state), GFP_KERNEL);
443 if (state) {
444 plane->state = &state->base;
445 plane->state->plane = plane;
446 }
447}
448
449static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
450{
451 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
452 struct tegra_plane_state *copy;
453
3b59b7ac 454 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
8f604f8c
TR		 455 if (!copy)
456 return NULL;
457
3b59b7ac
TR		 458 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
459 copy->tiling = state->tiling;
460 copy->format = state->format;
461 copy->swap = state->swap;
8f604f8c
TR		 462
463 return &copy->base;
464}
465
466static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
467 struct drm_plane_state *state)
468{
3b59b7ac 469 __drm_atomic_helper_plane_destroy_state(plane, state);
8f604f8c
TR		 470 kfree(state);
471}
472
4aa3df71 473static const struct drm_plane_funcs tegra_primary_plane_funcs = {
07866963
TR		 474 .update_plane = drm_atomic_helper_update_plane,
475 .disable_plane = drm_atomic_helper_disable_plane,
4aa3df71 476 .destroy = tegra_primary_plane_destroy,
8f604f8c
TR		 477 .reset = tegra_plane_reset,
478 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
479 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 480};
481
482static int tegra_plane_prepare_fb(struct drm_plane *plane,
d136dfee
TU		 483 struct drm_framebuffer *fb,
484 const struct drm_plane_state *new_state)
4aa3df71
TR		 485{
486 return 0;
487}
488
489static void tegra_plane_cleanup_fb(struct drm_plane *plane,
d136dfee
TU		 490 struct drm_framebuffer *fb,
491 const struct drm_plane_state *old_fb)
4aa3df71
TR		 492{
493}
494
47802b09
TR		 495static int tegra_plane_state_add(struct tegra_plane *plane,
496 struct drm_plane_state *state)
497{
498 struct drm_crtc_state *crtc_state;
499 struct tegra_dc_state *tegra;
500
501 /* Propagate errors from allocation or locking failures. */
502 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
503 if (IS_ERR(crtc_state))
504 return PTR_ERR(crtc_state);
505
506 tegra = to_dc_state(crtc_state);
507
508 tegra->planes |= WIN_A_ACT_REQ << plane->index;
509
510 return 0;
511}
512
4aa3df71
TR		 513static int tegra_plane_atomic_check(struct drm_plane *plane,
514 struct drm_plane_state *state)
515{
8f604f8c
TR		 516 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
517 struct tegra_bo_tiling *tiling = &plane_state->tiling;
47802b09 518 struct tegra_plane *tegra = to_tegra_plane(plane);
4aa3df71 519 struct tegra_dc *dc = to_tegra_dc(state->crtc);
4aa3df71
TR		 520 int err;
521
522 /* no need for further checks if the plane is being disabled */
523 if (!state->crtc)
524 return 0;
525
8f604f8c
TR		 526 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
527 &plane_state->swap);
4aa3df71
TR		 528 if (err < 0)
529 return err;
530
8f604f8c
TR		 531 err = tegra_fb_get_tiling(state->fb, tiling);
532 if (err < 0)
533 return err;
534
535 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
4aa3df71
TR		 536 !dc->soc->supports_block_linear) {
537 DRM_ERROR("hardware doesn't support block linear mode\n");
538 return -EINVAL;
539 }
540
541 /*
542 * Tegra doesn't support different strides for U and V planes so we
543 * error out if the user tries to display a framebuffer with such a
544 * configuration.
545 */
546 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
547 if (state->fb->pitches[2] != state->fb->pitches[1]) {
548 DRM_ERROR("unsupported UV-plane configuration\n");
549 return -EINVAL;
550 }
551 }
552
47802b09
TR		 553 err = tegra_plane_state_add(tegra, state);
554 if (err < 0)
555 return err;
556
4aa3df71
TR		 557 return 0;
558}
559
560static void tegra_plane_atomic_update(struct drm_plane *plane,
561 struct drm_plane_state *old_state)
562{
8f604f8c 563 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
4aa3df71
TR		 564 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
565 struct drm_framebuffer *fb = plane->state->fb;
c7679306 566 struct tegra_plane *p = to_tegra_plane(plane);
c7679306 567 struct tegra_dc_window window;
4aa3df71 568 unsigned int i;
c7679306 569
4aa3df71
TR		 570 /* rien ne va plus */
571 if (!plane->state->crtc || !plane->state->fb)
572 return;
573
c7679306 574 memset(&window, 0, sizeof(window));
4aa3df71
TR		 575 window.src.x = plane->state->src_x >> 16;
576 window.src.y = plane->state->src_y >> 16;
577 window.src.w = plane->state->src_w >> 16;
578 window.src.h = plane->state->src_h >> 16;
579 window.dst.x = plane->state->crtc_x;
580 window.dst.y = plane->state->crtc_y;
581 window.dst.w = plane->state->crtc_w;
582 window.dst.h = plane->state->crtc_h;
c7679306
TR		 583 window.bits_per_pixel = fb->bits_per_pixel;
584 window.bottom_up = tegra_fb_is_bottom_up(fb);
585
8f604f8c
TR		 586 /* copy from state */
587 window.tiling = state->tiling;
588 window.format = state->format;
589 window.swap = state->swap;
c7679306 590
4aa3df71
TR		 591 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
592 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
c7679306 593
4aa3df71
TR		 594 window.base[i] = bo->paddr + fb->offsets[i];
595 window.stride[i] = fb->pitches[i];
596 }
10288eea 597
4aa3df71 598 tegra_dc_setup_window(dc, p->index, &window);
10288eea
TR		 599}
600
4aa3df71
TR		 601static void tegra_plane_atomic_disable(struct drm_plane *plane,
602 struct drm_plane_state *old_state)
c7679306 603{
4aa3df71
TR		 604 struct tegra_plane *p = to_tegra_plane(plane);
605 struct tegra_dc *dc;
606 unsigned long flags;
607 u32 value;
608
609 /* rien ne va plus */
610 if (!old_state || !old_state->crtc)
611 return;
612
613 dc = to_tegra_dc(old_state->crtc);
614
615 spin_lock_irqsave(&dc->lock, flags);
616
617 value = WINDOW_A_SELECT << p->index;
618 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
619
620 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
621 value &= ~WIN_ENABLE;
622 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
623
4aa3df71 624 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 625}
626
4aa3df71
TR		 627static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
628 .prepare_fb = tegra_plane_prepare_fb,
629 .cleanup_fb = tegra_plane_cleanup_fb,
630 .atomic_check = tegra_plane_atomic_check,
631 .atomic_update = tegra_plane_atomic_update,
632 .atomic_disable = tegra_plane_atomic_disable,
c7679306
TR		 633};
634
635static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
636 struct tegra_dc *dc)
637{
518e6227
TR		 638 /*
639 * Ideally this would use drm_crtc_mask(), but that would require the
640 * CRTC to already be in the mode_config's list of CRTCs. However, it
641 * will only be added to that list in the drm_crtc_init_with_planes()
642 * (in tegra_dc_init()), which in turn requires registration of these
643 * planes. So we have ourselves a nice little chicken and egg problem
644 * here.
645 *
646 * We work around this by manually creating the mask from the number
647 * of CRTCs that have been registered, and should therefore always be
648 * the same as drm_crtc_index() after registration.
649 */
650 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 651 struct tegra_plane *plane;
652 unsigned int num_formats;
653 const u32 *formats;
654 int err;
655
656 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
657 if (!plane)
658 return ERR_PTR(-ENOMEM);
659
660 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
661 formats = tegra_primary_plane_formats;
662
518e6227 663 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306
TR		 664 &tegra_primary_plane_funcs, formats,
665 num_formats, DRM_PLANE_TYPE_PRIMARY);
666 if (err < 0) {
667 kfree(plane);
668 return ERR_PTR(err);
669 }
670
4aa3df71
TR		 671 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
672
c7679306
TR		 673 return &plane->base;
674}
675
676static const u32 tegra_cursor_plane_formats[] = {
677 DRM_FORMAT_RGBA8888,
678};
679
4aa3df71
TR		 680static int tegra_cursor_atomic_check(struct drm_plane *plane,
681 struct drm_plane_state *state)
c7679306 682{
47802b09
TR		 683 struct tegra_plane *tegra = to_tegra_plane(plane);
684 int err;
685
4aa3df71
TR		 686 /* no need for further checks if the plane is being disabled */
687 if (!state->crtc)
688 return 0;
c7679306
TR		 689
690 /* scaling not supported for cursor */
4aa3df71
TR		 691 if ((state->src_w >> 16 != state->crtc_w) ||
692 (state->src_h >> 16 != state->crtc_h))
c7679306
TR		 693 return -EINVAL;
694
695 /* only square cursors supported */
4aa3df71
TR		 696 if (state->src_w != state->src_h)
697 return -EINVAL;
698
699 if (state->crtc_w != 32 && state->crtc_w != 64 &&
700 state->crtc_w != 128 && state->crtc_w != 256)
c7679306
TR		 701 return -EINVAL;
702
47802b09
TR		 703 err = tegra_plane_state_add(tegra, state);
704 if (err < 0)
705 return err;
706
4aa3df71
TR		 707 return 0;
708}
709
710static void tegra_cursor_atomic_update(struct drm_plane *plane,
711 struct drm_plane_state *old_state)
712{
713 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
714 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
715 struct drm_plane_state *state = plane->state;
716 u32 value = CURSOR_CLIP_DISPLAY;
717
718 /* rien ne va plus */
719 if (!plane->state->crtc || !plane->state->fb)
720 return;
721
722 switch (state->crtc_w) {
c7679306
TR		 723 case 32:
724 value |= CURSOR_SIZE_32x32;
725 break;
726
727 case 64:
728 value |= CURSOR_SIZE_64x64;
729 break;
730
731 case 128:
732 value |= CURSOR_SIZE_128x128;
733 break;
734
735 case 256:
736 value |= CURSOR_SIZE_256x256;
737 break;
738
739 default:
4aa3df71
TR		 740 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
741 state->crtc_h);
742 return;
c7679306
TR		 743 }
744
745 value |= (bo->paddr >> 10) & 0x3fffff;
746 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
747
748#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
749 value = (bo->paddr >> 32) & 0x3;
750 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
751#endif
752
753 /* enable cursor and set blend mode */
754 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
755 value |= CURSOR_ENABLE;
756 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
757
758 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
759 value &= ~CURSOR_DST_BLEND_MASK;
760 value &= ~CURSOR_SRC_BLEND_MASK;
761 value |= CURSOR_MODE_NORMAL;
762 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
763 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
764 value |= CURSOR_ALPHA;
765 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
766
767 /* position the cursor */
4aa3df71 768 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
c7679306 769 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
c7679306
TR		 770}
771
4aa3df71
TR		 772static void tegra_cursor_atomic_disable(struct drm_plane *plane,
773 struct drm_plane_state *old_state)
c7679306 774{
4aa3df71 775 struct tegra_dc *dc;
c7679306
TR		 776 u32 value;
777
4aa3df71
TR		 778 /* rien ne va plus */
779 if (!old_state || !old_state->crtc)
780 return;
781
782 dc = to_tegra_dc(old_state->crtc);
c7679306
TR		 783
784 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
785 value &= ~CURSOR_ENABLE;
786 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
c7679306
TR		 787}
788
789static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
07866963
TR		 790 .update_plane = drm_atomic_helper_update_plane,
791 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 792 .destroy = tegra_plane_destroy,
8f604f8c
TR		 793 .reset = tegra_plane_reset,
794 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
795 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 796};
797
798static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
799 .prepare_fb = tegra_plane_prepare_fb,
800 .cleanup_fb = tegra_plane_cleanup_fb,
801 .atomic_check = tegra_cursor_atomic_check,
802 .atomic_update = tegra_cursor_atomic_update,
803 .atomic_disable = tegra_cursor_atomic_disable,
c7679306
TR		 804};
805
806static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
807 struct tegra_dc *dc)
808{
809 struct tegra_plane *plane;
810 unsigned int num_formats;
811 const u32 *formats;
812 int err;
813
814 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
815 if (!plane)
816 return ERR_PTR(-ENOMEM);
817
47802b09 818 /*
a1df3b24
TR		 819 * This index is kind of fake. The cursor isn't a regular plane, but
820 * its update and activation request bits in DC_CMD_STATE_CONTROL do
821 * use the same programming. Setting this fake index here allows the
822 * code in tegra_add_plane_state() to do the right thing without the
823 * need to special-casing the cursor plane.
47802b09
TR		 824 */
825 plane->index = 6;
826
c7679306
TR		 827 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
828 formats = tegra_cursor_plane_formats;
829
830 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
831 &tegra_cursor_plane_funcs, formats,
832 num_formats, DRM_PLANE_TYPE_CURSOR);
833 if (err < 0) {
834 kfree(plane);
835 return ERR_PTR(err);
836 }
837
4aa3df71 838 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
f34bc787 839
4aa3df71 840 return &plane->base;
f34bc787
TR		 841}
842
c7679306 843static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 844{
c7679306 845 tegra_plane_destroy(plane);
f34bc787
TR		 846}
847
c7679306 848static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
07866963
TR		 849 .update_plane = drm_atomic_helper_update_plane,
850 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 851 .destroy = tegra_overlay_plane_destroy,
8f604f8c
TR		 852 .reset = tegra_plane_reset,
853 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
854 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
f34bc787
TR		 855};
856
c7679306 857static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 858 DRM_FORMAT_XBGR8888,
f34bc787 859 DRM_FORMAT_XRGB8888,
dbe4d9a7 860 DRM_FORMAT_RGB565,
f34bc787 861 DRM_FORMAT_UYVY,
f925390e 862 DRM_FORMAT_YUYV,
f34bc787
TR		 863 DRM_FORMAT_YUV420,
864 DRM_FORMAT_YUV422,
865};
866
4aa3df71
TR		 867static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
868 .prepare_fb = tegra_plane_prepare_fb,
869 .cleanup_fb = tegra_plane_cleanup_fb,
870 .atomic_check = tegra_plane_atomic_check,
871 .atomic_update = tegra_plane_atomic_update,
872 .atomic_disable = tegra_plane_atomic_disable,
873};
874
c7679306
TR		 875static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
876 struct tegra_dc *dc,
877 unsigned int index)
f34bc787 878{
c7679306
TR		 879 struct tegra_plane *plane;
880 unsigned int num_formats;
881 const u32 *formats;
882 int err;
f34bc787 883
c7679306
TR		 884 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
885 if (!plane)
886 return ERR_PTR(-ENOMEM);
f34bc787 887
c7679306 888 plane->index = index;
f34bc787 889
c7679306
TR		 890 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
891 formats = tegra_overlay_plane_formats;
f34bc787 892
c7679306
TR		 893 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
894 &tegra_overlay_plane_funcs, formats,
895 num_formats, DRM_PLANE_TYPE_OVERLAY);
896 if (err < 0) {
897 kfree(plane);
898 return ERR_PTR(err);
899 }
900
4aa3df71
TR		 901 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
902
c7679306
TR		 903 return &plane->base;
904}
905
906static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
907{
908 struct drm_plane *plane;
909 unsigned int i;
910
911 for (i = 0; i < 2; i++) {
912 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
913 if (IS_ERR(plane))
914 return PTR_ERR(plane);
f34bc787
TR		 915 }
916
917 return 0;
918}
919
42e9ce05
TR		 920u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
921{
922 if (dc->syncpt)
923 return host1x_syncpt_read(dc->syncpt);
924
925 /* fallback to software emulated VBLANK counter */
926 return drm_crtc_vblank_count(&dc->base);
927}
928
6e5ff998
TR		 929void tegra_dc_enable_vblank(struct tegra_dc *dc)
930{
931 unsigned long value, flags;
932
933 spin_lock_irqsave(&dc->lock, flags);
934
935 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
936 value |= VBLANK_INT;
937 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
938
939 spin_unlock_irqrestore(&dc->lock, flags);
940}
941
942void tegra_dc_disable_vblank(struct tegra_dc *dc)
943{
944 unsigned long value, flags;
945
946 spin_lock_irqsave(&dc->lock, flags);
947
948 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
949 value &= ~VBLANK_INT;
950 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
951
952 spin_unlock_irqrestore(&dc->lock, flags);
953}
954
3c03c46a
TR		 955static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
956{
957 struct drm_device *drm = dc->base.dev;
958 struct drm_crtc *crtc = &dc->base;
3c03c46a 959 unsigned long flags, base;
de2ba664 960 struct tegra_bo *bo;
3c03c46a 961
6b59cc1c
TR		 962 spin_lock_irqsave(&drm->event_lock, flags);
963
964 if (!dc->event) {
965 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 966 return;
6b59cc1c 967 }
3c03c46a 968
f4510a27 969 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 970
8643bc6d 971 spin_lock(&dc->lock);
93396d0f 972
3c03c46a 973 /* check if new start address has been latched */
93396d0f 974 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 975 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
976 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
977 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
978
8643bc6d 979 spin_unlock(&dc->lock);
93396d0f 980
f4510a27 981 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 982 drm_crtc_send_vblank_event(crtc, dc->event);
983 drm_crtc_vblank_put(crtc);
3c03c46a 984 dc->event = NULL;
3c03c46a 985 }
6b59cc1c
TR		 986
987 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 988}
989
990void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
991{
992 struct tegra_dc *dc = to_tegra_dc(crtc);
993 struct drm_device *drm = crtc->dev;
994 unsigned long flags;
995
996 spin_lock_irqsave(&drm->event_lock, flags);
997
998 if (dc->event && dc->event->base.file_priv == file) {
999 dc->event->base.destroy(&dc->event->base);
ed7dae58 1000 drm_crtc_vblank_put(crtc);
3c03c46a
TR		 1001 dc->event = NULL;
1002 }
1003
1004 spin_unlock_irqrestore(&drm->event_lock, flags);
1005}
1006
f002abc1
TR		 1007static void tegra_dc_destroy(struct drm_crtc *crtc)
1008{
1009 drm_crtc_cleanup(crtc);
f002abc1
TR		 1010}
1011
ca915b10
TR		 1012static void tegra_crtc_reset(struct drm_crtc *crtc)
1013{
1014 struct tegra_dc_state *state;
1015
3b59b7ac
TR		 1016 if (crtc->state)
1017 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1018
ca915b10
TR		 1019 kfree(crtc->state);
1020 crtc->state = NULL;
1021
1022 state = kzalloc(sizeof(*state), GFP_KERNEL);
332bbe70 1023 if (state) {
ca915b10 1024 crtc->state = &state->base;
332bbe70
TR		 1025 crtc->state->crtc = crtc;
1026 }
31930d4d
TR		 1027
1028 drm_crtc_vblank_reset(crtc);
ca915b10
TR		 1029}
1030
1031static struct drm_crtc_state *
1032tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1033{
1034 struct tegra_dc_state *state = to_dc_state(crtc->state);
1035 struct tegra_dc_state *copy;
1036
3b59b7ac 1037 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
ca915b10
TR		 1038 if (!copy)
1039 return NULL;
1040
3b59b7ac
TR		 1041 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1042 copy->clk = state->clk;
1043 copy->pclk = state->pclk;
1044 copy->div = state->div;
1045 copy->planes = state->planes;
ca915b10
TR		 1046
1047 return &copy->base;
1048}
1049
1050static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1051 struct drm_crtc_state *state)
1052{
3b59b7ac 1053 __drm_atomic_helper_crtc_destroy_state(crtc, state);
ca915b10
TR		 1054 kfree(state);
1055}
1056
d8f4a9ed 1057static const struct drm_crtc_funcs tegra_crtc_funcs = {
1503ca47 1058 .page_flip = drm_atomic_helper_page_flip,
74f48791 1059 .set_config = drm_atomic_helper_set_config,
f002abc1 1060 .destroy = tegra_dc_destroy,
ca915b10
TR		 1061 .reset = tegra_crtc_reset,
1062 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1063 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
d8f4a9ed
TR		 1064};
1065
d8f4a9ed
TR		 1066static int tegra_dc_set_timings(struct tegra_dc *dc,
1067 struct drm_display_mode *mode)
1068{
0444c0ff
TR		 1069 unsigned int h_ref_to_sync = 1;
1070 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 1071 unsigned long value;
1072
1073 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1074
1075 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1076 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1077
1078 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1079 ((mode->hsync_end - mode->hsync_start) << 0);
1080 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1081
d8f4a9ed
TR		 1082 value = ((mode->vtotal - mode->vsync_end) << 16) |
1083 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 1084 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1085
1086 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1087 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 1088 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1089
1090 value = (mode->vdisplay << 16) | mode->hdisplay;
1091 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1092
1093 return 0;
1094}
1095
9d910b60
TR		 1096/**
1097 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1098 * state
1099 * @dc: display controller
1100 * @crtc_state: CRTC atomic state
1101 * @clk: parent clock for display controller
1102 * @pclk: pixel clock
1103 * @div: shift clock divider
1104 *
1105 * Returns:
1106 * 0 on success or a negative error-code on failure.
1107 */
ca915b10
TR		 1108int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1109 struct drm_crtc_state *crtc_state,
1110 struct clk *clk, unsigned long pclk,
1111 unsigned int div)
1112{
1113 struct tegra_dc_state *state = to_dc_state(crtc_state);
1114
d2982748
TR		 1115 if (!clk_has_parent(dc->clk, clk))
1116 return -EINVAL;
1117
ca915b10
TR		 1118 state->clk = clk;
1119 state->pclk = pclk;
1120 state->div = div;
1121
1122 return 0;
1123}
1124
76d59ed0
TR		 1125static void tegra_dc_commit_state(struct tegra_dc *dc,
1126 struct tegra_dc_state *state)
1127{
1128 u32 value;
1129 int err;
1130
1131 err = clk_set_parent(dc->clk, state->clk);
1132 if (err < 0)
1133 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1134
1135 /*
1136 * Outputs may not want to change the parent clock rate. This is only
1137 * relevant to Tegra20 where only a single display PLL is available.
1138 * Since that PLL would typically be used for HDMI, an internal LVDS
1139 * panel would need to be driven by some other clock such as PLL_P
1140 * which is shared with other peripherals. Changing the clock rate
1141 * should therefore be avoided.
1142 */
1143 if (state->pclk > 0) {
1144 err = clk_set_rate(state->clk, state->pclk);
1145 if (err < 0)
1146 dev_err(dc->dev,
1147 "failed to set clock rate to %lu Hz\n",
1148 state->pclk);
1149 }
1150
1151 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1152 state->div);
1153 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1154
1155 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1156 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1157}
1158
003fc848
TR		 1159static void tegra_dc_stop(struct tegra_dc *dc)
1160{
1161 u32 value;
1162
1163 /* stop the display controller */
1164 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1165 value &= ~DISP_CTRL_MODE_MASK;
1166 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1167
1168 tegra_dc_commit(dc);
1169}
1170
1171static bool tegra_dc_idle(struct tegra_dc *dc)
1172{
1173 u32 value;
1174
1175 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1176
1177 return (value & DISP_CTRL_MODE_MASK) == 0;
1178}
1179
1180static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1181{
1182 timeout = jiffies + msecs_to_jiffies(timeout);
1183
1184 while (time_before(jiffies, timeout)) {
1185 if (tegra_dc_idle(dc))
1186 return 0;
1187
1188 usleep_range(1000, 2000);
1189 }
1190
1191 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1192 return -ETIMEDOUT;
1193}
1194
1195static void tegra_crtc_disable(struct drm_crtc *crtc)
1196{
1197 struct tegra_dc *dc = to_tegra_dc(crtc);
1198 u32 value;
1199
1200 if (!tegra_dc_idle(dc)) {
1201 tegra_dc_stop(dc);
1202
1203 /*
1204 * Ignore the return value, there isn't anything useful to do
1205 * in case this fails.
1206 */
1207 tegra_dc_wait_idle(dc, 100);
1208 }
1209
1210 /*
1211 * This should really be part of the RGB encoder driver, but clearing
1212 * these bits has the side-effect of stopping the display controller.
1213 * When that happens no VBLANK interrupts will be raised. At the same
1214 * time the encoder is disabled before the display controller, so the
1215 * above code is always going to timeout waiting for the controller
1216 * to go idle.
1217 *
1218 * Given the close coupling between the RGB encoder and the display
1219 * controller doing it here is still kind of okay. None of the other
1220 * encoder drivers require these bits to be cleared.
1221 *
1222 * XXX: Perhaps given that the display controller is switched off at
1223 * this point anyway maybe clearing these bits isn't even useful for
1224 * the RGB encoder?
1225 */
1226 if (dc->rgb) {
1227 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1228 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1229 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1230 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1231 }
1232
1233 tegra_dc_stats_reset(&dc->stats);
1234 drm_crtc_vblank_off(crtc);
1235}
1236
1237static void tegra_crtc_enable(struct drm_crtc *crtc)
d8f4a9ed 1238{
4aa3df71 1239 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
76d59ed0 1240 struct tegra_dc_state *state = to_dc_state(crtc->state);
d8f4a9ed 1241 struct tegra_dc *dc = to_tegra_dc(crtc);
dbb3f2f7 1242 u32 value;
d8f4a9ed 1243
76d59ed0
TR		 1244 tegra_dc_commit_state(dc, state);
1245
d8f4a9ed
TR		 1246 /* program display mode */
1247 tegra_dc_set_timings(dc, mode);
1248
8620fc62
TR		 1249 /* interlacing isn't supported yet, so disable it */
1250 if (dc->soc->supports_interlacing) {
1251 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1252 value &= ~INTERLACE_ENABLE;
1253 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1254 }
666cb873
TR		 1255
1256 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1257 value &= ~DISP_CTRL_MODE_MASK;
1258 value |= DISP_CTRL_MODE_C_DISPLAY;
1259 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1260
1261 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1262 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1263 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1264 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1265
1266 tegra_dc_commit(dc);
d8f4a9ed 1267
8ff64c17 1268 drm_crtc_vblank_on(crtc);
d8f4a9ed
TR		 1269}
1270
4aa3df71
TR		 1271static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1272 struct drm_crtc_state *state)
1273{
1274 return 0;
1275}
1276
613d2b27
ML		 1277static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1278 struct drm_crtc_state *old_crtc_state)
4aa3df71 1279{
1503ca47
TR		 1280 struct tegra_dc *dc = to_tegra_dc(crtc);
1281
1282 if (crtc->state->event) {
1283 crtc->state->event->pipe = drm_crtc_index(crtc);
1284
1285 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1286
1287 dc->event = crtc->state->event;
1288 crtc->state->event = NULL;
1289 }
4aa3df71
TR		 1290}
1291
613d2b27
ML		 1292static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1293 struct drm_crtc_state *old_crtc_state)
4aa3df71 1294{
47802b09
TR		 1295 struct tegra_dc_state *state = to_dc_state(crtc->state);
1296 struct tegra_dc *dc = to_tegra_dc(crtc);
1297
1298 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1299 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
4aa3df71
TR		 1300}
1301
d8f4a9ed 1302static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1303 .disable = tegra_crtc_disable,
003fc848 1304 .enable = tegra_crtc_enable,
4aa3df71
TR		 1305 .atomic_check = tegra_crtc_atomic_check,
1306 .atomic_begin = tegra_crtc_atomic_begin,
1307 .atomic_flush = tegra_crtc_atomic_flush,
d8f4a9ed
TR		 1308};
1309
6e5ff998 1310static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1311{
1312 struct tegra_dc *dc = data;
1313 unsigned long status;
1314
1315 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1316 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1317
1318 if (status & FRAME_END_INT) {
1319 /*
1320 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1321 */
791ddb1e 1322 dc->stats.frames++;
d8f4a9ed
TR		 1323 }
1324
1325 if (status & VBLANK_INT) {
1326 /*
1327 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1328 */
ed7dae58 1329 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1330 tegra_dc_finish_page_flip(dc);
791ddb1e 1331 dc->stats.vblank++;
d8f4a9ed
TR		 1332 }
1333
1334 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1335 /*
1336 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1337 */
791ddb1e
TR		 1338 dc->stats.underflow++;
1339 }
1340
1341 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1342 /*
1343 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1344 */
1345 dc->stats.overflow++;
d8f4a9ed
TR		 1346 }
1347
1348 return IRQ_HANDLED;
1349}
1350
1351static int tegra_dc_show_regs(struct seq_file *s, void *data)
1352{
1353 struct drm_info_node *node = s->private;
1354 struct tegra_dc *dc = node->info_ent->data;
003fc848
TR		 1355 int err = 0;
1356
1357 drm_modeset_lock_crtc(&dc->base, NULL);
1358
1359 if (!dc->base.state->active) {
1360 err = -EBUSY;
1361 goto unlock;
1362 }
d8f4a9ed
TR		 1363
1364#define DUMP_REG(name) \
03a60569 1365 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1366 tegra_dc_readl(dc, name))
1367
1368 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1369 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1370 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1371 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1372 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1373 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1374 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1375 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1376 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1377 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1378 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1379 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1380 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1381 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1382 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1383 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1384 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1385 DUMP_REG(DC_CMD_INT_STATUS);
1386 DUMP_REG(DC_CMD_INT_MASK);
1387 DUMP_REG(DC_CMD_INT_ENABLE);
1388 DUMP_REG(DC_CMD_INT_TYPE);
1389 DUMP_REG(DC_CMD_INT_POLARITY);
1390 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1391 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1392 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1393 DUMP_REG(DC_CMD_STATE_ACCESS);
1394 DUMP_REG(DC_CMD_STATE_CONTROL);
1395 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1396 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1397 DUMP_REG(DC_COM_CRC_CONTROL);
1398 DUMP_REG(DC_COM_CRC_CHECKSUM);
1399 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1400 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1401 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1402 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1403 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1404 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1405 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1406 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1407 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1408 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1409 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1410 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1411 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1412 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1413 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1414 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1415 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1416 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1417 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1418 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1419 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1420 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1421 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1422 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1423 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1424 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1425 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1426 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1427 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1428 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1429 DUMP_REG(DC_COM_SPI_CONTROL);
1430 DUMP_REG(DC_COM_SPI_START_BYTE);
1431 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1432 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1433 DUMP_REG(DC_COM_HSPI_CS_DC);
1434 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1435 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1436 DUMP_REG(DC_COM_GPIO_CTRL);
1437 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1438 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1439 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1440 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1441 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1442 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1443 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1444 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1445 DUMP_REG(DC_DISP_REF_TO_SYNC);
1446 DUMP_REG(DC_DISP_SYNC_WIDTH);
1447 DUMP_REG(DC_DISP_BACK_PORCH);
1448 DUMP_REG(DC_DISP_ACTIVE);
1449 DUMP_REG(DC_DISP_FRONT_PORCH);
1450 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1451 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1452 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1453 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1454 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1455 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1456 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1457 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1458 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1459 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1460 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1461 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1462 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1463 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1464 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1465 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1466 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1467 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1468 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1469 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1470 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1471 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1472 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1473 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1474 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1475 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1476 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1477 DUMP_REG(DC_DISP_M0_CONTROL);
1478 DUMP_REG(DC_DISP_M1_CONTROL);
1479 DUMP_REG(DC_DISP_DI_CONTROL);
1480 DUMP_REG(DC_DISP_PP_CONTROL);
1481 DUMP_REG(DC_DISP_PP_SELECT_A);
1482 DUMP_REG(DC_DISP_PP_SELECT_B);
1483 DUMP_REG(DC_DISP_PP_SELECT_C);
1484 DUMP_REG(DC_DISP_PP_SELECT_D);
1485 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1486 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1487 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1488 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1489 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1490 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1491 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1492 DUMP_REG(DC_DISP_BORDER_COLOR);
1493 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1494 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1495 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1496 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1497 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1498 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1499 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1500 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1501 DUMP_REG(DC_DISP_CURSOR_POSITION);
1502 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1503 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1504 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1505 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1506 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1507 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1508 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1509 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1510 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1511 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1512 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1513 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1514 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1515 DUMP_REG(DC_DISP_SD_CONTROL);
1516 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1517 DUMP_REG(DC_DISP_SD_LUT(0));
1518 DUMP_REG(DC_DISP_SD_LUT(1));
1519 DUMP_REG(DC_DISP_SD_LUT(2));
1520 DUMP_REG(DC_DISP_SD_LUT(3));
1521 DUMP_REG(DC_DISP_SD_LUT(4));
1522 DUMP_REG(DC_DISP_SD_LUT(5));
1523 DUMP_REG(DC_DISP_SD_LUT(6));
1524 DUMP_REG(DC_DISP_SD_LUT(7));
1525 DUMP_REG(DC_DISP_SD_LUT(8));
1526 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1527 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1528 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1529 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1530 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1531 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1532 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1533 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1534 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1535 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1536 DUMP_REG(DC_DISP_SD_BL_TF(0));
1537 DUMP_REG(DC_DISP_SD_BL_TF(1));
1538 DUMP_REG(DC_DISP_SD_BL_TF(2));
1539 DUMP_REG(DC_DISP_SD_BL_TF(3));
1540 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1541 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1542 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1543 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1544 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1545 DUMP_REG(DC_WIN_WIN_OPTIONS);
1546 DUMP_REG(DC_WIN_BYTE_SWAP);
1547 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1548 DUMP_REG(DC_WIN_COLOR_DEPTH);
1549 DUMP_REG(DC_WIN_POSITION);
1550 DUMP_REG(DC_WIN_SIZE);
1551 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1552 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1553 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1554 DUMP_REG(DC_WIN_DDA_INC);
1555 DUMP_REG(DC_WIN_LINE_STRIDE);
1556 DUMP_REG(DC_WIN_BUF_STRIDE);
1557 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1558 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1559 DUMP_REG(DC_WIN_DV_CONTROL);
1560 DUMP_REG(DC_WIN_BLEND_NOKEY);
1561 DUMP_REG(DC_WIN_BLEND_1WIN);
1562 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1563 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1564 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1565 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1566 DUMP_REG(DC_WINBUF_START_ADDR);
1567 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1568 DUMP_REG(DC_WINBUF_START_ADDR_U);
1569 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1570 DUMP_REG(DC_WINBUF_START_ADDR_V);
1571 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1572 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1573 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1574 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1575 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1576 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1577 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1578 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1579 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1580
1581#undef DUMP_REG
1582
003fc848
TR		 1583unlock:
1584 drm_modeset_unlock_crtc(&dc->base);
1585 return err;
d8f4a9ed
TR		 1586}
1587
6ca1f62f
TR		 1588static int tegra_dc_show_crc(struct seq_file *s, void *data)
1589{
1590 struct drm_info_node *node = s->private;
1591 struct tegra_dc *dc = node->info_ent->data;
003fc848 1592 int err = 0;
6ca1f62f
TR		 1593 u32 value;
1594
003fc848
TR		 1595 drm_modeset_lock_crtc(&dc->base, NULL);
1596
1597 if (!dc->base.state->active) {
1598 err = -EBUSY;
1599 goto unlock;
1600 }
1601
6ca1f62f
TR		 1602 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1603 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1604 tegra_dc_commit(dc);
1605
1606 drm_crtc_wait_one_vblank(&dc->base);
1607 drm_crtc_wait_one_vblank(&dc->base);
1608
1609 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1610 seq_printf(s, "%08x\n", value);
1611
1612 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1613
003fc848
TR		 1614unlock:
1615 drm_modeset_unlock_crtc(&dc->base);
1616 return err;
6ca1f62f
TR		 1617}
1618
791ddb1e
TR		 1619static int tegra_dc_show_stats(struct seq_file *s, void *data)
1620{
1621 struct drm_info_node *node = s->private;
1622 struct tegra_dc *dc = node->info_ent->data;
1623
1624 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1625 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1626 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1627 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1628
d8f4a9ed
TR		 1629 return 0;
1630}
1631
1632static struct drm_info_list debugfs_files[] = {
1633 { "regs", tegra_dc_show_regs, 0, NULL },
6ca1f62f 1634 { "crc", tegra_dc_show_crc, 0, NULL },
791ddb1e 1635 { "stats", tegra_dc_show_stats, 0, NULL },
d8f4a9ed
TR		 1636};
1637
1638static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1639{
1640 unsigned int i;
1641 char *name;
1642 int err;
1643
1644 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1645 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1646 kfree(name);
1647
1648 if (!dc->debugfs)
1649 return -ENOMEM;
1650
1651 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1652 GFP_KERNEL);
1653 if (!dc->debugfs_files) {
1654 err = -ENOMEM;
1655 goto remove;
1656 }
1657
1658 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1659 dc->debugfs_files[i].data = dc;
1660
1661 err = drm_debugfs_create_files(dc->debugfs_files,
1662 ARRAY_SIZE(debugfs_files),
1663 dc->debugfs, minor);
1664 if (err < 0)
1665 goto free;
1666
1667 dc->minor = minor;
1668
1669 return 0;
1670
1671free:
1672 kfree(dc->debugfs_files);
1673 dc->debugfs_files = NULL;
1674remove:
1675 debugfs_remove(dc->debugfs);
1676 dc->debugfs = NULL;
1677
1678 return err;
1679}
1680
1681static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1682{
1683 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1684 dc->minor);
1685 dc->minor = NULL;
1686
1687 kfree(dc->debugfs_files);
1688 dc->debugfs_files = NULL;
1689
1690 debugfs_remove(dc->debugfs);
1691 dc->debugfs = NULL;
1692
1693 return 0;
1694}
1695
53fa7f72 1696static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1697{
9910f5c4 1698 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1699 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1700 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1701 struct drm_plane *primary = NULL;
1702 struct drm_plane *cursor = NULL;
07d05cbf 1703 u32 value;
d8f4a9ed
TR		 1704 int err;
1705
df06b759
TR		 1706 if (tegra->domain) {
1707 err = iommu_attach_device(tegra->domain, dc->dev);
1708 if (err < 0) {
1709 dev_err(dc->dev, "failed to attach to domain: %d\n",
1710 err);
1711 return err;
1712 }
1713
1714 dc->domain = tegra->domain;
1715 }
1716
c7679306
TR		 1717 primary = tegra_dc_primary_plane_create(drm, dc);
1718 if (IS_ERR(primary)) {
1719 err = PTR_ERR(primary);
1720 goto cleanup;
1721 }
1722
1723 if (dc->soc->supports_cursor) {
1724 cursor = tegra_dc_cursor_plane_create(drm, dc);
1725 if (IS_ERR(cursor)) {
1726 err = PTR_ERR(cursor);
1727 goto cleanup;
1728 }
1729 }
1730
1731 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1732 &tegra_crtc_funcs);
1733 if (err < 0)
1734 goto cleanup;
1735
d8f4a9ed
TR		 1736 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1737 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1738
d1f3e1e0
TR		 1739 /*
1740 * Keep track of the minimum pitch alignment across all display
1741 * controllers.
1742 */
1743 if (dc->soc->pitch_align > tegra->pitch_align)
1744 tegra->pitch_align = dc->soc->pitch_align;
1745
9910f5c4 1746 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1747 if (err < 0 && err != -ENODEV) {
1748 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1749 goto cleanup;
d8f4a9ed
TR		 1750 }
1751
9910f5c4 1752 err = tegra_dc_add_planes(drm, dc);
f34bc787 1753 if (err < 0)
c7679306 1754 goto cleanup;
f34bc787 1755
d8f4a9ed 1756 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1757 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1758 if (err < 0)
1759 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1760 }
1761
6e5ff998 1762 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1763 dev_name(dc->dev), dc);
1764 if (err < 0) {
1765 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1766 err);
c7679306 1767 goto cleanup;
d8f4a9ed
TR		 1768 }
1769
07d05cbf 1770 /* initialize display controller */
42e9ce05
TR		 1771 if (dc->syncpt) {
1772 u32 syncpt = host1x_syncpt_id(dc->syncpt);
07d05cbf 1773
42e9ce05
TR		 1774 value = SYNCPT_CNTRL_NO_STALL;
1775 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1776
1777 value = SYNCPT_VSYNC_ENABLE | syncpt;
1778 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1779 }
07d05cbf 1780
791ddb1e
TR		 1781 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1782 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
07d05cbf
TR		 1783 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1784
1785 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1786 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1787 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1788
1789 /* initialize timer */
1790 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1791 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1792 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1793
1794 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1795 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1796 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1797
791ddb1e
TR		 1798 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1799 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
07d05cbf
TR		 1800 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1801
791ddb1e
TR		 1802 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1803 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
07d05cbf
TR		 1804 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1805
1806 if (dc->soc->supports_border_color)
1807 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1808
791ddb1e
TR		 1809 tegra_dc_stats_reset(&dc->stats);
1810
d8f4a9ed 1811 return 0;
c7679306
TR		 1812
1813cleanup:
1814 if (cursor)
1815 drm_plane_cleanup(cursor);
1816
1817 if (primary)
1818 drm_plane_cleanup(primary);
1819
1820 if (tegra->domain) {
1821 iommu_detach_device(tegra->domain, dc->dev);
1822 dc->domain = NULL;
1823 }
1824
1825 return err;
d8f4a9ed
TR		 1826}
1827
53fa7f72 1828static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1829{
776dc384 1830 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1831 int err;
1832
1833 devm_free_irq(dc->dev, dc->irq, dc);
1834
1835 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1836 err = tegra_dc_debugfs_exit(dc);
1837 if (err < 0)
1838 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1839 }
1840
1841 err = tegra_dc_rgb_exit(dc);
1842 if (err) {
1843 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1844 return err;
1845 }
1846
df06b759
TR		 1847 if (dc->domain) {
1848 iommu_detach_device(dc->domain, dc->dev);
1849 dc->domain = NULL;
1850 }
1851
d8f4a9ed
TR		 1852 return 0;
1853}
1854
1855static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1856 .init = tegra_dc_init,
1857 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1858};
1859
8620fc62 1860static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1861 .supports_border_color = true,
8620fc62 1862 .supports_interlacing = false,
e687651b 1863 .supports_cursor = false,
c134f019 1864 .supports_block_linear = false,
d1f3e1e0 1865 .pitch_align = 8,
9c012700 1866 .has_powergate = false,
8620fc62
TR		 1867};
1868
1869static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1870 .supports_border_color = true,
8620fc62 1871 .supports_interlacing = false,
e687651b 1872 .supports_cursor = false,
c134f019 1873 .supports_block_linear = false,
d1f3e1e0 1874 .pitch_align = 8,
9c012700 1875 .has_powergate = false,
d1f3e1e0
TR		 1876};
1877
1878static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1879 .supports_border_color = true,
d1f3e1e0
TR		 1880 .supports_interlacing = false,
1881 .supports_cursor = false,
1882 .supports_block_linear = false,
1883 .pitch_align = 64,
9c012700 1884 .has_powergate = true,
8620fc62
TR		 1885};
1886
1887static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1888 .supports_border_color = false,
8620fc62 1889 .supports_interlacing = true,
e687651b 1890 .supports_cursor = true,
c134f019 1891 .supports_block_linear = true,
d1f3e1e0 1892 .pitch_align = 64,
9c012700 1893 .has_powergate = true,
8620fc62
TR		 1894};
1895
5b4f516f
TR		 1896static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1897 .supports_border_color = false,
1898 .supports_interlacing = true,
1899 .supports_cursor = true,
1900 .supports_block_linear = true,
1901 .pitch_align = 64,
1902 .has_powergate = true,
1903};
1904
8620fc62
TR		 1905static const struct of_device_id tegra_dc_of_match[] = {
1906 {
5b4f516f
TR		 1907 .compatible = "nvidia,tegra210-dc",
1908 .data = &tegra210_dc_soc_info,
1909 }, {
8620fc62
TR		 1910 .compatible = "nvidia,tegra124-dc",
1911 .data = &tegra124_dc_soc_info,
9c012700
TR		 1912 }, {
1913 .compatible = "nvidia,tegra114-dc",
1914 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1915 }, {
1916 .compatible = "nvidia,tegra30-dc",
1917 .data = &tegra30_dc_soc_info,
1918 }, {
1919 .compatible = "nvidia,tegra20-dc",
1920 .data = &tegra20_dc_soc_info,
1921 }, {
1922 /* sentinel */
1923 }
1924};
ef70728c 1925MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1926
13411ddd
TR		 1927static int tegra_dc_parse_dt(struct tegra_dc *dc)
1928{
1929 struct device_node *np;
1930 u32 value = 0;
1931 int err;
1932
1933 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1934 if (err < 0) {
1935 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1936
1937 /*
1938 * If the nvidia,head property isn't present, try to find the
1939 * correct head number by looking up the position of this
1940 * display controller's node within the device tree. Assuming
1941 * that the nodes are ordered properly in the DTS file and
1942 * that the translation into a flattened device tree blob
1943 * preserves that ordering this will actually yield the right
1944 * head number.
1945 *
1946 * If those assumptions don't hold, this will still work for
1947 * cases where only a single display controller is used.
1948 */
1949 for_each_matching_node(np, tegra_dc_of_match) {
1950 if (np == dc->dev->of_node)
1951 break;
1952
1953 value++;
1954 }
1955 }
1956
1957 dc->pipe = value;
1958
1959 return 0;
1960}
1961
d8f4a9ed
TR		 1962static int tegra_dc_probe(struct platform_device *pdev)
1963{
42e9ce05 1964 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
8620fc62 1965 const struct of_device_id *id;
d8f4a9ed
TR		 1966 struct resource *regs;
1967 struct tegra_dc *dc;
1968 int err;
1969
1970 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1971 if (!dc)
1972 return -ENOMEM;
1973
8620fc62
TR		 1974 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1975 if (!id)
1976 return -ENODEV;
1977
6e5ff998 1978 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1979 INIT_LIST_HEAD(&dc->list);
1980 dc->dev = &pdev->dev;
8620fc62 1981 dc->soc = id->data;
d8f4a9ed 1982
13411ddd
TR		 1983 err = tegra_dc_parse_dt(dc);
1984 if (err < 0)
1985 return err;
1986
d8f4a9ed
TR		 1987 dc->clk = devm_clk_get(&pdev->dev, NULL);
1988 if (IS_ERR(dc->clk)) {
1989 dev_err(&pdev->dev, "failed to get clock\n");
1990 return PTR_ERR(dc->clk);
1991 }
1992
ca48080a
SW		 1993 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1994 if (IS_ERR(dc->rst)) {
1995 dev_err(&pdev->dev, "failed to get reset\n");
1996 return PTR_ERR(dc->rst);
1997 }
1998
9c012700
TR		 1999 if (dc->soc->has_powergate) {
2000 if (dc->pipe == 0)
2001 dc->powergate = TEGRA_POWERGATE_DIS;
2002 else
2003 dc->powergate = TEGRA_POWERGATE_DISB;
2004
2005 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2006 dc->rst);
2007 if (err < 0) {
2008 dev_err(&pdev->dev, "failed to power partition: %d\n",
2009 err);
2010 return err;
2011 }
2012 } else {
2013 err = clk_prepare_enable(dc->clk);
2014 if (err < 0) {
2015 dev_err(&pdev->dev, "failed to enable clock: %d\n",
2016 err);
2017 return err;
2018 }
2019
2020 err = reset_control_deassert(dc->rst);
2021 if (err < 0) {
2022 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2023 err);
2024 return err;
2025 }
2026 }
d8f4a9ed
TR		 2027
2028 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 2029 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2030 if (IS_ERR(dc->regs))
2031 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 2032
2033 dc->irq = platform_get_irq(pdev, 0);
2034 if (dc->irq < 0) {
2035 dev_err(&pdev->dev, "failed to get IRQ\n");
2036 return -ENXIO;
2037 }
2038
01a5da0c
TR		 2039 dc->syncpt = host1x_syncpt_request(&pdev->dev, flags);
2040 if (!dc->syncpt)
2041 dev_warn(&pdev->dev, "failed to allocate syncpoint\n");
2042
776dc384
TR		 2043 INIT_LIST_HEAD(&dc->client.list);
2044 dc->client.ops = &dc_client_ops;
2045 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 2046
2047 err = tegra_dc_rgb_probe(dc);
2048 if (err < 0 && err != -ENODEV) {
2049 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2050 return err;
2051 }
2052
776dc384 2053 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 2054 if (err < 0) {
2055 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2056 err);
2057 return err;
2058 }
2059
2060 platform_set_drvdata(pdev, dc);
2061
2062 return 0;
2063}
2064
2065static int tegra_dc_remove(struct platform_device *pdev)
2066{
d8f4a9ed
TR		 2067 struct tegra_dc *dc = platform_get_drvdata(pdev);
2068 int err;
2069
42e9ce05
TR		 2070 host1x_syncpt_free(dc->syncpt);
2071
776dc384 2072 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 2073 if (err < 0) {
2074 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2075 err);
2076 return err;
2077 }
2078
59d29c0e
TR		 2079 err = tegra_dc_rgb_remove(dc);
2080 if (err < 0) {
2081 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2082 return err;
2083 }
2084
5482d75a 2085 reset_control_assert(dc->rst);
9c012700
TR		 2086
2087 if (dc->soc->has_powergate)
2088 tegra_powergate_power_off(dc->powergate);
2089
d8f4a9ed
TR		 2090 clk_disable_unprepare(dc->clk);
2091
2092 return 0;
2093}
2094
d8f4a9ed
TR		 2095struct platform_driver tegra_dc_driver = {
2096 .driver = {
2097 .name = "tegra-dc",
d8f4a9ed
TR		 2098 .of_match_table = tegra_dc_of_match,
2099 },
2100 .probe = tegra_dc_probe,
2101 .remove = tegra_dc_remove,
2102};
Linux kernel - Deliverables
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