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drm/tegra: dc: Remove unused callbacks
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
ca48080a 13#include <linux/reset.h>
d8f4a9ed 14
9c012700
TR		 15#include <soc/tegra/pmc.h>
16
de2ba664
AM		 17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
d8f4a9ed 20
9d44189f 21#include <drm/drm_atomic.h>
4aa3df71 22#include <drm/drm_atomic_helper.h>
3cb9ae4f
DV		 23#include <drm/drm_plane_helper.h>
24
8620fc62 25struct tegra_dc_soc_info {
42d0659b 26 bool supports_border_color;
8620fc62 27 bool supports_interlacing;
e687651b 28 bool supports_cursor;
c134f019 29 bool supports_block_linear;
d1f3e1e0 30 unsigned int pitch_align;
9c012700 31 bool has_powergate;
8620fc62
TR		 32};
33
f34bc787
TR		 34struct tegra_plane {
35 struct drm_plane base;
36 unsigned int index;
d8f4a9ed
TR		 37};
38
f34bc787
TR		 39static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
40{
41 return container_of(plane, struct tegra_plane, base);
42}
43
ca915b10
TR		 44struct tegra_dc_state {
45 struct drm_crtc_state base;
46
47 struct clk *clk;
48 unsigned long pclk;
49 unsigned int div;
47802b09
TR		 50
51 u32 planes;
ca915b10
TR		 52};
53
54static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
55{
56 if (state)
57 return container_of(state, struct tegra_dc_state, base);
58
59 return NULL;
60}
61
8f604f8c
TR		 62struct tegra_plane_state {
63 struct drm_plane_state base;
64
65 struct tegra_bo_tiling tiling;
66 u32 format;
67 u32 swap;
68};
69
70static inline struct tegra_plane_state *
71to_tegra_plane_state(struct drm_plane_state *state)
72{
73 if (state)
74 return container_of(state, struct tegra_plane_state, base);
75
76 return NULL;
77}
78
86df256f
TR		 79/*
80 * Reads the active copy of a register. This takes the dc->lock spinlock to
81 * prevent races with the VBLANK processing which also needs access to the
82 * active copy of some registers.
83 */
84static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
85{
86 unsigned long flags;
87 u32 value;
88
89 spin_lock_irqsave(&dc->lock, flags);
90
91 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
92 value = tegra_dc_readl(dc, offset);
93 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
94
95 spin_unlock_irqrestore(&dc->lock, flags);
96 return value;
97}
98
d700ba7a
TR		 99/*
100 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
101 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
102 * Latching happens mmediately if the display controller is in STOP mode or
103 * on the next frame boundary otherwise.
104 *
105 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
106 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
107 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
108 * into the ACTIVE copy, either immediately if the display controller is in
109 * STOP mode, or at the next frame boundary otherwise.
110 */
62b9e063 111void tegra_dc_commit(struct tegra_dc *dc)
205d48ed
TR		 112{
113 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
114 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
115}
116
8f604f8c 117static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
10288eea
TR		 118{
119 /* assume no swapping of fetched data */
120 if (swap)
121 *swap = BYTE_SWAP_NOSWAP;
122
8f604f8c 123 switch (fourcc) {
10288eea 124 case DRM_FORMAT_XBGR8888:
8f604f8c
TR		 125 *format = WIN_COLOR_DEPTH_R8G8B8A8;
126 break;
10288eea
TR		 127
128 case DRM_FORMAT_XRGB8888:
8f604f8c
TR		 129 *format = WIN_COLOR_DEPTH_B8G8R8A8;
130 break;
10288eea
TR		 131
132 case DRM_FORMAT_RGB565:
8f604f8c
TR		 133 *format = WIN_COLOR_DEPTH_B5G6R5;
134 break;
10288eea
TR		 135
136 case DRM_FORMAT_UYVY:
8f604f8c
TR		 137 *format = WIN_COLOR_DEPTH_YCbCr422;
138 break;
10288eea
TR		 139
140 case DRM_FORMAT_YUYV:
141 if (swap)
142 *swap = BYTE_SWAP_SWAP2;
143
8f604f8c
TR		 144 *format = WIN_COLOR_DEPTH_YCbCr422;
145 break;
10288eea
TR		 146
147 case DRM_FORMAT_YUV420:
8f604f8c
TR		 148 *format = WIN_COLOR_DEPTH_YCbCr420P;
149 break;
10288eea
TR		 150
151 case DRM_FORMAT_YUV422:
8f604f8c
TR		 152 *format = WIN_COLOR_DEPTH_YCbCr422P;
153 break;
10288eea
TR		 154
155 default:
8f604f8c 156 return -EINVAL;
10288eea
TR		 157 }
158
8f604f8c 159 return 0;
10288eea
TR		 160}
161
162static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
163{
164 switch (format) {
165 case WIN_COLOR_DEPTH_YCbCr422:
166 case WIN_COLOR_DEPTH_YUV422:
167 if (planar)
168 *planar = false;
169
170 return true;
171
172 case WIN_COLOR_DEPTH_YCbCr420P:
173 case WIN_COLOR_DEPTH_YUV420P:
174 case WIN_COLOR_DEPTH_YCbCr422P:
175 case WIN_COLOR_DEPTH_YUV422P:
176 case WIN_COLOR_DEPTH_YCbCr422R:
177 case WIN_COLOR_DEPTH_YUV422R:
178 case WIN_COLOR_DEPTH_YCbCr422RA:
179 case WIN_COLOR_DEPTH_YUV422RA:
180 if (planar)
181 *planar = true;
182
183 return true;
184 }
185
fb35c6b6
TR		 186 if (planar)
187 *planar = false;
188
10288eea
TR		 189 return false;
190}
191
192static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
193 unsigned int bpp)
194{
195 fixed20_12 outf = dfixed_init(out);
196 fixed20_12 inf = dfixed_init(in);
197 u32 dda_inc;
198 int max;
199
200 if (v)
201 max = 15;
202 else {
203 switch (bpp) {
204 case 2:
205 max = 8;
206 break;
207
208 default:
209 WARN_ON_ONCE(1);
210 /* fallthrough */
211 case 4:
212 max = 4;
213 break;
214 }
215 }
216
217 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
218 inf.full -= dfixed_const(1);
219
220 dda_inc = dfixed_div(inf, outf);
221 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
222
223 return dda_inc;
224}
225
226static inline u32 compute_initial_dda(unsigned int in)
227{
228 fixed20_12 inf = dfixed_init(in);
229 return dfixed_frac(inf);
230}
231
4aa3df71
TR		 232static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
233 const struct tegra_dc_window *window)
10288eea
TR		 234{
235 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 236 unsigned long value, flags;
10288eea
TR		 237 bool yuv, planar;
238
239 /*
240 * For YUV planar modes, the number of bytes per pixel takes into
241 * account only the luma component and therefore is 1.
242 */
243 yuv = tegra_dc_format_is_yuv(window->format, &planar);
244 if (!yuv)
245 bpp = window->bits_per_pixel / 8;
246 else
247 bpp = planar ? 1 : 2;
248
93396d0f
SP		 249 spin_lock_irqsave(&dc->lock, flags);
250
10288eea
TR		 251 value = WINDOW_A_SELECT << index;
252 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
253
254 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
255 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
256
257 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
258 tegra_dc_writel(dc, value, DC_WIN_POSITION);
259
260 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
261 tegra_dc_writel(dc, value, DC_WIN_SIZE);
262
263 h_offset = window->src.x * bpp;
264 v_offset = window->src.y;
265 h_size = window->src.w * bpp;
266 v_size = window->src.h;
267
268 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
269 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
270
271 /*
272 * For DDA computations the number of bytes per pixel for YUV planar
273 * modes needs to take into account all Y, U and V components.
274 */
275 if (yuv && planar)
276 bpp = 2;
277
278 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
279 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
280
281 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
282 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
283
284 h_dda = compute_initial_dda(window->src.x);
285 v_dda = compute_initial_dda(window->src.y);
286
287 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
288 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
289
290 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
291 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
292
293 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
294
295 if (yuv && planar) {
296 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
297 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
298 value = window->stride[1] << 16 | window->stride[0];
299 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
300 } else {
301 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
302 }
303
304 if (window->bottom_up)
305 v_offset += window->src.h - 1;
306
307 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
308 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
309
c134f019
TR		 310 if (dc->soc->supports_block_linear) {
311 unsigned long height = window->tiling.value;
312
313 switch (window->tiling.mode) {
314 case TEGRA_BO_TILING_MODE_PITCH:
315 value = DC_WINBUF_SURFACE_KIND_PITCH;
316 break;
317
318 case TEGRA_BO_TILING_MODE_TILED:
319 value = DC_WINBUF_SURFACE_KIND_TILED;
320 break;
321
322 case TEGRA_BO_TILING_MODE_BLOCK:
323 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
324 DC_WINBUF_SURFACE_KIND_BLOCK;
325 break;
326 }
327
328 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 329 } else {
c134f019
TR		 330 switch (window->tiling.mode) {
331 case TEGRA_BO_TILING_MODE_PITCH:
332 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
333 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
334 break;
10288eea 335
c134f019
TR		 336 case TEGRA_BO_TILING_MODE_TILED:
337 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
338 DC_WIN_BUFFER_ADDR_MODE_TILE;
339 break;
340
341 case TEGRA_BO_TILING_MODE_BLOCK:
4aa3df71
TR		 342 /*
343 * No need to handle this here because ->atomic_check
344 * will already have filtered it out.
345 */
346 break;
c134f019
TR		 347 }
348
349 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
350 }
10288eea
TR		 351
352 value = WIN_ENABLE;
353
354 if (yuv) {
355 /* setup default colorspace conversion coefficients */
356 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
357 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
358 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
359 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
360 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
361 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
362 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
363 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
364
365 value |= CSC_ENABLE;
366 } else if (window->bits_per_pixel < 24) {
367 value |= COLOR_EXPAND;
368 }
369
370 if (window->bottom_up)
371 value |= V_DIRECTION;
372
373 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
374
375 /*
376 * Disable blending and assume Window A is the bottom-most window,
377 * Window C is the top-most window and Window B is in the middle.
378 */
379 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
380 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
381
382 switch (index) {
383 case 0:
384 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
385 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
386 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
387 break;
388
389 case 1:
390 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
391 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
393 break;
394
395 case 2:
396 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
397 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
399 break;
400 }
401
93396d0f 402 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 403}
404
405static void tegra_plane_destroy(struct drm_plane *plane)
406{
407 struct tegra_plane *p = to_tegra_plane(plane);
408
409 drm_plane_cleanup(plane);
410 kfree(p);
411}
412
413static const u32 tegra_primary_plane_formats[] = {
414 DRM_FORMAT_XBGR8888,
415 DRM_FORMAT_XRGB8888,
416 DRM_FORMAT_RGB565,
417};
418
4aa3df71 419static void tegra_primary_plane_destroy(struct drm_plane *plane)
c7679306 420{
4aa3df71
TR		 421 tegra_plane_destroy(plane);
422}
423
8f604f8c
TR		 424static void tegra_plane_reset(struct drm_plane *plane)
425{
426 struct tegra_plane_state *state;
427
3b59b7ac
TR		 428 if (plane->state)
429 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
8f604f8c
TR		 430
431 kfree(plane->state);
432 plane->state = NULL;
433
434 state = kzalloc(sizeof(*state), GFP_KERNEL);
435 if (state) {
436 plane->state = &state->base;
437 plane->state->plane = plane;
438 }
439}
440
441static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
442{
443 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
444 struct tegra_plane_state *copy;
445
3b59b7ac 446 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
8f604f8c
TR		 447 if (!copy)
448 return NULL;
449
3b59b7ac
TR		 450 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
451 copy->tiling = state->tiling;
452 copy->format = state->format;
453 copy->swap = state->swap;
8f604f8c
TR		 454
455 return &copy->base;
456}
457
458static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
459 struct drm_plane_state *state)
460{
3b59b7ac 461 __drm_atomic_helper_plane_destroy_state(plane, state);
8f604f8c
TR		 462 kfree(state);
463}
464
4aa3df71 465static const struct drm_plane_funcs tegra_primary_plane_funcs = {
07866963
TR		 466 .update_plane = drm_atomic_helper_update_plane,
467 .disable_plane = drm_atomic_helper_disable_plane,
4aa3df71 468 .destroy = tegra_primary_plane_destroy,
8f604f8c
TR		 469 .reset = tegra_plane_reset,
470 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
471 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 472};
473
474static int tegra_plane_prepare_fb(struct drm_plane *plane,
475 struct drm_framebuffer *fb)
476{
477 return 0;
478}
479
480static void tegra_plane_cleanup_fb(struct drm_plane *plane,
481 struct drm_framebuffer *fb)
482{
483}
484
47802b09
TR		 485static int tegra_plane_state_add(struct tegra_plane *plane,
486 struct drm_plane_state *state)
487{
488 struct drm_crtc_state *crtc_state;
489 struct tegra_dc_state *tegra;
490
491 /* Propagate errors from allocation or locking failures. */
492 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
493 if (IS_ERR(crtc_state))
494 return PTR_ERR(crtc_state);
495
496 tegra = to_dc_state(crtc_state);
497
498 tegra->planes |= WIN_A_ACT_REQ << plane->index;
499
500 return 0;
501}
502
4aa3df71
TR		 503static int tegra_plane_atomic_check(struct drm_plane *plane,
504 struct drm_plane_state *state)
505{
8f604f8c
TR		 506 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
507 struct tegra_bo_tiling *tiling = &plane_state->tiling;
47802b09 508 struct tegra_plane *tegra = to_tegra_plane(plane);
4aa3df71 509 struct tegra_dc *dc = to_tegra_dc(state->crtc);
4aa3df71
TR		 510 int err;
511
512 /* no need for further checks if the plane is being disabled */
513 if (!state->crtc)
514 return 0;
515
8f604f8c
TR		 516 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
517 &plane_state->swap);
4aa3df71
TR		 518 if (err < 0)
519 return err;
520
8f604f8c
TR		 521 err = tegra_fb_get_tiling(state->fb, tiling);
522 if (err < 0)
523 return err;
524
525 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
4aa3df71
TR		 526 !dc->soc->supports_block_linear) {
527 DRM_ERROR("hardware doesn't support block linear mode\n");
528 return -EINVAL;
529 }
530
531 /*
532 * Tegra doesn't support different strides for U and V planes so we
533 * error out if the user tries to display a framebuffer with such a
534 * configuration.
535 */
536 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
537 if (state->fb->pitches[2] != state->fb->pitches[1]) {
538 DRM_ERROR("unsupported UV-plane configuration\n");
539 return -EINVAL;
540 }
541 }
542
47802b09
TR		 543 err = tegra_plane_state_add(tegra, state);
544 if (err < 0)
545 return err;
546
4aa3df71
TR		 547 return 0;
548}
549
550static void tegra_plane_atomic_update(struct drm_plane *plane,
551 struct drm_plane_state *old_state)
552{
8f604f8c 553 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
4aa3df71
TR		 554 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
555 struct drm_framebuffer *fb = plane->state->fb;
c7679306 556 struct tegra_plane *p = to_tegra_plane(plane);
c7679306 557 struct tegra_dc_window window;
4aa3df71 558 unsigned int i;
c7679306 559
4aa3df71
TR		 560 /* rien ne va plus */
561 if (!plane->state->crtc || !plane->state->fb)
562 return;
563
c7679306 564 memset(&window, 0, sizeof(window));
4aa3df71
TR		 565 window.src.x = plane->state->src_x >> 16;
566 window.src.y = plane->state->src_y >> 16;
567 window.src.w = plane->state->src_w >> 16;
568 window.src.h = plane->state->src_h >> 16;
569 window.dst.x = plane->state->crtc_x;
570 window.dst.y = plane->state->crtc_y;
571 window.dst.w = plane->state->crtc_w;
572 window.dst.h = plane->state->crtc_h;
c7679306
TR		 573 window.bits_per_pixel = fb->bits_per_pixel;
574 window.bottom_up = tegra_fb_is_bottom_up(fb);
575
8f604f8c
TR		 576 /* copy from state */
577 window.tiling = state->tiling;
578 window.format = state->format;
579 window.swap = state->swap;
c7679306 580
4aa3df71
TR		 581 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
582 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
c7679306 583
4aa3df71
TR		 584 window.base[i] = bo->paddr + fb->offsets[i];
585 window.stride[i] = fb->pitches[i];
586 }
10288eea 587
4aa3df71 588 tegra_dc_setup_window(dc, p->index, &window);
10288eea
TR		 589}
590
4aa3df71
TR		 591static void tegra_plane_atomic_disable(struct drm_plane *plane,
592 struct drm_plane_state *old_state)
c7679306 593{
4aa3df71
TR		 594 struct tegra_plane *p = to_tegra_plane(plane);
595 struct tegra_dc *dc;
596 unsigned long flags;
597 u32 value;
598
599 /* rien ne va plus */
600 if (!old_state || !old_state->crtc)
601 return;
602
603 dc = to_tegra_dc(old_state->crtc);
604
605 spin_lock_irqsave(&dc->lock, flags);
606
607 value = WINDOW_A_SELECT << p->index;
608 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
609
610 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
611 value &= ~WIN_ENABLE;
612 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
613
4aa3df71 614 spin_unlock_irqrestore(&dc->lock, flags);
c7679306
TR		 615}
616
4aa3df71
TR		 617static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
618 .prepare_fb = tegra_plane_prepare_fb,
619 .cleanup_fb = tegra_plane_cleanup_fb,
620 .atomic_check = tegra_plane_atomic_check,
621 .atomic_update = tegra_plane_atomic_update,
622 .atomic_disable = tegra_plane_atomic_disable,
c7679306
TR		 623};
624
625static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
626 struct tegra_dc *dc)
627{
518e6227
TR		 628 /*
629 * Ideally this would use drm_crtc_mask(), but that would require the
630 * CRTC to already be in the mode_config's list of CRTCs. However, it
631 * will only be added to that list in the drm_crtc_init_with_planes()
632 * (in tegra_dc_init()), which in turn requires registration of these
633 * planes. So we have ourselves a nice little chicken and egg problem
634 * here.
635 *
636 * We work around this by manually creating the mask from the number
637 * of CRTCs that have been registered, and should therefore always be
638 * the same as drm_crtc_index() after registration.
639 */
640 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 641 struct tegra_plane *plane;
642 unsigned int num_formats;
643 const u32 *formats;
644 int err;
645
646 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
647 if (!plane)
648 return ERR_PTR(-ENOMEM);
649
650 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
651 formats = tegra_primary_plane_formats;
652
518e6227 653 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306
TR		 654 &tegra_primary_plane_funcs, formats,
655 num_formats, DRM_PLANE_TYPE_PRIMARY);
656 if (err < 0) {
657 kfree(plane);
658 return ERR_PTR(err);
659 }
660
4aa3df71
TR		 661 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
662
c7679306
TR		 663 return &plane->base;
664}
665
666static const u32 tegra_cursor_plane_formats[] = {
667 DRM_FORMAT_RGBA8888,
668};
669
4aa3df71
TR		 670static int tegra_cursor_atomic_check(struct drm_plane *plane,
671 struct drm_plane_state *state)
c7679306 672{
47802b09
TR		 673 struct tegra_plane *tegra = to_tegra_plane(plane);
674 int err;
675
4aa3df71
TR		 676 /* no need for further checks if the plane is being disabled */
677 if (!state->crtc)
678 return 0;
c7679306
TR		 679
680 /* scaling not supported for cursor */
4aa3df71
TR		 681 if ((state->src_w >> 16 != state->crtc_w) ||
682 (state->src_h >> 16 != state->crtc_h))
c7679306
TR		 683 return -EINVAL;
684
685 /* only square cursors supported */
4aa3df71
TR		 686 if (state->src_w != state->src_h)
687 return -EINVAL;
688
689 if (state->crtc_w != 32 && state->crtc_w != 64 &&
690 state->crtc_w != 128 && state->crtc_w != 256)
c7679306
TR		 691 return -EINVAL;
692
47802b09
TR		 693 err = tegra_plane_state_add(tegra, state);
694 if (err < 0)
695 return err;
696
4aa3df71
TR		 697 return 0;
698}
699
700static void tegra_cursor_atomic_update(struct drm_plane *plane,
701 struct drm_plane_state *old_state)
702{
703 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
704 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
705 struct drm_plane_state *state = plane->state;
706 u32 value = CURSOR_CLIP_DISPLAY;
707
708 /* rien ne va plus */
709 if (!plane->state->crtc || !plane->state->fb)
710 return;
711
712 switch (state->crtc_w) {
c7679306
TR		 713 case 32:
714 value |= CURSOR_SIZE_32x32;
715 break;
716
717 case 64:
718 value |= CURSOR_SIZE_64x64;
719 break;
720
721 case 128:
722 value |= CURSOR_SIZE_128x128;
723 break;
724
725 case 256:
726 value |= CURSOR_SIZE_256x256;
727 break;
728
729 default:
4aa3df71
TR		 730 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
731 state->crtc_h);
732 return;
c7679306
TR		 733 }
734
735 value |= (bo->paddr >> 10) & 0x3fffff;
736 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
737
738#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
739 value = (bo->paddr >> 32) & 0x3;
740 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
741#endif
742
743 /* enable cursor and set blend mode */
744 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
745 value |= CURSOR_ENABLE;
746 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
747
748 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
749 value &= ~CURSOR_DST_BLEND_MASK;
750 value &= ~CURSOR_SRC_BLEND_MASK;
751 value |= CURSOR_MODE_NORMAL;
752 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
753 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
754 value |= CURSOR_ALPHA;
755 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
756
757 /* position the cursor */
4aa3df71 758 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
c7679306
TR		 759 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
760
c7679306
TR		 761}
762
4aa3df71
TR		 763static void tegra_cursor_atomic_disable(struct drm_plane *plane,
764 struct drm_plane_state *old_state)
c7679306 765{
4aa3df71 766 struct tegra_dc *dc;
c7679306
TR		 767 u32 value;
768
4aa3df71
TR		 769 /* rien ne va plus */
770 if (!old_state || !old_state->crtc)
771 return;
772
773 dc = to_tegra_dc(old_state->crtc);
c7679306
TR		 774
775 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
776 value &= ~CURSOR_ENABLE;
777 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
c7679306
TR		 778}
779
780static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
07866963
TR		 781 .update_plane = drm_atomic_helper_update_plane,
782 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 783 .destroy = tegra_plane_destroy,
8f604f8c
TR		 784 .reset = tegra_plane_reset,
785 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
786 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
4aa3df71
TR		 787};
788
789static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
790 .prepare_fb = tegra_plane_prepare_fb,
791 .cleanup_fb = tegra_plane_cleanup_fb,
792 .atomic_check = tegra_cursor_atomic_check,
793 .atomic_update = tegra_cursor_atomic_update,
794 .atomic_disable = tegra_cursor_atomic_disable,
c7679306
TR		 795};
796
797static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
798 struct tegra_dc *dc)
799{
800 struct tegra_plane *plane;
801 unsigned int num_formats;
802 const u32 *formats;
803 int err;
804
805 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
806 if (!plane)
807 return ERR_PTR(-ENOMEM);
808
47802b09
TR		 809 /*
810 * We'll treat the cursor as an overlay plane with index 6 here so
811 * that the update and activation request bits in DC_CMD_STATE_CONTROL
812 * match up.
813 */
814 plane->index = 6;
815
c7679306
TR		 816 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
817 formats = tegra_cursor_plane_formats;
818
819 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
820 &tegra_cursor_plane_funcs, formats,
821 num_formats, DRM_PLANE_TYPE_CURSOR);
822 if (err < 0) {
823 kfree(plane);
824 return ERR_PTR(err);
825 }
826
4aa3df71 827 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
f34bc787 828
4aa3df71 829 return &plane->base;
f34bc787
TR		 830}
831
c7679306 832static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 833{
c7679306 834 tegra_plane_destroy(plane);
f34bc787
TR		 835}
836
c7679306 837static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
07866963
TR		 838 .update_plane = drm_atomic_helper_update_plane,
839 .disable_plane = drm_atomic_helper_disable_plane,
c7679306 840 .destroy = tegra_overlay_plane_destroy,
8f604f8c
TR		 841 .reset = tegra_plane_reset,
842 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
843 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
f34bc787
TR		 844};
845
c7679306 846static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 847 DRM_FORMAT_XBGR8888,
f34bc787 848 DRM_FORMAT_XRGB8888,
dbe4d9a7 849 DRM_FORMAT_RGB565,
f34bc787 850 DRM_FORMAT_UYVY,
f925390e 851 DRM_FORMAT_YUYV,
f34bc787
TR		 852 DRM_FORMAT_YUV420,
853 DRM_FORMAT_YUV422,
854};
855
4aa3df71
TR		 856static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
857 .prepare_fb = tegra_plane_prepare_fb,
858 .cleanup_fb = tegra_plane_cleanup_fb,
859 .atomic_check = tegra_plane_atomic_check,
860 .atomic_update = tegra_plane_atomic_update,
861 .atomic_disable = tegra_plane_atomic_disable,
862};
863
c7679306
TR		 864static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
865 struct tegra_dc *dc,
866 unsigned int index)
f34bc787 867{
c7679306
TR		 868 struct tegra_plane *plane;
869 unsigned int num_formats;
870 const u32 *formats;
871 int err;
f34bc787 872
c7679306
TR		 873 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
874 if (!plane)
875 return ERR_PTR(-ENOMEM);
f34bc787 876
c7679306 877 plane->index = index;
f34bc787 878
c7679306
TR		 879 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
880 formats = tegra_overlay_plane_formats;
f34bc787 881
c7679306
TR		 882 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
883 &tegra_overlay_plane_funcs, formats,
884 num_formats, DRM_PLANE_TYPE_OVERLAY);
885 if (err < 0) {
886 kfree(plane);
887 return ERR_PTR(err);
888 }
889
4aa3df71
TR		 890 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
891
c7679306
TR		 892 return &plane->base;
893}
894
895static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
896{
897 struct drm_plane *plane;
898 unsigned int i;
899
900 for (i = 0; i < 2; i++) {
901 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
902 if (IS_ERR(plane))
903 return PTR_ERR(plane);
f34bc787
TR		 904 }
905
906 return 0;
907}
908
42e9ce05
TR		 909u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
910{
911 if (dc->syncpt)
912 return host1x_syncpt_read(dc->syncpt);
913
914 /* fallback to software emulated VBLANK counter */
915 return drm_crtc_vblank_count(&dc->base);
916}
917
6e5ff998
TR		 918void tegra_dc_enable_vblank(struct tegra_dc *dc)
919{
920 unsigned long value, flags;
921
922 spin_lock_irqsave(&dc->lock, flags);
923
924 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
925 value |= VBLANK_INT;
926 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
927
928 spin_unlock_irqrestore(&dc->lock, flags);
929}
930
931void tegra_dc_disable_vblank(struct tegra_dc *dc)
932{
933 unsigned long value, flags;
934
935 spin_lock_irqsave(&dc->lock, flags);
936
937 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
938 value &= ~VBLANK_INT;
939 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
940
941 spin_unlock_irqrestore(&dc->lock, flags);
942}
943
3c03c46a
TR		 944static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
945{
946 struct drm_device *drm = dc->base.dev;
947 struct drm_crtc *crtc = &dc->base;
3c03c46a 948 unsigned long flags, base;
de2ba664 949 struct tegra_bo *bo;
3c03c46a 950
6b59cc1c
TR		 951 spin_lock_irqsave(&drm->event_lock, flags);
952
953 if (!dc->event) {
954 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 955 return;
6b59cc1c 956 }
3c03c46a 957
f4510a27 958 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 959
8643bc6d 960 spin_lock(&dc->lock);
93396d0f 961
3c03c46a 962 /* check if new start address has been latched */
93396d0f 963 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 964 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
965 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
966 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
967
8643bc6d 968 spin_unlock(&dc->lock);
93396d0f 969
f4510a27 970 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 971 drm_crtc_send_vblank_event(crtc, dc->event);
972 drm_crtc_vblank_put(crtc);
3c03c46a 973 dc->event = NULL;
3c03c46a 974 }
6b59cc1c
TR		 975
976 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 977}
978
979void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
980{
981 struct tegra_dc *dc = to_tegra_dc(crtc);
982 struct drm_device *drm = crtc->dev;
983 unsigned long flags;
984
985 spin_lock_irqsave(&drm->event_lock, flags);
986
987 if (dc->event && dc->event->base.file_priv == file) {
988 dc->event->base.destroy(&dc->event->base);
ed7dae58 989 drm_crtc_vblank_put(crtc);
3c03c46a
TR		 990 dc->event = NULL;
991 }
992
993 spin_unlock_irqrestore(&drm->event_lock, flags);
994}
995
f002abc1
TR		 996static void tegra_dc_destroy(struct drm_crtc *crtc)
997{
998 drm_crtc_cleanup(crtc);
f002abc1
TR		 999}
1000
ca915b10
TR		 1001static void tegra_crtc_reset(struct drm_crtc *crtc)
1002{
1003 struct tegra_dc_state *state;
1004
3b59b7ac
TR		 1005 if (crtc->state)
1006 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1007
ca915b10
TR		 1008 kfree(crtc->state);
1009 crtc->state = NULL;
1010
1011 state = kzalloc(sizeof(*state), GFP_KERNEL);
332bbe70 1012 if (state) {
ca915b10 1013 crtc->state = &state->base;
332bbe70
TR		 1014 crtc->state->crtc = crtc;
1015 }
ca915b10
TR		 1016}
1017
1018static struct drm_crtc_state *
1019tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1020{
1021 struct tegra_dc_state *state = to_dc_state(crtc->state);
1022 struct tegra_dc_state *copy;
1023
3b59b7ac 1024 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
ca915b10
TR		 1025 if (!copy)
1026 return NULL;
1027
3b59b7ac
TR		 1028 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1029 copy->clk = state->clk;
1030 copy->pclk = state->pclk;
1031 copy->div = state->div;
1032 copy->planes = state->planes;
ca915b10
TR		 1033
1034 return &copy->base;
1035}
1036
1037static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1038 struct drm_crtc_state *state)
1039{
3b59b7ac 1040 __drm_atomic_helper_crtc_destroy_state(crtc, state);
ca915b10
TR		 1041 kfree(state);
1042}
1043
d8f4a9ed 1044static const struct drm_crtc_funcs tegra_crtc_funcs = {
1503ca47 1045 .page_flip = drm_atomic_helper_page_flip,
74f48791 1046 .set_config = drm_atomic_helper_set_config,
f002abc1 1047 .destroy = tegra_dc_destroy,
ca915b10
TR		 1048 .reset = tegra_crtc_reset,
1049 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1050 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
d8f4a9ed
TR		 1051};
1052
86df256f
TR		 1053static void tegra_dc_stop(struct tegra_dc *dc)
1054{
1055 u32 value;
1056
1057 /* stop the display controller */
1058 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1059 value &= ~DISP_CTRL_MODE_MASK;
1060 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1061
1062 tegra_dc_commit(dc);
1063}
1064
1065static bool tegra_dc_idle(struct tegra_dc *dc)
1066{
1067 u32 value;
1068
1069 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1070
1071 return (value & DISP_CTRL_MODE_MASK) == 0;
1072}
1073
1074static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1075{
1076 timeout = jiffies + msecs_to_jiffies(timeout);
1077
1078 while (time_before(jiffies, timeout)) {
1079 if (tegra_dc_idle(dc))
1080 return 0;
1081
1082 usleep_range(1000, 2000);
1083 }
1084
1085 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1086 return -ETIMEDOUT;
1087}
1088
f34bc787 1089static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 1090{
f002abc1 1091 struct tegra_dc *dc = to_tegra_dc(crtc);
3b0e5855 1092 u32 value;
f002abc1 1093
86df256f
TR		 1094 if (!tegra_dc_idle(dc)) {
1095 tegra_dc_stop(dc);
1096
1097 /*
1098 * Ignore the return value, there isn't anything useful to do
1099 * in case this fails.
1100 */
1101 tegra_dc_wait_idle(dc, 100);
1102 }
36904adf 1103
3b0e5855
TR		 1104 /*
1105 * This should really be part of the RGB encoder driver, but clearing
1106 * these bits has the side-effect of stopping the display controller.
1107 * When that happens no VBLANK interrupts will be raised. At the same
1108 * time the encoder is disabled before the display controller, so the
1109 * above code is always going to timeout waiting for the controller
1110 * to go idle.
1111 *
1112 * Given the close coupling between the RGB encoder and the display
1113 * controller doing it here is still kind of okay. None of the other
1114 * encoder drivers require these bits to be cleared.
1115 *
1116 * XXX: Perhaps given that the display controller is switched off at
1117 * this point anyway maybe clearing these bits isn't even useful for
1118 * the RGB encoder?
1119 */
1120 if (dc->rgb) {
1121 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1122 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1123 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1124 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1125 }
1126
8ff64c17 1127 drm_crtc_vblank_off(crtc);
d8f4a9ed
TR		 1128}
1129
1130static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
1131 const struct drm_display_mode *mode,
1132 struct drm_display_mode *adjusted)
1133{
1134 return true;
1135}
1136
d8f4a9ed
TR		 1137static int tegra_dc_set_timings(struct tegra_dc *dc,
1138 struct drm_display_mode *mode)
1139{
0444c0ff
TR		 1140 unsigned int h_ref_to_sync = 1;
1141 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 1142 unsigned long value;
1143
1144 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1145
1146 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1147 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1148
1149 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1150 ((mode->hsync_end - mode->hsync_start) << 0);
1151 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1152
d8f4a9ed
TR		 1153 value = ((mode->vtotal - mode->vsync_end) << 16) |
1154 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 1155 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1156
1157 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1158 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 1159 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1160
1161 value = (mode->vdisplay << 16) | mode->hdisplay;
1162 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1163
1164 return 0;
1165}
1166
ca915b10
TR		 1167int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1168 struct drm_crtc_state *crtc_state,
1169 struct clk *clk, unsigned long pclk,
1170 unsigned int div)
1171{
1172 struct tegra_dc_state *state = to_dc_state(crtc_state);
1173
d2982748
TR		 1174 if (!clk_has_parent(dc->clk, clk))
1175 return -EINVAL;
1176
ca915b10
TR		 1177 state->clk = clk;
1178 state->pclk = pclk;
1179 state->div = div;
1180
1181 return 0;
1182}
1183
76d59ed0
TR		 1184static void tegra_dc_commit_state(struct tegra_dc *dc,
1185 struct tegra_dc_state *state)
1186{
1187 u32 value;
1188 int err;
1189
1190 err = clk_set_parent(dc->clk, state->clk);
1191 if (err < 0)
1192 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1193
1194 /*
1195 * Outputs may not want to change the parent clock rate. This is only
1196 * relevant to Tegra20 where only a single display PLL is available.
1197 * Since that PLL would typically be used for HDMI, an internal LVDS
1198 * panel would need to be driven by some other clock such as PLL_P
1199 * which is shared with other peripherals. Changing the clock rate
1200 * should therefore be avoided.
1201 */
1202 if (state->pclk > 0) {
1203 err = clk_set_rate(state->clk, state->pclk);
1204 if (err < 0)
1205 dev_err(dc->dev,
1206 "failed to set clock rate to %lu Hz\n",
1207 state->pclk);
1208 }
1209
1210 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1211 state->div);
1212 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1213
1214 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1215 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1216}
1217
4aa3df71 1218static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
d8f4a9ed 1219{
4aa3df71 1220 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
76d59ed0 1221 struct tegra_dc_state *state = to_dc_state(crtc->state);
d8f4a9ed 1222 struct tegra_dc *dc = to_tegra_dc(crtc);
dbb3f2f7 1223 u32 value;
d8f4a9ed 1224
76d59ed0
TR		 1225 tegra_dc_commit_state(dc, state);
1226
d8f4a9ed
TR		 1227 /* program display mode */
1228 tegra_dc_set_timings(dc, mode);
1229
8620fc62
TR		 1230 /* interlacing isn't supported yet, so disable it */
1231 if (dc->soc->supports_interlacing) {
1232 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1233 value &= ~INTERLACE_ENABLE;
1234 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1235 }
666cb873
TR		 1236
1237 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1238 value &= ~DISP_CTRL_MODE_MASK;
1239 value |= DISP_CTRL_MODE_C_DISPLAY;
1240 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1241
1242 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1243 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1244 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1245 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1246
1247 tegra_dc_commit(dc);
d8f4a9ed
TR		 1248}
1249
1250static void tegra_crtc_prepare(struct drm_crtc *crtc)
1251{
8ff64c17 1252 drm_crtc_vblank_off(crtc);
d8f4a9ed
TR		 1253}
1254
1255static void tegra_crtc_commit(struct drm_crtc *crtc)
1256{
8ff64c17 1257 drm_crtc_vblank_on(crtc);
d8f4a9ed
TR		 1258}
1259
4aa3df71
TR		 1260static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1261 struct drm_crtc_state *state)
1262{
1263 return 0;
1264}
1265
1266static void tegra_crtc_atomic_begin(struct drm_crtc *crtc)
1267{
1503ca47
TR		 1268 struct tegra_dc *dc = to_tegra_dc(crtc);
1269
1270 if (crtc->state->event) {
1271 crtc->state->event->pipe = drm_crtc_index(crtc);
1272
1273 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1274
1275 dc->event = crtc->state->event;
1276 crtc->state->event = NULL;
1277 }
4aa3df71
TR		 1278}
1279
1280static void tegra_crtc_atomic_flush(struct drm_crtc *crtc)
1281{
47802b09
TR		 1282 struct tegra_dc_state *state = to_dc_state(crtc->state);
1283 struct tegra_dc *dc = to_tegra_dc(crtc);
1284
1285 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1286 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
4aa3df71
TR		 1287}
1288
d8f4a9ed 1289static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1290 .disable = tegra_crtc_disable,
d8f4a9ed 1291 .mode_fixup = tegra_crtc_mode_fixup,
4aa3df71 1292 .mode_set_nofb = tegra_crtc_mode_set_nofb,
d8f4a9ed
TR		 1293 .prepare = tegra_crtc_prepare,
1294 .commit = tegra_crtc_commit,
4aa3df71
TR		 1295 .atomic_check = tegra_crtc_atomic_check,
1296 .atomic_begin = tegra_crtc_atomic_begin,
1297 .atomic_flush = tegra_crtc_atomic_flush,
d8f4a9ed
TR		 1298};
1299
6e5ff998 1300static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1301{
1302 struct tegra_dc *dc = data;
1303 unsigned long status;
1304
1305 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1306 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1307
1308 if (status & FRAME_END_INT) {
1309 /*
1310 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1311 */
1312 }
1313
1314 if (status & VBLANK_INT) {
1315 /*
1316 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1317 */
ed7dae58 1318 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1319 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 1320 }
1321
1322 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1323 /*
1324 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1325 */
1326 }
1327
1328 return IRQ_HANDLED;
1329}
1330
1331static int tegra_dc_show_regs(struct seq_file *s, void *data)
1332{
1333 struct drm_info_node *node = s->private;
1334 struct tegra_dc *dc = node->info_ent->data;
1335
1336#define DUMP_REG(name) \
03a60569 1337 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1338 tegra_dc_readl(dc, name))
1339
1340 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1341 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1342 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1343 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1344 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1345 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1346 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1347 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1348 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1349 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1350 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1351 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1352 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1353 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1354 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1355 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1356 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1357 DUMP_REG(DC_CMD_INT_STATUS);
1358 DUMP_REG(DC_CMD_INT_MASK);
1359 DUMP_REG(DC_CMD_INT_ENABLE);
1360 DUMP_REG(DC_CMD_INT_TYPE);
1361 DUMP_REG(DC_CMD_INT_POLARITY);
1362 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1363 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1364 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1365 DUMP_REG(DC_CMD_STATE_ACCESS);
1366 DUMP_REG(DC_CMD_STATE_CONTROL);
1367 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1368 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1369 DUMP_REG(DC_COM_CRC_CONTROL);
1370 DUMP_REG(DC_COM_CRC_CHECKSUM);
1371 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1372 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1373 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1374 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1375 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1376 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1377 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1378 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1379 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1380 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1381 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1382 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1383 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1384 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1385 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1386 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1387 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1388 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1389 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1390 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1391 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1392 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1393 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1394 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1395 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1396 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1397 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1398 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1399 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1400 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1401 DUMP_REG(DC_COM_SPI_CONTROL);
1402 DUMP_REG(DC_COM_SPI_START_BYTE);
1403 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1404 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1405 DUMP_REG(DC_COM_HSPI_CS_DC);
1406 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1407 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1408 DUMP_REG(DC_COM_GPIO_CTRL);
1409 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1410 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1411 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1412 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1413 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1414 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1415 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1416 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1417 DUMP_REG(DC_DISP_REF_TO_SYNC);
1418 DUMP_REG(DC_DISP_SYNC_WIDTH);
1419 DUMP_REG(DC_DISP_BACK_PORCH);
1420 DUMP_REG(DC_DISP_ACTIVE);
1421 DUMP_REG(DC_DISP_FRONT_PORCH);
1422 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1423 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1424 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1425 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1426 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1427 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1428 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1429 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1430 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1431 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1432 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1433 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1434 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1435 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1436 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1437 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1438 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1439 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1440 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1441 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1442 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1443 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1444 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1445 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1446 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1447 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1448 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1449 DUMP_REG(DC_DISP_M0_CONTROL);
1450 DUMP_REG(DC_DISP_M1_CONTROL);
1451 DUMP_REG(DC_DISP_DI_CONTROL);
1452 DUMP_REG(DC_DISP_PP_CONTROL);
1453 DUMP_REG(DC_DISP_PP_SELECT_A);
1454 DUMP_REG(DC_DISP_PP_SELECT_B);
1455 DUMP_REG(DC_DISP_PP_SELECT_C);
1456 DUMP_REG(DC_DISP_PP_SELECT_D);
1457 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1458 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1459 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1460 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1461 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1462 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1463 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1464 DUMP_REG(DC_DISP_BORDER_COLOR);
1465 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1466 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1467 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1468 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1469 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1470 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1471 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1472 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1473 DUMP_REG(DC_DISP_CURSOR_POSITION);
1474 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1475 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1476 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1477 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1478 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1479 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1480 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1481 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1482 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1483 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1484 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1485 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1486 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1487 DUMP_REG(DC_DISP_SD_CONTROL);
1488 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1489 DUMP_REG(DC_DISP_SD_LUT(0));
1490 DUMP_REG(DC_DISP_SD_LUT(1));
1491 DUMP_REG(DC_DISP_SD_LUT(2));
1492 DUMP_REG(DC_DISP_SD_LUT(3));
1493 DUMP_REG(DC_DISP_SD_LUT(4));
1494 DUMP_REG(DC_DISP_SD_LUT(5));
1495 DUMP_REG(DC_DISP_SD_LUT(6));
1496 DUMP_REG(DC_DISP_SD_LUT(7));
1497 DUMP_REG(DC_DISP_SD_LUT(8));
1498 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1499 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1500 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1501 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1502 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1503 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1504 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1505 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1506 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1507 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1508 DUMP_REG(DC_DISP_SD_BL_TF(0));
1509 DUMP_REG(DC_DISP_SD_BL_TF(1));
1510 DUMP_REG(DC_DISP_SD_BL_TF(2));
1511 DUMP_REG(DC_DISP_SD_BL_TF(3));
1512 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1513 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1514 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1515 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1516 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1517 DUMP_REG(DC_WIN_WIN_OPTIONS);
1518 DUMP_REG(DC_WIN_BYTE_SWAP);
1519 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1520 DUMP_REG(DC_WIN_COLOR_DEPTH);
1521 DUMP_REG(DC_WIN_POSITION);
1522 DUMP_REG(DC_WIN_SIZE);
1523 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1524 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1525 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1526 DUMP_REG(DC_WIN_DDA_INC);
1527 DUMP_REG(DC_WIN_LINE_STRIDE);
1528 DUMP_REG(DC_WIN_BUF_STRIDE);
1529 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1530 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1531 DUMP_REG(DC_WIN_DV_CONTROL);
1532 DUMP_REG(DC_WIN_BLEND_NOKEY);
1533 DUMP_REG(DC_WIN_BLEND_1WIN);
1534 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1535 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1536 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1537 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1538 DUMP_REG(DC_WINBUF_START_ADDR);
1539 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1540 DUMP_REG(DC_WINBUF_START_ADDR_U);
1541 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1542 DUMP_REG(DC_WINBUF_START_ADDR_V);
1543 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1544 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1545 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1546 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1547 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1548 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1549 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1550 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1551 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1552
1553#undef DUMP_REG
1554
1555 return 0;
1556}
1557
1558static struct drm_info_list debugfs_files[] = {
1559 { "regs", tegra_dc_show_regs, 0, NULL },
1560};
1561
1562static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1563{
1564 unsigned int i;
1565 char *name;
1566 int err;
1567
1568 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1569 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1570 kfree(name);
1571
1572 if (!dc->debugfs)
1573 return -ENOMEM;
1574
1575 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1576 GFP_KERNEL);
1577 if (!dc->debugfs_files) {
1578 err = -ENOMEM;
1579 goto remove;
1580 }
1581
1582 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1583 dc->debugfs_files[i].data = dc;
1584
1585 err = drm_debugfs_create_files(dc->debugfs_files,
1586 ARRAY_SIZE(debugfs_files),
1587 dc->debugfs, minor);
1588 if (err < 0)
1589 goto free;
1590
1591 dc->minor = minor;
1592
1593 return 0;
1594
1595free:
1596 kfree(dc->debugfs_files);
1597 dc->debugfs_files = NULL;
1598remove:
1599 debugfs_remove(dc->debugfs);
1600 dc->debugfs = NULL;
1601
1602 return err;
1603}
1604
1605static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1606{
1607 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1608 dc->minor);
1609 dc->minor = NULL;
1610
1611 kfree(dc->debugfs_files);
1612 dc->debugfs_files = NULL;
1613
1614 debugfs_remove(dc->debugfs);
1615 dc->debugfs = NULL;
1616
1617 return 0;
1618}
1619
53fa7f72 1620static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1621{
9910f5c4 1622 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1623 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1624 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1625 struct drm_plane *primary = NULL;
1626 struct drm_plane *cursor = NULL;
07d05cbf 1627 u32 value;
d8f4a9ed
TR		 1628 int err;
1629
df06b759
TR		 1630 if (tegra->domain) {
1631 err = iommu_attach_device(tegra->domain, dc->dev);
1632 if (err < 0) {
1633 dev_err(dc->dev, "failed to attach to domain: %d\n",
1634 err);
1635 return err;
1636 }
1637
1638 dc->domain = tegra->domain;
1639 }
1640
c7679306
TR		 1641 primary = tegra_dc_primary_plane_create(drm, dc);
1642 if (IS_ERR(primary)) {
1643 err = PTR_ERR(primary);
1644 goto cleanup;
1645 }
1646
1647 if (dc->soc->supports_cursor) {
1648 cursor = tegra_dc_cursor_plane_create(drm, dc);
1649 if (IS_ERR(cursor)) {
1650 err = PTR_ERR(cursor);
1651 goto cleanup;
1652 }
1653 }
1654
1655 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1656 &tegra_crtc_funcs);
1657 if (err < 0)
1658 goto cleanup;
1659
d8f4a9ed
TR		 1660 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1661 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1662
d1f3e1e0
TR		 1663 /*
1664 * Keep track of the minimum pitch alignment across all display
1665 * controllers.
1666 */
1667 if (dc->soc->pitch_align > tegra->pitch_align)
1668 tegra->pitch_align = dc->soc->pitch_align;
1669
9910f5c4 1670 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1671 if (err < 0 && err != -ENODEV) {
1672 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1673 goto cleanup;
d8f4a9ed
TR		 1674 }
1675
9910f5c4 1676 err = tegra_dc_add_planes(drm, dc);
f34bc787 1677 if (err < 0)
c7679306 1678 goto cleanup;
f34bc787 1679
d8f4a9ed 1680 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1681 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1682 if (err < 0)
1683 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1684 }
1685
6e5ff998 1686 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1687 dev_name(dc->dev), dc);
1688 if (err < 0) {
1689 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1690 err);
c7679306 1691 goto cleanup;
d8f4a9ed
TR		 1692 }
1693
07d05cbf 1694 /* initialize display controller */
42e9ce05
TR		 1695 if (dc->syncpt) {
1696 u32 syncpt = host1x_syncpt_id(dc->syncpt);
07d05cbf 1697
42e9ce05
TR		 1698 value = SYNCPT_CNTRL_NO_STALL;
1699 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1700
1701 value = SYNCPT_VSYNC_ENABLE | syncpt;
1702 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1703 }
07d05cbf
TR		 1704
1705 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1706 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1707
1708 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1709 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1710 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1711
1712 /* initialize timer */
1713 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1714 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1715 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1716
1717 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1718 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1719 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1720
1721 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1722 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1723
1724 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1725 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1726
1727 if (dc->soc->supports_border_color)
1728 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1729
d8f4a9ed 1730 return 0;
c7679306
TR		 1731
1732cleanup:
1733 if (cursor)
1734 drm_plane_cleanup(cursor);
1735
1736 if (primary)
1737 drm_plane_cleanup(primary);
1738
1739 if (tegra->domain) {
1740 iommu_detach_device(tegra->domain, dc->dev);
1741 dc->domain = NULL;
1742 }
1743
1744 return err;
d8f4a9ed
TR		 1745}
1746
53fa7f72 1747static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1748{
776dc384 1749 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1750 int err;
1751
1752 devm_free_irq(dc->dev, dc->irq, dc);
1753
1754 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1755 err = tegra_dc_debugfs_exit(dc);
1756 if (err < 0)
1757 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1758 }
1759
1760 err = tegra_dc_rgb_exit(dc);
1761 if (err) {
1762 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1763 return err;
1764 }
1765
df06b759
TR		 1766 if (dc->domain) {
1767 iommu_detach_device(dc->domain, dc->dev);
1768 dc->domain = NULL;
1769 }
1770
d8f4a9ed
TR		 1771 return 0;
1772}
1773
1774static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1775 .init = tegra_dc_init,
1776 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1777};
1778
8620fc62 1779static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1780 .supports_border_color = true,
8620fc62 1781 .supports_interlacing = false,
e687651b 1782 .supports_cursor = false,
c134f019 1783 .supports_block_linear = false,
d1f3e1e0 1784 .pitch_align = 8,
9c012700 1785 .has_powergate = false,
8620fc62
TR		 1786};
1787
1788static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1789 .supports_border_color = true,
8620fc62 1790 .supports_interlacing = false,
e687651b 1791 .supports_cursor = false,
c134f019 1792 .supports_block_linear = false,
d1f3e1e0 1793 .pitch_align = 8,
9c012700 1794 .has_powergate = false,
d1f3e1e0
TR		 1795};
1796
1797static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1798 .supports_border_color = true,
d1f3e1e0
TR		 1799 .supports_interlacing = false,
1800 .supports_cursor = false,
1801 .supports_block_linear = false,
1802 .pitch_align = 64,
9c012700 1803 .has_powergate = true,
8620fc62
TR		 1804};
1805
1806static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1807 .supports_border_color = false,
8620fc62 1808 .supports_interlacing = true,
e687651b 1809 .supports_cursor = true,
c134f019 1810 .supports_block_linear = true,
d1f3e1e0 1811 .pitch_align = 64,
9c012700 1812 .has_powergate = true,
8620fc62
TR		 1813};
1814
1815static const struct of_device_id tegra_dc_of_match[] = {
1816 {
1817 .compatible = "nvidia,tegra124-dc",
1818 .data = &tegra124_dc_soc_info,
9c012700
TR		 1819 }, {
1820 .compatible = "nvidia,tegra114-dc",
1821 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1822 }, {
1823 .compatible = "nvidia,tegra30-dc",
1824 .data = &tegra30_dc_soc_info,
1825 }, {
1826 .compatible = "nvidia,tegra20-dc",
1827 .data = &tegra20_dc_soc_info,
1828 }, {
1829 /* sentinel */
1830 }
1831};
ef70728c 1832MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1833
13411ddd
TR		 1834static int tegra_dc_parse_dt(struct tegra_dc *dc)
1835{
1836 struct device_node *np;
1837 u32 value = 0;
1838 int err;
1839
1840 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1841 if (err < 0) {
1842 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1843
1844 /*
1845 * If the nvidia,head property isn't present, try to find the
1846 * correct head number by looking up the position of this
1847 * display controller's node within the device tree. Assuming
1848 * that the nodes are ordered properly in the DTS file and
1849 * that the translation into a flattened device tree blob
1850 * preserves that ordering this will actually yield the right
1851 * head number.
1852 *
1853 * If those assumptions don't hold, this will still work for
1854 * cases where only a single display controller is used.
1855 */
1856 for_each_matching_node(np, tegra_dc_of_match) {
1857 if (np == dc->dev->of_node)
1858 break;
1859
1860 value++;
1861 }
1862 }
1863
1864 dc->pipe = value;
1865
1866 return 0;
1867}
1868
d8f4a9ed
TR		 1869static int tegra_dc_probe(struct platform_device *pdev)
1870{
42e9ce05 1871 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
8620fc62 1872 const struct of_device_id *id;
d8f4a9ed
TR		 1873 struct resource *regs;
1874 struct tegra_dc *dc;
1875 int err;
1876
1877 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1878 if (!dc)
1879 return -ENOMEM;
1880
8620fc62
TR		 1881 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1882 if (!id)
1883 return -ENODEV;
1884
6e5ff998 1885 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1886 INIT_LIST_HEAD(&dc->list);
1887 dc->dev = &pdev->dev;
8620fc62 1888 dc->soc = id->data;
d8f4a9ed 1889
13411ddd
TR		 1890 err = tegra_dc_parse_dt(dc);
1891 if (err < 0)
1892 return err;
1893
d8f4a9ed
TR		 1894 dc->clk = devm_clk_get(&pdev->dev, NULL);
1895 if (IS_ERR(dc->clk)) {
1896 dev_err(&pdev->dev, "failed to get clock\n");
1897 return PTR_ERR(dc->clk);
1898 }
1899
ca48080a
SW		 1900 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1901 if (IS_ERR(dc->rst)) {
1902 dev_err(&pdev->dev, "failed to get reset\n");
1903 return PTR_ERR(dc->rst);
1904 }
1905
9c012700
TR		 1906 if (dc->soc->has_powergate) {
1907 if (dc->pipe == 0)
1908 dc->powergate = TEGRA_POWERGATE_DIS;
1909 else
1910 dc->powergate = TEGRA_POWERGATE_DISB;
1911
1912 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1913 dc->rst);
1914 if (err < 0) {
1915 dev_err(&pdev->dev, "failed to power partition: %d\n",
1916 err);
1917 return err;
1918 }
1919 } else {
1920 err = clk_prepare_enable(dc->clk);
1921 if (err < 0) {
1922 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1923 err);
1924 return err;
1925 }
1926
1927 err = reset_control_deassert(dc->rst);
1928 if (err < 0) {
1929 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1930 err);
1931 return err;
1932 }
1933 }
d8f4a9ed
TR		 1934
1935 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1936 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1937 if (IS_ERR(dc->regs))
1938 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1939
1940 dc->irq = platform_get_irq(pdev, 0);
1941 if (dc->irq < 0) {
1942 dev_err(&pdev->dev, "failed to get IRQ\n");
1943 return -ENXIO;
1944 }
1945
776dc384
TR		 1946 INIT_LIST_HEAD(&dc->client.list);
1947 dc->client.ops = &dc_client_ops;
1948 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1949
1950 err = tegra_dc_rgb_probe(dc);
1951 if (err < 0 && err != -ENODEV) {
1952 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1953 return err;
1954 }
1955
776dc384 1956 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1957 if (err < 0) {
1958 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1959 err);
1960 return err;
1961 }
1962
42e9ce05
TR		 1963 dc->syncpt = host1x_syncpt_request(&pdev->dev, flags);
1964 if (!dc->syncpt)
1965 dev_warn(&pdev->dev, "failed to allocate syncpoint\n");
1966
d8f4a9ed
TR		 1967 platform_set_drvdata(pdev, dc);
1968
1969 return 0;
1970}
1971
1972static int tegra_dc_remove(struct platform_device *pdev)
1973{
d8f4a9ed
TR		 1974 struct tegra_dc *dc = platform_get_drvdata(pdev);
1975 int err;
1976
42e9ce05
TR		 1977 host1x_syncpt_free(dc->syncpt);
1978
776dc384 1979 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1980 if (err < 0) {
1981 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1982 err);
1983 return err;
1984 }
1985
59d29c0e
TR		 1986 err = tegra_dc_rgb_remove(dc);
1987 if (err < 0) {
1988 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1989 return err;
1990 }
1991
5482d75a 1992 reset_control_assert(dc->rst);
9c012700
TR		 1993
1994 if (dc->soc->has_powergate)
1995 tegra_powergate_power_off(dc->powergate);
1996
d8f4a9ed
TR		 1997 clk_disable_unprepare(dc->clk);
1998
1999 return 0;
2000}
2001
d8f4a9ed
TR		 2002struct platform_driver tegra_dc_driver = {
2003 .driver = {
2004 .name = "tegra-dc",
2005 .owner = THIS_MODULE,
2006 .of_match_table = tegra_dc_of_match,
2007 },
2008 .probe = tegra_dc_probe,
2009 .remove = tegra_dc_remove,
2010};
Linux kernel - Deliverables
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