projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/tegra: dc: Describe register copies
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
df06b759 12#include <linux/iommu.h>
ca48080a 13#include <linux/reset.h>
d8f4a9ed 14
9c012700
TR		 15#include <soc/tegra/pmc.h>
16
de2ba664
AM		 17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
d8f4a9ed 20
3cb9ae4f
DV		 21#include <drm/drm_plane_helper.h>
22
8620fc62 23struct tegra_dc_soc_info {
42d0659b 24 bool supports_border_color;
8620fc62 25 bool supports_interlacing;
e687651b 26 bool supports_cursor;
c134f019 27 bool supports_block_linear;
d1f3e1e0 28 unsigned int pitch_align;
9c012700 29 bool has_powergate;
8620fc62
TR		 30};
31
f34bc787
TR		 32struct tegra_plane {
33 struct drm_plane base;
34 unsigned int index;
d8f4a9ed
TR		 35};
36
f34bc787
TR		 37static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
38{
39 return container_of(plane, struct tegra_plane, base);
40}
41
205d48ed
TR		 42static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index)
43{
44 u32 value = WIN_A_ACT_REQ << index;
45
46 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
47 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
48}
49
50static void tegra_dc_cursor_commit(struct tegra_dc *dc)
51{
52 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
53 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
54}
55
d700ba7a
TR		 56/*
57 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
58 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
59 * Latching happens mmediately if the display controller is in STOP mode or
60 * on the next frame boundary otherwise.
61 *
62 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
63 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
64 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
65 * into the ACTIVE copy, either immediately if the display controller is in
66 * STOP mode, or at the next frame boundary otherwise.
67 */
205d48ed
TR		 68static void tegra_dc_commit(struct tegra_dc *dc)
69{
70 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
71 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
72}
73
10288eea
TR		 74static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
75{
76 /* assume no swapping of fetched data */
77 if (swap)
78 *swap = BYTE_SWAP_NOSWAP;
79
80 switch (format) {
81 case DRM_FORMAT_XBGR8888:
82 return WIN_COLOR_DEPTH_R8G8B8A8;
83
84 case DRM_FORMAT_XRGB8888:
85 return WIN_COLOR_DEPTH_B8G8R8A8;
86
87 case DRM_FORMAT_RGB565:
88 return WIN_COLOR_DEPTH_B5G6R5;
89
90 case DRM_FORMAT_UYVY:
91 return WIN_COLOR_DEPTH_YCbCr422;
92
93 case DRM_FORMAT_YUYV:
94 if (swap)
95 *swap = BYTE_SWAP_SWAP2;
96
97 return WIN_COLOR_DEPTH_YCbCr422;
98
99 case DRM_FORMAT_YUV420:
100 return WIN_COLOR_DEPTH_YCbCr420P;
101
102 case DRM_FORMAT_YUV422:
103 return WIN_COLOR_DEPTH_YCbCr422P;
104
105 default:
106 break;
107 }
108
109 WARN(1, "unsupported pixel format %u, using default\n", format);
110 return WIN_COLOR_DEPTH_B8G8R8A8;
111}
112
113static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
114{
115 switch (format) {
116 case WIN_COLOR_DEPTH_YCbCr422:
117 case WIN_COLOR_DEPTH_YUV422:
118 if (planar)
119 *planar = false;
120
121 return true;
122
123 case WIN_COLOR_DEPTH_YCbCr420P:
124 case WIN_COLOR_DEPTH_YUV420P:
125 case WIN_COLOR_DEPTH_YCbCr422P:
126 case WIN_COLOR_DEPTH_YUV422P:
127 case WIN_COLOR_DEPTH_YCbCr422R:
128 case WIN_COLOR_DEPTH_YUV422R:
129 case WIN_COLOR_DEPTH_YCbCr422RA:
130 case WIN_COLOR_DEPTH_YUV422RA:
131 if (planar)
132 *planar = true;
133
134 return true;
135 }
136
137 return false;
138}
139
140static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
141 unsigned int bpp)
142{
143 fixed20_12 outf = dfixed_init(out);
144 fixed20_12 inf = dfixed_init(in);
145 u32 dda_inc;
146 int max;
147
148 if (v)
149 max = 15;
150 else {
151 switch (bpp) {
152 case 2:
153 max = 8;
154 break;
155
156 default:
157 WARN_ON_ONCE(1);
158 /* fallthrough */
159 case 4:
160 max = 4;
161 break;
162 }
163 }
164
165 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
166 inf.full -= dfixed_const(1);
167
168 dda_inc = dfixed_div(inf, outf);
169 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
170
171 return dda_inc;
172}
173
174static inline u32 compute_initial_dda(unsigned int in)
175{
176 fixed20_12 inf = dfixed_init(in);
177 return dfixed_frac(inf);
178}
179
180static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
181 const struct tegra_dc_window *window)
182{
183 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
93396d0f 184 unsigned long value, flags;
10288eea
TR		 185 bool yuv, planar;
186
187 /*
188 * For YUV planar modes, the number of bytes per pixel takes into
189 * account only the luma component and therefore is 1.
190 */
191 yuv = tegra_dc_format_is_yuv(window->format, &planar);
192 if (!yuv)
193 bpp = window->bits_per_pixel / 8;
194 else
195 bpp = planar ? 1 : 2;
196
93396d0f
SP		 197 spin_lock_irqsave(&dc->lock, flags);
198
10288eea
TR		 199 value = WINDOW_A_SELECT << index;
200 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
201
202 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
203 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
204
205 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
206 tegra_dc_writel(dc, value, DC_WIN_POSITION);
207
208 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
209 tegra_dc_writel(dc, value, DC_WIN_SIZE);
210
211 h_offset = window->src.x * bpp;
212 v_offset = window->src.y;
213 h_size = window->src.w * bpp;
214 v_size = window->src.h;
215
216 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
217 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
218
219 /*
220 * For DDA computations the number of bytes per pixel for YUV planar
221 * modes needs to take into account all Y, U and V components.
222 */
223 if (yuv && planar)
224 bpp = 2;
225
226 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
227 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
228
229 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
230 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
231
232 h_dda = compute_initial_dda(window->src.x);
233 v_dda = compute_initial_dda(window->src.y);
234
235 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
236 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
237
238 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
239 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
240
241 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
242
243 if (yuv && planar) {
244 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
245 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
246 value = window->stride[1] << 16 | window->stride[0];
247 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
248 } else {
249 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
250 }
251
252 if (window->bottom_up)
253 v_offset += window->src.h - 1;
254
255 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
256 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
257
c134f019
TR		 258 if (dc->soc->supports_block_linear) {
259 unsigned long height = window->tiling.value;
260
261 switch (window->tiling.mode) {
262 case TEGRA_BO_TILING_MODE_PITCH:
263 value = DC_WINBUF_SURFACE_KIND_PITCH;
264 break;
265
266 case TEGRA_BO_TILING_MODE_TILED:
267 value = DC_WINBUF_SURFACE_KIND_TILED;
268 break;
269
270 case TEGRA_BO_TILING_MODE_BLOCK:
271 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
272 DC_WINBUF_SURFACE_KIND_BLOCK;
273 break;
274 }
275
276 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
10288eea 277 } else {
c134f019
TR		 278 switch (window->tiling.mode) {
279 case TEGRA_BO_TILING_MODE_PITCH:
280 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
281 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
282 break;
10288eea 283
c134f019
TR		 284 case TEGRA_BO_TILING_MODE_TILED:
285 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
286 DC_WIN_BUFFER_ADDR_MODE_TILE;
287 break;
288
289 case TEGRA_BO_TILING_MODE_BLOCK:
290 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 291 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 292 return -EINVAL;
293 }
294
295 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
296 }
10288eea
TR		 297
298 value = WIN_ENABLE;
299
300 if (yuv) {
301 /* setup default colorspace conversion coefficients */
302 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
303 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
304 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
305 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
306 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
307 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
308 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
309 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
310
311 value |= CSC_ENABLE;
312 } else if (window->bits_per_pixel < 24) {
313 value |= COLOR_EXPAND;
314 }
315
316 if (window->bottom_up)
317 value |= V_DIRECTION;
318
319 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
320
321 /*
322 * Disable blending and assume Window A is the bottom-most window,
323 * Window C is the top-most window and Window B is in the middle.
324 */
325 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
326 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
327
328 switch (index) {
329 case 0:
330 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
331 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
332 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
333 break;
334
335 case 1:
336 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
337 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
338 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
339 break;
340
341 case 2:
342 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
343 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
344 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
345 break;
346 }
347
205d48ed 348 tegra_dc_window_commit(dc, index);
10288eea 349
93396d0f
SP		 350 spin_unlock_irqrestore(&dc->lock, flags);
351
10288eea
TR		 352 return 0;
353}
354
c7679306
TR		 355static int tegra_window_plane_disable(struct drm_plane *plane)
356{
357 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
358 struct tegra_plane *p = to_tegra_plane(plane);
93396d0f 359 unsigned long flags;
c7679306
TR		 360 u32 value;
361
362 if (!plane->crtc)
363 return 0;
364
93396d0f
SP		 365 spin_lock_irqsave(&dc->lock, flags);
366
c7679306
TR		 367 value = WINDOW_A_SELECT << p->index;
368 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
369
370 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
371 value &= ~WIN_ENABLE;
372 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
373
374 tegra_dc_window_commit(dc, p->index);
375
93396d0f
SP		 376 spin_unlock_irqrestore(&dc->lock, flags);
377
c7679306
TR		 378 return 0;
379}
380
381static void tegra_plane_destroy(struct drm_plane *plane)
382{
383 struct tegra_plane *p = to_tegra_plane(plane);
384
385 drm_plane_cleanup(plane);
386 kfree(p);
387}
388
389static const u32 tegra_primary_plane_formats[] = {
390 DRM_FORMAT_XBGR8888,
391 DRM_FORMAT_XRGB8888,
392 DRM_FORMAT_RGB565,
393};
394
395static int tegra_primary_plane_update(struct drm_plane *plane,
396 struct drm_crtc *crtc,
397 struct drm_framebuffer *fb, int crtc_x,
398 int crtc_y, unsigned int crtc_w,
399 unsigned int crtc_h, uint32_t src_x,
400 uint32_t src_y, uint32_t src_w,
401 uint32_t src_h)
402{
403 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
404 struct tegra_plane *p = to_tegra_plane(plane);
405 struct tegra_dc *dc = to_tegra_dc(crtc);
406 struct tegra_dc_window window;
407 int err;
408
409 memset(&window, 0, sizeof(window));
410 window.src.x = src_x >> 16;
411 window.src.y = src_y >> 16;
412 window.src.w = src_w >> 16;
413 window.src.h = src_h >> 16;
414 window.dst.x = crtc_x;
415 window.dst.y = crtc_y;
416 window.dst.w = crtc_w;
417 window.dst.h = crtc_h;
418 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
419 window.bits_per_pixel = fb->bits_per_pixel;
420 window.bottom_up = tegra_fb_is_bottom_up(fb);
421
422 err = tegra_fb_get_tiling(fb, &window.tiling);
423 if (err < 0)
424 return err;
425
426 window.base[0] = bo->paddr + fb->offsets[0];
427 window.stride[0] = fb->pitches[0];
428
429 err = tegra_dc_setup_window(dc, p->index, &window);
430 if (err < 0)
431 return err;
10288eea
TR		 432
433 return 0;
434}
435
c7679306
TR		 436static void tegra_primary_plane_destroy(struct drm_plane *plane)
437{
438 tegra_window_plane_disable(plane);
439 tegra_plane_destroy(plane);
440}
441
442static const struct drm_plane_funcs tegra_primary_plane_funcs = {
443 .update_plane = tegra_primary_plane_update,
444 .disable_plane = tegra_window_plane_disable,
445 .destroy = tegra_primary_plane_destroy,
446};
447
448static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
449 struct tegra_dc *dc)
450{
518e6227
TR		 451 /*
452 * Ideally this would use drm_crtc_mask(), but that would require the
453 * CRTC to already be in the mode_config's list of CRTCs. However, it
454 * will only be added to that list in the drm_crtc_init_with_planes()
455 * (in tegra_dc_init()), which in turn requires registration of these
456 * planes. So we have ourselves a nice little chicken and egg problem
457 * here.
458 *
459 * We work around this by manually creating the mask from the number
460 * of CRTCs that have been registered, and should therefore always be
461 * the same as drm_crtc_index() after registration.
462 */
463 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
c7679306
TR		 464 struct tegra_plane *plane;
465 unsigned int num_formats;
466 const u32 *formats;
467 int err;
468
469 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
470 if (!plane)
471 return ERR_PTR(-ENOMEM);
472
473 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
474 formats = tegra_primary_plane_formats;
475
518e6227 476 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
c7679306
TR		 477 &tegra_primary_plane_funcs, formats,
478 num_formats, DRM_PLANE_TYPE_PRIMARY);
479 if (err < 0) {
480 kfree(plane);
481 return ERR_PTR(err);
482 }
483
484 return &plane->base;
485}
486
487static const u32 tegra_cursor_plane_formats[] = {
488 DRM_FORMAT_RGBA8888,
489};
490
491static int tegra_cursor_plane_update(struct drm_plane *plane,
492 struct drm_crtc *crtc,
493 struct drm_framebuffer *fb, int crtc_x,
494 int crtc_y, unsigned int crtc_w,
495 unsigned int crtc_h, uint32_t src_x,
496 uint32_t src_y, uint32_t src_w,
497 uint32_t src_h)
498{
499 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
500 struct tegra_dc *dc = to_tegra_dc(crtc);
501 u32 value = CURSOR_CLIP_DISPLAY;
502
503 /* scaling not supported for cursor */
504 if ((src_w >> 16 != crtc_w) || (src_h >> 16 != crtc_h))
505 return -EINVAL;
506
507 /* only square cursors supported */
508 if (src_w != src_h)
509 return -EINVAL;
510
511 switch (crtc_w) {
512 case 32:
513 value |= CURSOR_SIZE_32x32;
514 break;
515
516 case 64:
517 value |= CURSOR_SIZE_64x64;
518 break;
519
520 case 128:
521 value |= CURSOR_SIZE_128x128;
522 break;
523
524 case 256:
525 value |= CURSOR_SIZE_256x256;
526 break;
527
528 default:
529 return -EINVAL;
530 }
531
532 value |= (bo->paddr >> 10) & 0x3fffff;
533 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
534
535#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
536 value = (bo->paddr >> 32) & 0x3;
537 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
538#endif
539
540 /* enable cursor and set blend mode */
541 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
542 value |= CURSOR_ENABLE;
543 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
544
545 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
546 value &= ~CURSOR_DST_BLEND_MASK;
547 value &= ~CURSOR_SRC_BLEND_MASK;
548 value |= CURSOR_MODE_NORMAL;
549 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
550 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
551 value |= CURSOR_ALPHA;
552 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
553
554 /* position the cursor */
555 value = (crtc_y & 0x3fff) << 16 | (crtc_x & 0x3fff);
556 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
557
558 /* apply changes */
559 tegra_dc_cursor_commit(dc);
560 tegra_dc_commit(dc);
561
562 return 0;
563}
564
565static int tegra_cursor_plane_disable(struct drm_plane *plane)
566{
567 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
568 u32 value;
569
570 if (!plane->crtc)
571 return 0;
572
573 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
574 value &= ~CURSOR_ENABLE;
575 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
576
577 tegra_dc_cursor_commit(dc);
578 tegra_dc_commit(dc);
579
580 return 0;
581}
582
583static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
584 .update_plane = tegra_cursor_plane_update,
585 .disable_plane = tegra_cursor_plane_disable,
586 .destroy = tegra_plane_destroy,
587};
588
589static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
590 struct tegra_dc *dc)
591{
592 struct tegra_plane *plane;
593 unsigned int num_formats;
594 const u32 *formats;
595 int err;
596
597 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
598 if (!plane)
599 return ERR_PTR(-ENOMEM);
600
601 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
602 formats = tegra_cursor_plane_formats;
603
604 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
605 &tegra_cursor_plane_funcs, formats,
606 num_formats, DRM_PLANE_TYPE_CURSOR);
607 if (err < 0) {
608 kfree(plane);
609 return ERR_PTR(err);
610 }
611
612 return &plane->base;
613}
614
615static int tegra_overlay_plane_update(struct drm_plane *plane,
616 struct drm_crtc *crtc,
617 struct drm_framebuffer *fb, int crtc_x,
618 int crtc_y, unsigned int crtc_w,
619 unsigned int crtc_h, uint32_t src_x,
620 uint32_t src_y, uint32_t src_w,
621 uint32_t src_h)
f34bc787
TR		 622{
623 struct tegra_plane *p = to_tegra_plane(plane);
624 struct tegra_dc *dc = to_tegra_dc(crtc);
625 struct tegra_dc_window window;
626 unsigned int i;
c134f019 627 int err;
f34bc787
TR		 628
629 memset(&window, 0, sizeof(window));
630 window.src.x = src_x >> 16;
631 window.src.y = src_y >> 16;
632 window.src.w = src_w >> 16;
633 window.src.h = src_h >> 16;
634 window.dst.x = crtc_x;
635 window.dst.y = crtc_y;
636 window.dst.w = crtc_w;
637 window.dst.h = crtc_h;
f925390e 638 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
f34bc787 639 window.bits_per_pixel = fb->bits_per_pixel;
db7fbdfd 640 window.bottom_up = tegra_fb_is_bottom_up(fb);
c134f019
TR		 641
642 err = tegra_fb_get_tiling(fb, &window.tiling);
643 if (err < 0)
644 return err;
f34bc787
TR		 645
646 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 647 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 648
de2ba664 649 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 650
651 /*
652 * Tegra doesn't support different strides for U and V planes
653 * so we display a warning if the user tries to display a
654 * framebuffer with such a configuration.
655 */
656 if (i >= 2) {
657 if (fb->pitches[i] != window.stride[1])
658 DRM_ERROR("unsupported UV-plane configuration\n");
659 } else {
660 window.stride[i] = fb->pitches[i];
661 }
662 }
663
664 return tegra_dc_setup_window(dc, p->index, &window);
665}
666
c7679306 667static void tegra_overlay_plane_destroy(struct drm_plane *plane)
f34bc787 668{
c7679306
TR		 669 tegra_window_plane_disable(plane);
670 tegra_plane_destroy(plane);
f34bc787
TR		 671}
672
c7679306
TR		 673static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
674 .update_plane = tegra_overlay_plane_update,
675 .disable_plane = tegra_window_plane_disable,
676 .destroy = tegra_overlay_plane_destroy,
f34bc787
TR		 677};
678
c7679306 679static const uint32_t tegra_overlay_plane_formats[] = {
dbe4d9a7 680 DRM_FORMAT_XBGR8888,
f34bc787 681 DRM_FORMAT_XRGB8888,
dbe4d9a7 682 DRM_FORMAT_RGB565,
f34bc787 683 DRM_FORMAT_UYVY,
f925390e 684 DRM_FORMAT_YUYV,
f34bc787
TR		 685 DRM_FORMAT_YUV420,
686 DRM_FORMAT_YUV422,
687};
688
c7679306
TR		 689static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
690 struct tegra_dc *dc,
691 unsigned int index)
f34bc787 692{
c7679306
TR		 693 struct tegra_plane *plane;
694 unsigned int num_formats;
695 const u32 *formats;
696 int err;
f34bc787 697
c7679306
TR		 698 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
699 if (!plane)
700 return ERR_PTR(-ENOMEM);
f34bc787 701
c7679306 702 plane->index = index;
f34bc787 703
c7679306
TR		 704 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
705 formats = tegra_overlay_plane_formats;
f34bc787 706
c7679306
TR		 707 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
708 &tegra_overlay_plane_funcs, formats,
709 num_formats, DRM_PLANE_TYPE_OVERLAY);
710 if (err < 0) {
711 kfree(plane);
712 return ERR_PTR(err);
713 }
714
715 return &plane->base;
716}
717
718static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
719{
720 struct drm_plane *plane;
721 unsigned int i;
722
723 for (i = 0; i < 2; i++) {
724 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
725 if (IS_ERR(plane))
726 return PTR_ERR(plane);
f34bc787
TR		 727 }
728
729 return 0;
730}
731
23fb4740
TR		 732static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
733 struct drm_framebuffer *fb)
734{
de2ba664 735 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
db7fbdfd 736 unsigned int h_offset = 0, v_offset = 0;
c134f019 737 struct tegra_bo_tiling tiling;
93396d0f 738 unsigned long value, flags;
f925390e 739 unsigned int format, swap;
c134f019
TR		 740 int err;
741
742 err = tegra_fb_get_tiling(fb, &tiling);
743 if (err < 0)
744 return err;
23fb4740 745
93396d0f
SP		 746 spin_lock_irqsave(&dc->lock, flags);
747
23fb4740
TR		 748 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
749
750 value = fb->offsets[0] + y * fb->pitches[0] +
751 x * fb->bits_per_pixel / 8;
752
de2ba664 753 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 754 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
f925390e
TR		 755
756 format = tegra_dc_format(fb->pixel_format, &swap);
ed683aea 757 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
f925390e 758 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
23fb4740 759
c134f019
TR		 760 if (dc->soc->supports_block_linear) {
761 unsigned long height = tiling.value;
762
763 switch (tiling.mode) {
764 case TEGRA_BO_TILING_MODE_PITCH:
765 value = DC_WINBUF_SURFACE_KIND_PITCH;
766 break;
767
768 case TEGRA_BO_TILING_MODE_TILED:
769 value = DC_WINBUF_SURFACE_KIND_TILED;
770 break;
771
772 case TEGRA_BO_TILING_MODE_BLOCK:
773 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
774 DC_WINBUF_SURFACE_KIND_BLOCK;
775 break;
776 }
777
778 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
773af77f 779 } else {
c134f019
TR		 780 switch (tiling.mode) {
781 case TEGRA_BO_TILING_MODE_PITCH:
782 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
783 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
784 break;
773af77f 785
c134f019
TR		 786 case TEGRA_BO_TILING_MODE_TILED:
787 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
788 DC_WIN_BUFFER_ADDR_MODE_TILE;
789 break;
790
791 case TEGRA_BO_TILING_MODE_BLOCK:
792 DRM_ERROR("hardware doesn't support block linear mode\n");
93396d0f 793 spin_unlock_irqrestore(&dc->lock, flags);
c134f019
TR		 794 return -EINVAL;
795 }
796
797 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
798 }
773af77f 799
db7fbdfd
TR		 800 /* make sure bottom-up buffers are properly displayed */
801 if (tegra_fb_is_bottom_up(fb)) {
802 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 803 value |= V_DIRECTION;
db7fbdfd
TR		 804 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
805
806 v_offset += fb->height - 1;
807 } else {
808 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 809 value &= ~V_DIRECTION;
db7fbdfd
TR		 810 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
811 }
812
813 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
814 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
815
23fb4740 816 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
205d48ed 817 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
23fb4740
TR		 818 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
819
93396d0f
SP		 820 spin_unlock_irqrestore(&dc->lock, flags);
821
23fb4740
TR		 822 return 0;
823}
824
6e5ff998
TR		 825void tegra_dc_enable_vblank(struct tegra_dc *dc)
826{
827 unsigned long value, flags;
828
829 spin_lock_irqsave(&dc->lock, flags);
830
831 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
832 value |= VBLANK_INT;
833 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
834
835 spin_unlock_irqrestore(&dc->lock, flags);
836}
837
838void tegra_dc_disable_vblank(struct tegra_dc *dc)
839{
840 unsigned long value, flags;
841
842 spin_lock_irqsave(&dc->lock, flags);
843
844 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
845 value &= ~VBLANK_INT;
846 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
847
848 spin_unlock_irqrestore(&dc->lock, flags);
849}
850
3c03c46a
TR		 851static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
852{
853 struct drm_device *drm = dc->base.dev;
854 struct drm_crtc *crtc = &dc->base;
3c03c46a 855 unsigned long flags, base;
de2ba664 856 struct tegra_bo *bo;
3c03c46a 857
6b59cc1c
TR		 858 spin_lock_irqsave(&drm->event_lock, flags);
859
860 if (!dc->event) {
861 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a 862 return;
6b59cc1c 863 }
3c03c46a 864
f4510a27 865 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a 866
93396d0f
SP		 867 spin_lock_irqsave(&dc->lock, flags);
868
3c03c46a 869 /* check if new start address has been latched */
93396d0f 870 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
3c03c46a
TR		 871 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
872 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
873 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
874
93396d0f
SP		 875 spin_unlock_irqrestore(&dc->lock, flags);
876
f4510a27 877 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
ed7dae58
TR		 878 drm_crtc_send_vblank_event(crtc, dc->event);
879 drm_crtc_vblank_put(crtc);
3c03c46a 880 dc->event = NULL;
3c03c46a 881 }
6b59cc1c
TR		 882
883 spin_unlock_irqrestore(&drm->event_lock, flags);
3c03c46a
TR		 884}
885
886void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
887{
888 struct tegra_dc *dc = to_tegra_dc(crtc);
889 struct drm_device *drm = crtc->dev;
890 unsigned long flags;
891
892 spin_lock_irqsave(&drm->event_lock, flags);
893
894 if (dc->event && dc->event->base.file_priv == file) {
895 dc->event->base.destroy(&dc->event->base);
ed7dae58 896 drm_crtc_vblank_put(crtc);
3c03c46a
TR		 897 dc->event = NULL;
898 }
899
900 spin_unlock_irqrestore(&drm->event_lock, flags);
901}
902
903static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 904 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a 905{
ed7dae58 906 unsigned int pipe = drm_crtc_index(crtc);
3c03c46a 907 struct tegra_dc *dc = to_tegra_dc(crtc);
3c03c46a
TR		 908
909 if (dc->event)
910 return -EBUSY;
911
912 if (event) {
ed7dae58 913 event->pipe = pipe;
3c03c46a 914 dc->event = event;
ed7dae58 915 drm_crtc_vblank_get(crtc);
3c03c46a
TR		 916 }
917
918 tegra_dc_set_base(dc, 0, 0, fb);
f4510a27 919 crtc->primary->fb = fb;
3c03c46a
TR		 920
921 return 0;
922}
923
f002abc1
TR		 924static void tegra_dc_destroy(struct drm_crtc *crtc)
925{
926 drm_crtc_cleanup(crtc);
f002abc1
TR		 927}
928
d8f4a9ed 929static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 930 .page_flip = tegra_dc_page_flip,
d8f4a9ed 931 .set_config = drm_crtc_helper_set_config,
f002abc1 932 .destroy = tegra_dc_destroy,
d8f4a9ed
TR		 933};
934
f34bc787 935static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 936{
f002abc1 937 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787
TR		 938 struct drm_device *drm = crtc->dev;
939 struct drm_plane *plane;
940
2b4c3661 941 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
f34bc787 942 if (plane->crtc == crtc) {
c7679306 943 tegra_window_plane_disable(plane);
f34bc787
TR		 944 plane->crtc = NULL;
945
946 if (plane->fb) {
947 drm_framebuffer_unreference(plane->fb);
948 plane->fb = NULL;
949 }
950 }
951 }
f002abc1 952
8ff64c17 953 drm_crtc_vblank_off(crtc);
c7679306 954 tegra_dc_commit(dc);
d8f4a9ed
TR		 955}
956
957static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
958 const struct drm_display_mode *mode,
959 struct drm_display_mode *adjusted)
960{
961 return true;
962}
963
d8f4a9ed
TR		 964static int tegra_dc_set_timings(struct tegra_dc *dc,
965 struct drm_display_mode *mode)
966{
0444c0ff
TR		 967 unsigned int h_ref_to_sync = 1;
968 unsigned int v_ref_to_sync = 1;
d8f4a9ed
TR		 969 unsigned long value;
970
971 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
972
973 value = (v_ref_to_sync << 16) | h_ref_to_sync;
974 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
975
976 value = ((mode->vsync_end - mode->vsync_start) << 16) |
977 ((mode->hsync_end - mode->hsync_start) << 0);
978 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
979
d8f4a9ed
TR		 980 value = ((mode->vtotal - mode->vsync_end) << 16) |
981 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 982 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
983
984 value = ((mode->vsync_start - mode->vdisplay) << 16) |
985 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 986 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
987
988 value = (mode->vdisplay << 16) | mode->hdisplay;
989 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
990
991 return 0;
992}
993
994static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
dbb3f2f7 995 struct drm_display_mode *mode)
d8f4a9ed 996{
91eded9b 997 unsigned long pclk = mode->clock * 1000;
d8f4a9ed
TR		 998 struct tegra_dc *dc = to_tegra_dc(crtc);
999 struct tegra_output *output = NULL;
1000 struct drm_encoder *encoder;
dbb3f2f7
TR		 1001 unsigned int div;
1002 u32 value;
d8f4a9ed
TR		 1003 long err;
1004
1005 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
1006 if (encoder->crtc == crtc) {
1007 output = encoder_to_output(encoder);
1008 break;
1009 }
1010
1011 if (!output)
1012 return -ENODEV;
1013
1014 /*
91eded9b
TR		 1015 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
1016 * respectively, each of which divides the base pll_d by 2.
d8f4a9ed 1017 */
91eded9b 1018 err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
d8f4a9ed
TR		 1019 if (err < 0) {
1020 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
1021 return err;
1022 }
1023
91eded9b 1024 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
d8f4a9ed 1025
dbb3f2f7
TR		 1026 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
1027 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
d8f4a9ed
TR		 1028
1029 return 0;
1030}
1031
1032static int tegra_crtc_mode_set(struct drm_crtc *crtc,
1033 struct drm_display_mode *mode,
1034 struct drm_display_mode *adjusted,
1035 int x, int y, struct drm_framebuffer *old_fb)
1036{
f4510a27 1037 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
d8f4a9ed 1038 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 1039 struct tegra_dc_window window;
dbb3f2f7 1040 u32 value;
d8f4a9ed
TR		 1041 int err;
1042
dbb3f2f7 1043 err = tegra_crtc_setup_clk(crtc, mode);
d8f4a9ed
TR		 1044 if (err) {
1045 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
1046 return err;
1047 }
1048
1049 /* program display mode */
1050 tegra_dc_set_timings(dc, mode);
1051
42d0659b
TR		 1052 if (dc->soc->supports_border_color)
1053 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1054
8620fc62
TR		 1055 /* interlacing isn't supported yet, so disable it */
1056 if (dc->soc->supports_interlacing) {
1057 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1058 value &= ~INTERLACE_ENABLE;
1059 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1060 }
1061
d8f4a9ed 1062 /* setup window parameters */
f34bc787
TR		 1063 memset(&window, 0, sizeof(window));
1064 window.src.x = 0;
1065 window.src.y = 0;
1066 window.src.w = mode->hdisplay;
1067 window.src.h = mode->vdisplay;
1068 window.dst.x = 0;
1069 window.dst.y = 0;
1070 window.dst.w = mode->hdisplay;
1071 window.dst.h = mode->vdisplay;
f925390e
TR		 1072 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
1073 &window.swap);
f4510a27
MR		 1074 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
1075 window.stride[0] = crtc->primary->fb->pitches[0];
de2ba664 1076 window.base[0] = bo->paddr;
f34bc787
TR		 1077
1078 err = tegra_dc_setup_window(dc, 0, &window);
1079 if (err < 0)
1080 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 1081
d8f4a9ed
TR		 1082 return 0;
1083}
d8f4a9ed 1084
23fb4740
TR		 1085static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1086 struct drm_framebuffer *old_fb)
1087{
1088 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1089
f4510a27 1090 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
d8f4a9ed
TR		 1091}
1092
1093static void tegra_crtc_prepare(struct drm_crtc *crtc)
1094{
1095 struct tegra_dc *dc = to_tegra_dc(crtc);
1096 unsigned int syncpt;
1097 unsigned long value;
1098
8ff64c17
TR		 1099 drm_crtc_vblank_off(crtc);
1100
d8f4a9ed 1101 /* hardware initialization */
ca48080a 1102 reset_control_deassert(dc->rst);
d8f4a9ed
TR		 1103 usleep_range(10000, 20000);
1104
1105 if (dc->pipe)
1106 syncpt = SYNCPT_VBLANK1;
1107 else
1108 syncpt = SYNCPT_VBLANK0;
1109
1110 /* initialize display controller */
1111 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1112 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1113
1114 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1115 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1116
1117 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1118 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1119 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1120
d8f4a9ed
TR		 1121 /* initialize timer */
1122 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1123 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1124 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1125
1126 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1127 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1128 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1129
d8f4a9ed
TR		 1130 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1131 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 1132
1133 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1134 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 1135}
1136
1137static void tegra_crtc_commit(struct drm_crtc *crtc)
1138{
1139 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 1140
8ff64c17 1141 drm_crtc_vblank_on(crtc);
205d48ed 1142 tegra_dc_commit(dc);
d8f4a9ed
TR		 1143}
1144
d8f4a9ed 1145static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 1146 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 1147 .mode_fixup = tegra_crtc_mode_fixup,
1148 .mode_set = tegra_crtc_mode_set,
23fb4740 1149 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 1150 .prepare = tegra_crtc_prepare,
1151 .commit = tegra_crtc_commit,
d8f4a9ed
TR		 1152};
1153
6e5ff998 1154static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 1155{
1156 struct tegra_dc *dc = data;
1157 unsigned long status;
1158
1159 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1160 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1161
1162 if (status & FRAME_END_INT) {
1163 /*
1164 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1165 */
1166 }
1167
1168 if (status & VBLANK_INT) {
1169 /*
1170 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1171 */
ed7dae58 1172 drm_crtc_handle_vblank(&dc->base);
3c03c46a 1173 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 1174 }
1175
1176 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1177 /*
1178 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1179 */
1180 }
1181
1182 return IRQ_HANDLED;
1183}
1184
1185static int tegra_dc_show_regs(struct seq_file *s, void *data)
1186{
1187 struct drm_info_node *node = s->private;
1188 struct tegra_dc *dc = node->info_ent->data;
1189
1190#define DUMP_REG(name) \
03a60569 1191 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
d8f4a9ed
TR		 1192 tegra_dc_readl(dc, name))
1193
1194 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1195 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1196 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1197 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1198 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1199 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1200 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1201 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1202 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1203 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1204 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1205 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1206 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1207 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1208 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1209 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1210 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1211 DUMP_REG(DC_CMD_INT_STATUS);
1212 DUMP_REG(DC_CMD_INT_MASK);
1213 DUMP_REG(DC_CMD_INT_ENABLE);
1214 DUMP_REG(DC_CMD_INT_TYPE);
1215 DUMP_REG(DC_CMD_INT_POLARITY);
1216 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1217 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1218 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1219 DUMP_REG(DC_CMD_STATE_ACCESS);
1220 DUMP_REG(DC_CMD_STATE_CONTROL);
1221 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1222 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1223 DUMP_REG(DC_COM_CRC_CONTROL);
1224 DUMP_REG(DC_COM_CRC_CHECKSUM);
1225 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1226 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1227 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1228 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1229 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1230 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1231 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1232 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1233 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1234 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1235 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1236 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1237 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1238 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1239 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1240 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1241 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1242 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1243 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1244 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1245 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1246 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1247 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1248 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1249 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1250 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1251 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1252 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1253 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1254 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1255 DUMP_REG(DC_COM_SPI_CONTROL);
1256 DUMP_REG(DC_COM_SPI_START_BYTE);
1257 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1258 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1259 DUMP_REG(DC_COM_HSPI_CS_DC);
1260 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1261 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1262 DUMP_REG(DC_COM_GPIO_CTRL);
1263 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1264 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1265 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1266 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1267 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1268 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1269 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1270 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1271 DUMP_REG(DC_DISP_REF_TO_SYNC);
1272 DUMP_REG(DC_DISP_SYNC_WIDTH);
1273 DUMP_REG(DC_DISP_BACK_PORCH);
1274 DUMP_REG(DC_DISP_ACTIVE);
1275 DUMP_REG(DC_DISP_FRONT_PORCH);
1276 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1277 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1278 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1279 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1280 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1281 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1282 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1283 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1284 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1285 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1286 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1287 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1288 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1289 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1290 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1291 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1292 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1293 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1294 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1295 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1296 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1297 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1298 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1299 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1300 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1301 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1302 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1303 DUMP_REG(DC_DISP_M0_CONTROL);
1304 DUMP_REG(DC_DISP_M1_CONTROL);
1305 DUMP_REG(DC_DISP_DI_CONTROL);
1306 DUMP_REG(DC_DISP_PP_CONTROL);
1307 DUMP_REG(DC_DISP_PP_SELECT_A);
1308 DUMP_REG(DC_DISP_PP_SELECT_B);
1309 DUMP_REG(DC_DISP_PP_SELECT_C);
1310 DUMP_REG(DC_DISP_PP_SELECT_D);
1311 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1312 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1313 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1314 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1315 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1316 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1317 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1318 DUMP_REG(DC_DISP_BORDER_COLOR);
1319 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1320 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1321 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1322 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1323 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1324 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1325 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1326 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1327 DUMP_REG(DC_DISP_CURSOR_POSITION);
1328 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1329 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1330 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1331 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1332 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1333 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1334 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1335 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1336 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1337 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1338 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1339 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1340 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1341 DUMP_REG(DC_DISP_SD_CONTROL);
1342 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1343 DUMP_REG(DC_DISP_SD_LUT(0));
1344 DUMP_REG(DC_DISP_SD_LUT(1));
1345 DUMP_REG(DC_DISP_SD_LUT(2));
1346 DUMP_REG(DC_DISP_SD_LUT(3));
1347 DUMP_REG(DC_DISP_SD_LUT(4));
1348 DUMP_REG(DC_DISP_SD_LUT(5));
1349 DUMP_REG(DC_DISP_SD_LUT(6));
1350 DUMP_REG(DC_DISP_SD_LUT(7));
1351 DUMP_REG(DC_DISP_SD_LUT(8));
1352 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1353 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1354 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1355 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1356 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1357 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1358 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1359 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1360 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1361 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1362 DUMP_REG(DC_DISP_SD_BL_TF(0));
1363 DUMP_REG(DC_DISP_SD_BL_TF(1));
1364 DUMP_REG(DC_DISP_SD_BL_TF(2));
1365 DUMP_REG(DC_DISP_SD_BL_TF(3));
1366 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1367 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1368 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
e687651b
TR		 1369 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1370 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
d8f4a9ed
TR		 1371 DUMP_REG(DC_WIN_WIN_OPTIONS);
1372 DUMP_REG(DC_WIN_BYTE_SWAP);
1373 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1374 DUMP_REG(DC_WIN_COLOR_DEPTH);
1375 DUMP_REG(DC_WIN_POSITION);
1376 DUMP_REG(DC_WIN_SIZE);
1377 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1378 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1379 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1380 DUMP_REG(DC_WIN_DDA_INC);
1381 DUMP_REG(DC_WIN_LINE_STRIDE);
1382 DUMP_REG(DC_WIN_BUF_STRIDE);
1383 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1384 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1385 DUMP_REG(DC_WIN_DV_CONTROL);
1386 DUMP_REG(DC_WIN_BLEND_NOKEY);
1387 DUMP_REG(DC_WIN_BLEND_1WIN);
1388 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1389 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1390 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1391 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1392 DUMP_REG(DC_WINBUF_START_ADDR);
1393 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1394 DUMP_REG(DC_WINBUF_START_ADDR_U);
1395 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1396 DUMP_REG(DC_WINBUF_START_ADDR_V);
1397 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1398 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1399 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1400 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1401 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1402 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1403 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1404 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1405 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1406
1407#undef DUMP_REG
1408
1409 return 0;
1410}
1411
1412static struct drm_info_list debugfs_files[] = {
1413 { "regs", tegra_dc_show_regs, 0, NULL },
1414};
1415
1416static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1417{
1418 unsigned int i;
1419 char *name;
1420 int err;
1421
1422 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1423 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1424 kfree(name);
1425
1426 if (!dc->debugfs)
1427 return -ENOMEM;
1428
1429 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1430 GFP_KERNEL);
1431 if (!dc->debugfs_files) {
1432 err = -ENOMEM;
1433 goto remove;
1434 }
1435
1436 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1437 dc->debugfs_files[i].data = dc;
1438
1439 err = drm_debugfs_create_files(dc->debugfs_files,
1440 ARRAY_SIZE(debugfs_files),
1441 dc->debugfs, minor);
1442 if (err < 0)
1443 goto free;
1444
1445 dc->minor = minor;
1446
1447 return 0;
1448
1449free:
1450 kfree(dc->debugfs_files);
1451 dc->debugfs_files = NULL;
1452remove:
1453 debugfs_remove(dc->debugfs);
1454 dc->debugfs = NULL;
1455
1456 return err;
1457}
1458
1459static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1460{
1461 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1462 dc->minor);
1463 dc->minor = NULL;
1464
1465 kfree(dc->debugfs_files);
1466 dc->debugfs_files = NULL;
1467
1468 debugfs_remove(dc->debugfs);
1469 dc->debugfs = NULL;
1470
1471 return 0;
1472}
1473
53fa7f72 1474static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1475{
9910f5c4 1476 struct drm_device *drm = dev_get_drvdata(client->parent);
776dc384 1477 struct tegra_dc *dc = host1x_client_to_dc(client);
d1f3e1e0 1478 struct tegra_drm *tegra = drm->dev_private;
c7679306
TR		 1479 struct drm_plane *primary = NULL;
1480 struct drm_plane *cursor = NULL;
d8f4a9ed
TR		 1481 int err;
1482
df06b759
TR		 1483 if (tegra->domain) {
1484 err = iommu_attach_device(tegra->domain, dc->dev);
1485 if (err < 0) {
1486 dev_err(dc->dev, "failed to attach to domain: %d\n",
1487 err);
1488 return err;
1489 }
1490
1491 dc->domain = tegra->domain;
1492 }
1493
c7679306
TR		 1494 primary = tegra_dc_primary_plane_create(drm, dc);
1495 if (IS_ERR(primary)) {
1496 err = PTR_ERR(primary);
1497 goto cleanup;
1498 }
1499
1500 if (dc->soc->supports_cursor) {
1501 cursor = tegra_dc_cursor_plane_create(drm, dc);
1502 if (IS_ERR(cursor)) {
1503 err = PTR_ERR(cursor);
1504 goto cleanup;
1505 }
1506 }
1507
1508 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1509 &tegra_crtc_funcs);
1510 if (err < 0)
1511 goto cleanup;
1512
d8f4a9ed
TR		 1513 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1514 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1515
d1f3e1e0
TR		 1516 /*
1517 * Keep track of the minimum pitch alignment across all display
1518 * controllers.
1519 */
1520 if (dc->soc->pitch_align > tegra->pitch_align)
1521 tegra->pitch_align = dc->soc->pitch_align;
1522
9910f5c4 1523 err = tegra_dc_rgb_init(drm, dc);
d8f4a9ed
TR		 1524 if (err < 0 && err != -ENODEV) {
1525 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
c7679306 1526 goto cleanup;
d8f4a9ed
TR		 1527 }
1528
9910f5c4 1529 err = tegra_dc_add_planes(drm, dc);
f34bc787 1530 if (err < 0)
c7679306 1531 goto cleanup;
f34bc787 1532
d8f4a9ed 1533 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1534 err = tegra_dc_debugfs_init(dc, drm->primary);
d8f4a9ed
TR		 1535 if (err < 0)
1536 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1537 }
1538
6e5ff998 1539 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1540 dev_name(dc->dev), dc);
1541 if (err < 0) {
1542 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1543 err);
c7679306 1544 goto cleanup;
d8f4a9ed
TR		 1545 }
1546
1547 return 0;
c7679306
TR		 1548
1549cleanup:
1550 if (cursor)
1551 drm_plane_cleanup(cursor);
1552
1553 if (primary)
1554 drm_plane_cleanup(primary);
1555
1556 if (tegra->domain) {
1557 iommu_detach_device(tegra->domain, dc->dev);
1558 dc->domain = NULL;
1559 }
1560
1561 return err;
d8f4a9ed
TR		 1562}
1563
53fa7f72 1564static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1565{
776dc384 1566 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1567 int err;
1568
1569 devm_free_irq(dc->dev, dc->irq, dc);
1570
1571 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1572 err = tegra_dc_debugfs_exit(dc);
1573 if (err < 0)
1574 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1575 }
1576
1577 err = tegra_dc_rgb_exit(dc);
1578 if (err) {
1579 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1580 return err;
1581 }
1582
df06b759
TR		 1583 if (dc->domain) {
1584 iommu_detach_device(dc->domain, dc->dev);
1585 dc->domain = NULL;
1586 }
1587
d8f4a9ed
TR		 1588 return 0;
1589}
1590
1591static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1592 .init = tegra_dc_init,
1593 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1594};
1595
8620fc62 1596static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
42d0659b 1597 .supports_border_color = true,
8620fc62 1598 .supports_interlacing = false,
e687651b 1599 .supports_cursor = false,
c134f019 1600 .supports_block_linear = false,
d1f3e1e0 1601 .pitch_align = 8,
9c012700 1602 .has_powergate = false,
8620fc62
TR		 1603};
1604
1605static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
42d0659b 1606 .supports_border_color = true,
8620fc62 1607 .supports_interlacing = false,
e687651b 1608 .supports_cursor = false,
c134f019 1609 .supports_block_linear = false,
d1f3e1e0 1610 .pitch_align = 8,
9c012700 1611 .has_powergate = false,
d1f3e1e0
TR		 1612};
1613
1614static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
42d0659b 1615 .supports_border_color = true,
d1f3e1e0
TR		 1616 .supports_interlacing = false,
1617 .supports_cursor = false,
1618 .supports_block_linear = false,
1619 .pitch_align = 64,
9c012700 1620 .has_powergate = true,
8620fc62
TR		 1621};
1622
1623static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
42d0659b 1624 .supports_border_color = false,
8620fc62 1625 .supports_interlacing = true,
e687651b 1626 .supports_cursor = true,
c134f019 1627 .supports_block_linear = true,
d1f3e1e0 1628 .pitch_align = 64,
9c012700 1629 .has_powergate = true,
8620fc62
TR		 1630};
1631
1632static const struct of_device_id tegra_dc_of_match[] = {
1633 {
1634 .compatible = "nvidia,tegra124-dc",
1635 .data = &tegra124_dc_soc_info,
9c012700
TR		 1636 }, {
1637 .compatible = "nvidia,tegra114-dc",
1638 .data = &tegra114_dc_soc_info,
8620fc62
TR		 1639 }, {
1640 .compatible = "nvidia,tegra30-dc",
1641 .data = &tegra30_dc_soc_info,
1642 }, {
1643 .compatible = "nvidia,tegra20-dc",
1644 .data = &tegra20_dc_soc_info,
1645 }, {
1646 /* sentinel */
1647 }
1648};
ef70728c 1649MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
8620fc62 1650
13411ddd
TR		 1651static int tegra_dc_parse_dt(struct tegra_dc *dc)
1652{
1653 struct device_node *np;
1654 u32 value = 0;
1655 int err;
1656
1657 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1658 if (err < 0) {
1659 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1660
1661 /*
1662 * If the nvidia,head property isn't present, try to find the
1663 * correct head number by looking up the position of this
1664 * display controller's node within the device tree. Assuming
1665 * that the nodes are ordered properly in the DTS file and
1666 * that the translation into a flattened device tree blob
1667 * preserves that ordering this will actually yield the right
1668 * head number.
1669 *
1670 * If those assumptions don't hold, this will still work for
1671 * cases where only a single display controller is used.
1672 */
1673 for_each_matching_node(np, tegra_dc_of_match) {
1674 if (np == dc->dev->of_node)
1675 break;
1676
1677 value++;
1678 }
1679 }
1680
1681 dc->pipe = value;
1682
1683 return 0;
1684}
1685
d8f4a9ed
TR		 1686static int tegra_dc_probe(struct platform_device *pdev)
1687{
8620fc62 1688 const struct of_device_id *id;
d8f4a9ed
TR		 1689 struct resource *regs;
1690 struct tegra_dc *dc;
1691 int err;
1692
1693 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1694 if (!dc)
1695 return -ENOMEM;
1696
8620fc62
TR		 1697 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1698 if (!id)
1699 return -ENODEV;
1700
6e5ff998 1701 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1702 INIT_LIST_HEAD(&dc->list);
1703 dc->dev = &pdev->dev;
8620fc62 1704 dc->soc = id->data;
d8f4a9ed 1705
13411ddd
TR		 1706 err = tegra_dc_parse_dt(dc);
1707 if (err < 0)
1708 return err;
1709
d8f4a9ed
TR		 1710 dc->clk = devm_clk_get(&pdev->dev, NULL);
1711 if (IS_ERR(dc->clk)) {
1712 dev_err(&pdev->dev, "failed to get clock\n");
1713 return PTR_ERR(dc->clk);
1714 }
1715
ca48080a
SW		 1716 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1717 if (IS_ERR(dc->rst)) {
1718 dev_err(&pdev->dev, "failed to get reset\n");
1719 return PTR_ERR(dc->rst);
1720 }
1721
9c012700
TR		 1722 if (dc->soc->has_powergate) {
1723 if (dc->pipe == 0)
1724 dc->powergate = TEGRA_POWERGATE_DIS;
1725 else
1726 dc->powergate = TEGRA_POWERGATE_DISB;
1727
1728 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1729 dc->rst);
1730 if (err < 0) {
1731 dev_err(&pdev->dev, "failed to power partition: %d\n",
1732 err);
1733 return err;
1734 }
1735 } else {
1736 err = clk_prepare_enable(dc->clk);
1737 if (err < 0) {
1738 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1739 err);
1740 return err;
1741 }
1742
1743 err = reset_control_deassert(dc->rst);
1744 if (err < 0) {
1745 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1746 err);
1747 return err;
1748 }
1749 }
d8f4a9ed
TR		 1750
1751 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1752 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1753 if (IS_ERR(dc->regs))
1754 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1755
1756 dc->irq = platform_get_irq(pdev, 0);
1757 if (dc->irq < 0) {
1758 dev_err(&pdev->dev, "failed to get IRQ\n");
1759 return -ENXIO;
1760 }
1761
776dc384
TR		 1762 INIT_LIST_HEAD(&dc->client.list);
1763 dc->client.ops = &dc_client_ops;
1764 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1765
1766 err = tegra_dc_rgb_probe(dc);
1767 if (err < 0 && err != -ENODEV) {
1768 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1769 return err;
1770 }
1771
776dc384 1772 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1773 if (err < 0) {
1774 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1775 err);
1776 return err;
1777 }
1778
1779 platform_set_drvdata(pdev, dc);
1780
1781 return 0;
1782}
1783
1784static int tegra_dc_remove(struct platform_device *pdev)
1785{
d8f4a9ed
TR		 1786 struct tegra_dc *dc = platform_get_drvdata(pdev);
1787 int err;
1788
776dc384 1789 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1790 if (err < 0) {
1791 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1792 err);
1793 return err;
1794 }
1795
59d29c0e
TR		 1796 err = tegra_dc_rgb_remove(dc);
1797 if (err < 0) {
1798 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1799 return err;
1800 }
1801
5482d75a 1802 reset_control_assert(dc->rst);
9c012700
TR		 1803
1804 if (dc->soc->has_powergate)
1805 tegra_powergate_power_off(dc->powergate);
1806
d8f4a9ed
TR		 1807 clk_disable_unprepare(dc->clk);
1808
1809 return 0;
1810}
1811
d8f4a9ed
TR		 1812struct platform_driver tegra_dc_driver = {
1813 .driver = {
1814 .name = "tegra-dc",
1815 .owner = THIS_MODULE,
1816 .of_match_table = tegra_dc_of_match,
1817 },
1818 .probe = tegra_dc_probe,
1819 .remove = tegra_dc_remove,
1820};
Linux kernel - Deliverables
This page took 0.235164 seconds and 5 git commands to generate.