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drm: Add NVIDIA Tegra20 support
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15
16#include <mach/clk.h>
17
18#include "drm.h"
19#include "dc.h"
20
21struct tegra_dc_window {
22 fixed20_12 x;
23 fixed20_12 y;
24 fixed20_12 w;
25 fixed20_12 h;
26 unsigned int outx;
27 unsigned int outy;
28 unsigned int outw;
29 unsigned int outh;
30 unsigned int stride;
31 unsigned int fmt;
32};
33
34static const struct drm_crtc_funcs tegra_crtc_funcs = {
35 .set_config = drm_crtc_helper_set_config,
36 .destroy = drm_crtc_cleanup,
37};
38
39static void tegra_crtc_dpms(struct drm_crtc *crtc, int mode)
40{
41}
42
43static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
44 const struct drm_display_mode *mode,
45 struct drm_display_mode *adjusted)
46{
47 return true;
48}
49
50static inline u32 compute_dda_inc(fixed20_12 inf, unsigned int out, bool v,
51 unsigned int bpp)
52{
53 fixed20_12 outf = dfixed_init(out);
54 u32 dda_inc;
55 int max;
56
57 if (v)
58 max = 15;
59 else {
60 switch (bpp) {
61 case 2:
62 max = 8;
63 break;
64
65 default:
66 WARN_ON_ONCE(1);
67 /* fallthrough */
68 case 4:
69 max = 4;
70 break;
71 }
72 }
73
74 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
75 inf.full -= dfixed_const(1);
76
77 dda_inc = dfixed_div(inf, outf);
78 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
79
80 return dda_inc;
81}
82
83static inline u32 compute_initial_dda(fixed20_12 in)
84{
85 return dfixed_frac(in);
86}
87
88static int tegra_dc_set_timings(struct tegra_dc *dc,
89 struct drm_display_mode *mode)
90{
91 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
92 unsigned int h_ref_to_sync = 0;
93 unsigned int v_ref_to_sync = 0;
94 unsigned long value;
95
96 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
97
98 value = (v_ref_to_sync << 16) | h_ref_to_sync;
99 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
100
101 value = ((mode->vsync_end - mode->vsync_start) << 16) |
102 ((mode->hsync_end - mode->hsync_start) << 0);
103 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
104
105 value = ((mode->vsync_start - mode->vdisplay) << 16) |
106 ((mode->hsync_start - mode->hdisplay) << 0);
107 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
108
109 value = ((mode->vtotal - mode->vsync_end) << 16) |
110 ((mode->htotal - mode->hsync_end) << 0);
111 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
112
113 value = (mode->vdisplay << 16) | mode->hdisplay;
114 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
115
116 return 0;
117}
118
119static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
120 struct drm_display_mode *mode,
121 unsigned long *div)
122{
123 unsigned long pclk = mode->clock * 1000, rate;
124 struct tegra_dc *dc = to_tegra_dc(crtc);
125 struct tegra_output *output = NULL;
126 struct drm_encoder *encoder;
127 long err;
128
129 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
130 if (encoder->crtc == crtc) {
131 output = encoder_to_output(encoder);
132 break;
133 }
134
135 if (!output)
136 return -ENODEV;
137
138 /*
139 * This assumes that the display controller will divide its parent
140 * clock by 2 to generate the pixel clock.
141 */
142 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
143 if (err < 0) {
144 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
145 return err;
146 }
147
148 rate = clk_get_rate(dc->clk);
149 *div = (rate * 2 / pclk) - 2;
150
151 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
152
153 return 0;
154}
155
156static int tegra_crtc_mode_set(struct drm_crtc *crtc,
157 struct drm_display_mode *mode,
158 struct drm_display_mode *adjusted,
159 int x, int y, struct drm_framebuffer *old_fb)
160{
161 struct tegra_framebuffer *fb = to_tegra_fb(crtc->fb);
162 struct tegra_dc *dc = to_tegra_dc(crtc);
163 unsigned int h_dda, v_dda, bpp;
164 struct tegra_dc_window win;
165 unsigned long div, value;
166 int err;
167
168 err = tegra_crtc_setup_clk(crtc, mode, &div);
169 if (err) {
170 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
171 return err;
172 }
173
174 /* program display mode */
175 tegra_dc_set_timings(dc, mode);
176
177 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
178 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
179
180 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
181 value &= ~LVS_OUTPUT_POLARITY_LOW;
182 value &= ~LHS_OUTPUT_POLARITY_LOW;
183 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
184
185 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
186 DISP_ORDER_RED_BLUE;
187 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
188
189 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
190
191 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
192 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
193
194 /* setup window parameters */
195 memset(&win, 0, sizeof(win));
196 win.x.full = dfixed_const(0);
197 win.y.full = dfixed_const(0);
198 win.w.full = dfixed_const(mode->hdisplay);
199 win.h.full = dfixed_const(mode->vdisplay);
200 win.outx = 0;
201 win.outy = 0;
202 win.outw = mode->hdisplay;
203 win.outh = mode->vdisplay;
204
205 switch (crtc->fb->pixel_format) {
206 case DRM_FORMAT_XRGB8888:
207 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8;
208 break;
209
210 case DRM_FORMAT_RGB565:
211 win.fmt = WIN_COLOR_DEPTH_B5G6R5;
212 break;
213
214 default:
215 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8;
216 WARN_ON(1);
217 break;
218 }
219
220 bpp = crtc->fb->bits_per_pixel / 8;
221 win.stride = win.outw * bpp;
222
223 /* program window registers */
224 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
225 value |= WINDOW_A_SELECT;
226 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
227
228 tegra_dc_writel(dc, win.fmt, DC_WIN_COLOR_DEPTH);
229 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
230
231 value = V_POSITION(win.outy) | H_POSITION(win.outx);
232 tegra_dc_writel(dc, value, DC_WIN_POSITION);
233
234 value = V_SIZE(win.outh) | H_SIZE(win.outw);
235 tegra_dc_writel(dc, value, DC_WIN_SIZE);
236
237 value = V_PRESCALED_SIZE(dfixed_trunc(win.h)) |
238 H_PRESCALED_SIZE(dfixed_trunc(win.w) * bpp);
239 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
240
241 h_dda = compute_dda_inc(win.w, win.outw, false, bpp);
242 v_dda = compute_dda_inc(win.h, win.outh, true, bpp);
243
244 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
245 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
246
247 h_dda = compute_initial_dda(win.x);
248 v_dda = compute_initial_dda(win.y);
249
250 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
251 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
252
253 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
254 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
255
256 tegra_dc_writel(dc, fb->obj->paddr, DC_WINBUF_START_ADDR);
257 tegra_dc_writel(dc, win.stride, DC_WIN_LINE_STRIDE);
258 tegra_dc_writel(dc, dfixed_trunc(win.x) * bpp,
259 DC_WINBUF_ADDR_H_OFFSET);
260 tegra_dc_writel(dc, dfixed_trunc(win.y), DC_WINBUF_ADDR_V_OFFSET);
261
262 value = WIN_ENABLE;
263
264 if (bpp < 24)
265 value |= COLOR_EXPAND;
266
267 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
268
269 tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_NOKEY);
270 tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_1WIN);
271
272 return 0;
273}
274
275static void tegra_crtc_prepare(struct drm_crtc *crtc)
276{
277 struct tegra_dc *dc = to_tegra_dc(crtc);
278 unsigned int syncpt;
279 unsigned long value;
280
281 /* hardware initialization */
282 tegra_periph_reset_deassert(dc->clk);
283 usleep_range(10000, 20000);
284
285 if (dc->pipe)
286 syncpt = SYNCPT_VBLANK1;
287 else
288 syncpt = SYNCPT_VBLANK0;
289
290 /* initialize display controller */
291 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
292 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
293
294 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
295 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
296
297 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
298 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
299 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
300
301 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
302 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
303 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
304
305 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
306 value |= DISP_CTRL_MODE_C_DISPLAY;
307 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
308
309 /* initialize timer */
310 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
311 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
312 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
313
314 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
315 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
316 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
317
318 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
319 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
320
321 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
322 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
323}
324
325static void tegra_crtc_commit(struct drm_crtc *crtc)
326{
327 struct tegra_dc *dc = to_tegra_dc(crtc);
328 unsigned long update_mask;
329 unsigned long value;
330
331 update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
332
333 tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
334
335 value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
336 value |= FRAME_END_INT;
337 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
338
339 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
340 value |= FRAME_END_INT;
341 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
342
343 tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
344}
345
346static void tegra_crtc_load_lut(struct drm_crtc *crtc)
347{
348}
349
350static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
351 .dpms = tegra_crtc_dpms,
352 .mode_fixup = tegra_crtc_mode_fixup,
353 .mode_set = tegra_crtc_mode_set,
354 .prepare = tegra_crtc_prepare,
355 .commit = tegra_crtc_commit,
356 .load_lut = tegra_crtc_load_lut,
357};
358
359static irqreturn_t tegra_drm_irq(int irq, void *data)
360{
361 struct tegra_dc *dc = data;
362 unsigned long status;
363
364 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
365 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
366
367 if (status & FRAME_END_INT) {
368 /*
369 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
370 */
371 }
372
373 if (status & VBLANK_INT) {
374 /*
375 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
376 */
377 drm_handle_vblank(dc->base.dev, dc->pipe);
378 }
379
380 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
381 /*
382 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
383 */
384 }
385
386 return IRQ_HANDLED;
387}
388
389static int tegra_dc_show_regs(struct seq_file *s, void *data)
390{
391 struct drm_info_node *node = s->private;
392 struct tegra_dc *dc = node->info_ent->data;
393
394#define DUMP_REG(name) \
395 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
396 tegra_dc_readl(dc, name))
397
398 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
399 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
400 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
401 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
402 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
403 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
404 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
405 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
406 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
407 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
408 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
409 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
410 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
411 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
412 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
413 DUMP_REG(DC_CMD_SIGNAL_RAISE);
414 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
415 DUMP_REG(DC_CMD_INT_STATUS);
416 DUMP_REG(DC_CMD_INT_MASK);
417 DUMP_REG(DC_CMD_INT_ENABLE);
418 DUMP_REG(DC_CMD_INT_TYPE);
419 DUMP_REG(DC_CMD_INT_POLARITY);
420 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
421 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
422 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
423 DUMP_REG(DC_CMD_STATE_ACCESS);
424 DUMP_REG(DC_CMD_STATE_CONTROL);
425 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
426 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
427 DUMP_REG(DC_COM_CRC_CONTROL);
428 DUMP_REG(DC_COM_CRC_CHECKSUM);
429 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
430 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
431 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
432 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
433 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
434 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
435 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
436 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
437 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
438 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
439 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
440 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
441 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
442 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
443 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
444 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
445 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
446 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
447 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
448 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
449 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
450 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
451 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
452 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
453 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
454 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
455 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
456 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
457 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
458 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
459 DUMP_REG(DC_COM_SPI_CONTROL);
460 DUMP_REG(DC_COM_SPI_START_BYTE);
461 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
462 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
463 DUMP_REG(DC_COM_HSPI_CS_DC);
464 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
465 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
466 DUMP_REG(DC_COM_GPIO_CTRL);
467 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
468 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
469 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
470 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
471 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
472 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
473 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
474 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
475 DUMP_REG(DC_DISP_REF_TO_SYNC);
476 DUMP_REG(DC_DISP_SYNC_WIDTH);
477 DUMP_REG(DC_DISP_BACK_PORCH);
478 DUMP_REG(DC_DISP_ACTIVE);
479 DUMP_REG(DC_DISP_FRONT_PORCH);
480 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
481 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
482 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
483 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
484 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
485 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
486 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
487 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
488 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
489 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
490 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
491 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
492 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
493 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
494 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
495 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
496 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
497 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
498 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
499 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
500 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
501 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
502 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
503 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
504 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
505 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
506 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
507 DUMP_REG(DC_DISP_M0_CONTROL);
508 DUMP_REG(DC_DISP_M1_CONTROL);
509 DUMP_REG(DC_DISP_DI_CONTROL);
510 DUMP_REG(DC_DISP_PP_CONTROL);
511 DUMP_REG(DC_DISP_PP_SELECT_A);
512 DUMP_REG(DC_DISP_PP_SELECT_B);
513 DUMP_REG(DC_DISP_PP_SELECT_C);
514 DUMP_REG(DC_DISP_PP_SELECT_D);
515 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
516 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
517 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
518 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
519 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
520 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
521 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
522 DUMP_REG(DC_DISP_BORDER_COLOR);
523 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
524 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
525 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
526 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
527 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
528 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
529 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
530 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
531 DUMP_REG(DC_DISP_CURSOR_POSITION);
532 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
533 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
534 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
535 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
536 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
537 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
538 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
539 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
540 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
541 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
542 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
543 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
544 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
545 DUMP_REG(DC_DISP_SD_CONTROL);
546 DUMP_REG(DC_DISP_SD_CSC_COEFF);
547 DUMP_REG(DC_DISP_SD_LUT(0));
548 DUMP_REG(DC_DISP_SD_LUT(1));
549 DUMP_REG(DC_DISP_SD_LUT(2));
550 DUMP_REG(DC_DISP_SD_LUT(3));
551 DUMP_REG(DC_DISP_SD_LUT(4));
552 DUMP_REG(DC_DISP_SD_LUT(5));
553 DUMP_REG(DC_DISP_SD_LUT(6));
554 DUMP_REG(DC_DISP_SD_LUT(7));
555 DUMP_REG(DC_DISP_SD_LUT(8));
556 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
557 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
558 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
559 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
560 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
561 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
562 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
563 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
564 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
565 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
566 DUMP_REG(DC_DISP_SD_BL_TF(0));
567 DUMP_REG(DC_DISP_SD_BL_TF(1));
568 DUMP_REG(DC_DISP_SD_BL_TF(2));
569 DUMP_REG(DC_DISP_SD_BL_TF(3));
570 DUMP_REG(DC_DISP_SD_BL_CONTROL);
571 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
572 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
573 DUMP_REG(DC_WIN_WIN_OPTIONS);
574 DUMP_REG(DC_WIN_BYTE_SWAP);
575 DUMP_REG(DC_WIN_BUFFER_CONTROL);
576 DUMP_REG(DC_WIN_COLOR_DEPTH);
577 DUMP_REG(DC_WIN_POSITION);
578 DUMP_REG(DC_WIN_SIZE);
579 DUMP_REG(DC_WIN_PRESCALED_SIZE);
580 DUMP_REG(DC_WIN_H_INITIAL_DDA);
581 DUMP_REG(DC_WIN_V_INITIAL_DDA);
582 DUMP_REG(DC_WIN_DDA_INC);
583 DUMP_REG(DC_WIN_LINE_STRIDE);
584 DUMP_REG(DC_WIN_BUF_STRIDE);
585 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
586 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
587 DUMP_REG(DC_WIN_DV_CONTROL);
588 DUMP_REG(DC_WIN_BLEND_NOKEY);
589 DUMP_REG(DC_WIN_BLEND_1WIN);
590 DUMP_REG(DC_WIN_BLEND_2WIN_X);
591 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
592 DUMP_REG(DC_WIN_BLEND32WIN_XY);
593 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
594 DUMP_REG(DC_WINBUF_START_ADDR);
595 DUMP_REG(DC_WINBUF_START_ADDR_NS);
596 DUMP_REG(DC_WINBUF_START_ADDR_U);
597 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
598 DUMP_REG(DC_WINBUF_START_ADDR_V);
599 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
600 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
601 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
602 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
603 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
604 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
605 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
606 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
607 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
608
609#undef DUMP_REG
610
611 return 0;
612}
613
614static struct drm_info_list debugfs_files[] = {
615 { "regs", tegra_dc_show_regs, 0, NULL },
616};
617
618static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
619{
620 unsigned int i;
621 char *name;
622 int err;
623
624 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
625 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
626 kfree(name);
627
628 if (!dc->debugfs)
629 return -ENOMEM;
630
631 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
632 GFP_KERNEL);
633 if (!dc->debugfs_files) {
634 err = -ENOMEM;
635 goto remove;
636 }
637
638 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
639 dc->debugfs_files[i].data = dc;
640
641 err = drm_debugfs_create_files(dc->debugfs_files,
642 ARRAY_SIZE(debugfs_files),
643 dc->debugfs, minor);
644 if (err < 0)
645 goto free;
646
647 dc->minor = minor;
648
649 return 0;
650
651free:
652 kfree(dc->debugfs_files);
653 dc->debugfs_files = NULL;
654remove:
655 debugfs_remove(dc->debugfs);
656 dc->debugfs = NULL;
657
658 return err;
659}
660
661static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
662{
663 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
664 dc->minor);
665 dc->minor = NULL;
666
667 kfree(dc->debugfs_files);
668 dc->debugfs_files = NULL;
669
670 debugfs_remove(dc->debugfs);
671 dc->debugfs = NULL;
672
673 return 0;
674}
675
676static int tegra_dc_drm_init(struct host1x_client *client,
677 struct drm_device *drm)
678{
679 struct tegra_dc *dc = host1x_client_to_dc(client);
680 int err;
681
682 dc->pipe = drm->mode_config.num_crtc;
683
684 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
685 drm_mode_crtc_set_gamma_size(&dc->base, 256);
686 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
687
688 err = tegra_dc_rgb_init(drm, dc);
689 if (err < 0 && err != -ENODEV) {
690 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
691 return err;
692 }
693
694 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
695 err = tegra_dc_debugfs_init(dc, drm->primary);
696 if (err < 0)
697 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
698 }
699
700 err = devm_request_irq(dc->dev, dc->irq, tegra_drm_irq, 0,
701 dev_name(dc->dev), dc);
702 if (err < 0) {
703 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
704 err);
705 return err;
706 }
707
708 return 0;
709}
710
711static int tegra_dc_drm_exit(struct host1x_client *client)
712{
713 struct tegra_dc *dc = host1x_client_to_dc(client);
714 int err;
715
716 devm_free_irq(dc->dev, dc->irq, dc);
717
718 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
719 err = tegra_dc_debugfs_exit(dc);
720 if (err < 0)
721 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
722 }
723
724 err = tegra_dc_rgb_exit(dc);
725 if (err) {
726 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
727 return err;
728 }
729
730 return 0;
731}
732
733static const struct host1x_client_ops dc_client_ops = {
734 .drm_init = tegra_dc_drm_init,
735 .drm_exit = tegra_dc_drm_exit,
736};
737
738static int tegra_dc_probe(struct platform_device *pdev)
739{
740 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
741 struct resource *regs;
742 struct tegra_dc *dc;
743 int err;
744
745 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
746 if (!dc)
747 return -ENOMEM;
748
749 INIT_LIST_HEAD(&dc->list);
750 dc->dev = &pdev->dev;
751
752 dc->clk = devm_clk_get(&pdev->dev, NULL);
753 if (IS_ERR(dc->clk)) {
754 dev_err(&pdev->dev, "failed to get clock\n");
755 return PTR_ERR(dc->clk);
756 }
757
758 err = clk_prepare_enable(dc->clk);
759 if (err < 0)
760 return err;
761
762 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
763 if (!regs) {
764 dev_err(&pdev->dev, "failed to get registers\n");
765 return -ENXIO;
766 }
767
768 dc->regs = devm_request_and_ioremap(&pdev->dev, regs);
769 if (!dc->regs) {
770 dev_err(&pdev->dev, "failed to remap registers\n");
771 return -ENXIO;
772 }
773
774 dc->irq = platform_get_irq(pdev, 0);
775 if (dc->irq < 0) {
776 dev_err(&pdev->dev, "failed to get IRQ\n");
777 return -ENXIO;
778 }
779
780 INIT_LIST_HEAD(&dc->client.list);
781 dc->client.ops = &dc_client_ops;
782 dc->client.dev = &pdev->dev;
783
784 err = tegra_dc_rgb_probe(dc);
785 if (err < 0 && err != -ENODEV) {
786 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
787 return err;
788 }
789
790 err = host1x_register_client(host1x, &dc->client);
791 if (err < 0) {
792 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
793 err);
794 return err;
795 }
796
797 platform_set_drvdata(pdev, dc);
798
799 return 0;
800}
801
802static int tegra_dc_remove(struct platform_device *pdev)
803{
804 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
805 struct tegra_dc *dc = platform_get_drvdata(pdev);
806 int err;
807
808 err = host1x_unregister_client(host1x, &dc->client);
809 if (err < 0) {
810 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
811 err);
812 return err;
813 }
814
815 clk_disable_unprepare(dc->clk);
816
817 return 0;
818}
819
820static struct of_device_id tegra_dc_of_match[] = {
821 { .compatible = "nvidia,tegra20-dc", },
822 { },
823};
824
825struct platform_driver tegra_dc_driver = {
826 .driver = {
827 .name = "tegra-dc",
828 .owner = THIS_MODULE,
829 .of_match_table = tegra_dc_of_match,
830 },
831 .probe = tegra_dc_probe,
832 .remove = tegra_dc_remove,
833};
Linux kernel - Deliverables
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