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drm/tegra: Move driver to DRM tree
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
61fd290d 11#include <linux/clk/tegra.h>
9eb9b220 12#include <linux/debugfs.h>
d8f4a9ed 13
de2ba664
AM		 14#include "dc.h"
15#include "drm.h"
16#include "gem.h"
d8f4a9ed 17
f34bc787
TR		 18struct tegra_plane {
19 struct drm_plane base;
20 unsigned int index;
d8f4a9ed
TR		 21};
22
f34bc787
TR		 23static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
24{
25 return container_of(plane, struct tegra_plane, base);
26}
27
28static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
29 struct drm_framebuffer *fb, int crtc_x,
30 int crtc_y, unsigned int crtc_w,
31 unsigned int crtc_h, uint32_t src_x,
32 uint32_t src_y, uint32_t src_w, uint32_t src_h)
33{
34 struct tegra_plane *p = to_tegra_plane(plane);
35 struct tegra_dc *dc = to_tegra_dc(crtc);
36 struct tegra_dc_window window;
37 unsigned int i;
38
39 memset(&window, 0, sizeof(window));
40 window.src.x = src_x >> 16;
41 window.src.y = src_y >> 16;
42 window.src.w = src_w >> 16;
43 window.src.h = src_h >> 16;
44 window.dst.x = crtc_x;
45 window.dst.y = crtc_y;
46 window.dst.w = crtc_w;
47 window.dst.h = crtc_h;
48 window.format = tegra_dc_format(fb->pixel_format);
49 window.bits_per_pixel = fb->bits_per_pixel;
50
51 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 52 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 53
de2ba664 54 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 55
56 /*
57 * Tegra doesn't support different strides for U and V planes
58 * so we display a warning if the user tries to display a
59 * framebuffer with such a configuration.
60 */
61 if (i >= 2) {
62 if (fb->pitches[i] != window.stride[1])
63 DRM_ERROR("unsupported UV-plane configuration\n");
64 } else {
65 window.stride[i] = fb->pitches[i];
66 }
67 }
68
69 return tegra_dc_setup_window(dc, p->index, &window);
70}
71
72static int tegra_plane_disable(struct drm_plane *plane)
73{
74 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
75 struct tegra_plane *p = to_tegra_plane(plane);
76 unsigned long value;
77
2678aeba
TR		 78 if (!plane->crtc)
79 return 0;
80
f34bc787
TR		 81 value = WINDOW_A_SELECT << p->index;
82 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
83
84 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
85 value &= ~WIN_ENABLE;
86 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
87
88 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
89 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
90
91 return 0;
92}
93
94static void tegra_plane_destroy(struct drm_plane *plane)
95{
96 tegra_plane_disable(plane);
97 drm_plane_cleanup(plane);
98}
99
100static const struct drm_plane_funcs tegra_plane_funcs = {
101 .update_plane = tegra_plane_update,
102 .disable_plane = tegra_plane_disable,
103 .destroy = tegra_plane_destroy,
104};
105
106static const uint32_t plane_formats[] = {
dbe4d9a7 107 DRM_FORMAT_XBGR8888,
f34bc787 108 DRM_FORMAT_XRGB8888,
dbe4d9a7 109 DRM_FORMAT_RGB565,
f34bc787
TR		 110 DRM_FORMAT_UYVY,
111 DRM_FORMAT_YUV420,
112 DRM_FORMAT_YUV422,
113};
114
115static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
116{
117 unsigned int i;
118 int err = 0;
119
120 for (i = 0; i < 2; i++) {
121 struct tegra_plane *plane;
122
123 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
124 if (!plane)
125 return -ENOMEM;
126
127 plane->index = 1 + i;
128
129 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
130 &tegra_plane_funcs, plane_formats,
131 ARRAY_SIZE(plane_formats), false);
132 if (err < 0)
133 return err;
134 }
135
136 return 0;
137}
138
23fb4740
TR		 139static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
140 struct drm_framebuffer *fb)
141{
ed683aea 142 unsigned int format = tegra_dc_format(fb->pixel_format);
de2ba664 143 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
23fb4740
TR		 144 unsigned long value;
145
146 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
147
148 value = fb->offsets[0] + y * fb->pitches[0] +
149 x * fb->bits_per_pixel / 8;
150
de2ba664 151 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 152 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
ed683aea 153 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
23fb4740
TR		 154
155 value = GENERAL_UPDATE | WIN_A_UPDATE;
156 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
157
158 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
159 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
160
161 return 0;
162}
163
6e5ff998
TR		 164void tegra_dc_enable_vblank(struct tegra_dc *dc)
165{
166 unsigned long value, flags;
167
168 spin_lock_irqsave(&dc->lock, flags);
169
170 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
171 value |= VBLANK_INT;
172 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
173
174 spin_unlock_irqrestore(&dc->lock, flags);
175}
176
177void tegra_dc_disable_vblank(struct tegra_dc *dc)
178{
179 unsigned long value, flags;
180
181 spin_lock_irqsave(&dc->lock, flags);
182
183 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
184 value &= ~VBLANK_INT;
185 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
186
187 spin_unlock_irqrestore(&dc->lock, flags);
188}
189
3c03c46a
TR		 190static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
191{
192 struct drm_device *drm = dc->base.dev;
193 struct drm_crtc *crtc = &dc->base;
3c03c46a 194 unsigned long flags, base;
de2ba664 195 struct tegra_bo *bo;
3c03c46a
TR		 196
197 if (!dc->event)
198 return;
199
de2ba664 200 bo = tegra_fb_get_plane(crtc->fb, 0);
3c03c46a
TR		 201
202 /* check if new start address has been latched */
203 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
204 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
205 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
206
de2ba664 207 if (base == bo->paddr + crtc->fb->offsets[0]) {
3c03c46a
TR		 208 spin_lock_irqsave(&drm->event_lock, flags);
209 drm_send_vblank_event(drm, dc->pipe, dc->event);
210 drm_vblank_put(drm, dc->pipe);
211 dc->event = NULL;
212 spin_unlock_irqrestore(&drm->event_lock, flags);
213 }
214}
215
216void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
217{
218 struct tegra_dc *dc = to_tegra_dc(crtc);
219 struct drm_device *drm = crtc->dev;
220 unsigned long flags;
221
222 spin_lock_irqsave(&drm->event_lock, flags);
223
224 if (dc->event && dc->event->base.file_priv == file) {
225 dc->event->base.destroy(&dc->event->base);
226 drm_vblank_put(drm, dc->pipe);
227 dc->event = NULL;
228 }
229
230 spin_unlock_irqrestore(&drm->event_lock, flags);
231}
232
233static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 234 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a
TR		 235{
236 struct tegra_dc *dc = to_tegra_dc(crtc);
237 struct drm_device *drm = crtc->dev;
238
239 if (dc->event)
240 return -EBUSY;
241
242 if (event) {
243 event->pipe = dc->pipe;
244 dc->event = event;
245 drm_vblank_get(drm, dc->pipe);
246 }
247
248 tegra_dc_set_base(dc, 0, 0, fb);
249 crtc->fb = fb;
250
251 return 0;
252}
253
d8f4a9ed 254static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 255 .page_flip = tegra_dc_page_flip,
d8f4a9ed
TR		 256 .set_config = drm_crtc_helper_set_config,
257 .destroy = drm_crtc_cleanup,
258};
259
f34bc787 260static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 261{
f34bc787
TR		 262 struct drm_device *drm = crtc->dev;
263 struct drm_plane *plane;
264
265 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
266 if (plane->crtc == crtc) {
267 tegra_plane_disable(plane);
268 plane->crtc = NULL;
269
270 if (plane->fb) {
271 drm_framebuffer_unreference(plane->fb);
272 plane->fb = NULL;
273 }
274 }
275 }
d8f4a9ed
TR		 276}
277
278static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
279 const struct drm_display_mode *mode,
280 struct drm_display_mode *adjusted)
281{
282 return true;
283}
284
f34bc787 285static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 286 unsigned int bpp)
287{
288 fixed20_12 outf = dfixed_init(out);
f34bc787 289 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 290 u32 dda_inc;
291 int max;
292
293 if (v)
294 max = 15;
295 else {
296 switch (bpp) {
297 case 2:
298 max = 8;
299 break;
300
301 default:
302 WARN_ON_ONCE(1);
303 /* fallthrough */
304 case 4:
305 max = 4;
306 break;
307 }
308 }
309
310 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
311 inf.full -= dfixed_const(1);
312
313 dda_inc = dfixed_div(inf, outf);
314 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
315
316 return dda_inc;
317}
318
f34bc787 319static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 320{
f34bc787
TR		 321 fixed20_12 inf = dfixed_init(in);
322 return dfixed_frac(inf);
d8f4a9ed
TR		 323}
324
325static int tegra_dc_set_timings(struct tegra_dc *dc,
326 struct drm_display_mode *mode)
327{
328 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
329 unsigned int h_ref_to_sync = 0;
330 unsigned int v_ref_to_sync = 0;
331 unsigned long value;
332
333 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
334
335 value = (v_ref_to_sync << 16) | h_ref_to_sync;
336 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
337
338 value = ((mode->vsync_end - mode->vsync_start) << 16) |
339 ((mode->hsync_end - mode->hsync_start) << 0);
340 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
341
d8f4a9ed
TR		 342 value = ((mode->vtotal - mode->vsync_end) << 16) |
343 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 344 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
345
346 value = ((mode->vsync_start - mode->vdisplay) << 16) |
347 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 348 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
349
350 value = (mode->vdisplay << 16) | mode->hdisplay;
351 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
352
353 return 0;
354}
355
356static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
357 struct drm_display_mode *mode,
358 unsigned long *div)
359{
360 unsigned long pclk = mode->clock * 1000, rate;
361 struct tegra_dc *dc = to_tegra_dc(crtc);
362 struct tegra_output *output = NULL;
363 struct drm_encoder *encoder;
364 long err;
365
366 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
367 if (encoder->crtc == crtc) {
368 output = encoder_to_output(encoder);
369 break;
370 }
371
372 if (!output)
373 return -ENODEV;
374
375 /*
376 * This assumes that the display controller will divide its parent
377 * clock by 2 to generate the pixel clock.
378 */
379 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
380 if (err < 0) {
381 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
382 return err;
383 }
384
385 rate = clk_get_rate(dc->clk);
386 *div = (rate * 2 / pclk) - 2;
387
388 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
389
390 return 0;
391}
392
f34bc787
TR		 393static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
394{
395 switch (format) {
396 case WIN_COLOR_DEPTH_YCbCr422:
397 case WIN_COLOR_DEPTH_YUV422:
398 if (planar)
399 *planar = false;
400
401 return true;
402
403 case WIN_COLOR_DEPTH_YCbCr420P:
404 case WIN_COLOR_DEPTH_YUV420P:
405 case WIN_COLOR_DEPTH_YCbCr422P:
406 case WIN_COLOR_DEPTH_YUV422P:
407 case WIN_COLOR_DEPTH_YCbCr422R:
408 case WIN_COLOR_DEPTH_YUV422R:
409 case WIN_COLOR_DEPTH_YCbCr422RA:
410 case WIN_COLOR_DEPTH_YUV422RA:
411 if (planar)
412 *planar = true;
413
414 return true;
415 }
416
417 return false;
418}
419
420int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
421 const struct tegra_dc_window *window)
422{
423 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
424 unsigned long value;
425 bool yuv, planar;
426
427 /*
428 * For YUV planar modes, the number of bytes per pixel takes into
429 * account only the luma component and therefore is 1.
430 */
431 yuv = tegra_dc_format_is_yuv(window->format, &planar);
432 if (!yuv)
433 bpp = window->bits_per_pixel / 8;
434 else
435 bpp = planar ? 1 : 2;
436
437 value = WINDOW_A_SELECT << index;
438 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
439
440 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
441 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
442
443 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
444 tegra_dc_writel(dc, value, DC_WIN_POSITION);
445
446 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
447 tegra_dc_writel(dc, value, DC_WIN_SIZE);
448
449 h_offset = window->src.x * bpp;
450 v_offset = window->src.y;
451 h_size = window->src.w * bpp;
452 v_size = window->src.h;
453
454 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
455 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
456
457 /*
458 * For DDA computations the number of bytes per pixel for YUV planar
459 * modes needs to take into account all Y, U and V components.
460 */
461 if (yuv && planar)
462 bpp = 2;
463
464 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
465 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
466
467 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
468 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
469
470 h_dda = compute_initial_dda(window->src.x);
471 v_dda = compute_initial_dda(window->src.y);
472
473 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
474 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
475
476 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
477 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
478
479 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
480
481 if (yuv && planar) {
482 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
483 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
484 value = window->stride[1] << 16 | window->stride[0];
485 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
486 } else {
487 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
488 }
489
490 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
491 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
492
493 value = WIN_ENABLE;
494
495 if (yuv) {
496 /* setup default colorspace conversion coefficients */
497 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
498 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
499 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
500 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
501 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
502 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
503 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
504 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
505
506 value |= CSC_ENABLE;
84ff6b27 507 } else if (window->bits_per_pixel < 24) {
f34bc787
TR		 508 value |= COLOR_EXPAND;
509 }
510
511 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
512
513 /*
514 * Disable blending and assume Window A is the bottom-most window,
515 * Window C is the top-most window and Window B is in the middle.
516 */
517 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
518 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
519
520 switch (index) {
521 case 0:
522 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
523 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
524 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
525 break;
526
527 case 1:
528 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
529 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
530 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
531 break;
532
533 case 2:
534 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
535 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
536 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
537 break;
538 }
539
540 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
541 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
542
543 return 0;
544}
545
546unsigned int tegra_dc_format(uint32_t format)
547{
548 switch (format) {
dbe4d9a7
TR		 549 case DRM_FORMAT_XBGR8888:
550 return WIN_COLOR_DEPTH_R8G8B8A8;
551
f34bc787
TR		 552 case DRM_FORMAT_XRGB8888:
553 return WIN_COLOR_DEPTH_B8G8R8A8;
554
555 case DRM_FORMAT_RGB565:
556 return WIN_COLOR_DEPTH_B5G6R5;
557
558 case DRM_FORMAT_UYVY:
559 return WIN_COLOR_DEPTH_YCbCr422;
560
561 case DRM_FORMAT_YUV420:
562 return WIN_COLOR_DEPTH_YCbCr420P;
563
564 case DRM_FORMAT_YUV422:
565 return WIN_COLOR_DEPTH_YCbCr422P;
566
567 default:
568 break;
569 }
570
571 WARN(1, "unsupported pixel format %u, using default\n", format);
572 return WIN_COLOR_DEPTH_B8G8R8A8;
573}
574
d8f4a9ed
TR		 575static int tegra_crtc_mode_set(struct drm_crtc *crtc,
576 struct drm_display_mode *mode,
577 struct drm_display_mode *adjusted,
578 int x, int y, struct drm_framebuffer *old_fb)
579{
de2ba664 580 struct tegra_bo *bo = tegra_fb_get_plane(crtc->fb, 0);
d8f4a9ed 581 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 582 struct tegra_dc_window window;
d8f4a9ed
TR		 583 unsigned long div, value;
584 int err;
585
6e5ff998
TR		 586 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
587
d8f4a9ed
TR		 588 err = tegra_crtc_setup_clk(crtc, mode, &div);
589 if (err) {
590 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
591 return err;
592 }
593
594 /* program display mode */
595 tegra_dc_set_timings(dc, mode);
596
597 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
598 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
599
600 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
601 value &= ~LVS_OUTPUT_POLARITY_LOW;
602 value &= ~LHS_OUTPUT_POLARITY_LOW;
603 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
604
605 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
606 DISP_ORDER_RED_BLUE;
607 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
608
609 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
610
611 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
612 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
613
614 /* setup window parameters */
f34bc787
TR		 615 memset(&window, 0, sizeof(window));
616 window.src.x = 0;
617 window.src.y = 0;
618 window.src.w = mode->hdisplay;
619 window.src.h = mode->vdisplay;
620 window.dst.x = 0;
621 window.dst.y = 0;
622 window.dst.w = mode->hdisplay;
623 window.dst.h = mode->vdisplay;
624 window.format = tegra_dc_format(crtc->fb->pixel_format);
625 window.bits_per_pixel = crtc->fb->bits_per_pixel;
626 window.stride[0] = crtc->fb->pitches[0];
de2ba664 627 window.base[0] = bo->paddr;
f34bc787
TR		 628
629 err = tegra_dc_setup_window(dc, 0, &window);
630 if (err < 0)
631 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 632
d8f4a9ed
TR		 633 return 0;
634}
d8f4a9ed 635
23fb4740
TR		 636static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
637 struct drm_framebuffer *old_fb)
638{
639 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 640
23fb4740 641 return tegra_dc_set_base(dc, x, y, crtc->fb);
d8f4a9ed
TR		 642}
643
644static void tegra_crtc_prepare(struct drm_crtc *crtc)
645{
646 struct tegra_dc *dc = to_tegra_dc(crtc);
647 unsigned int syncpt;
648 unsigned long value;
649
650 /* hardware initialization */
651 tegra_periph_reset_deassert(dc->clk);
652 usleep_range(10000, 20000);
653
654 if (dc->pipe)
655 syncpt = SYNCPT_VBLANK1;
656 else
657 syncpt = SYNCPT_VBLANK0;
658
659 /* initialize display controller */
660 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
661 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
662
663 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
664 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
665
666 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
667 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
668 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
669
670 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
671 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
672 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
673
674 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
675 value |= DISP_CTRL_MODE_C_DISPLAY;
676 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
677
678 /* initialize timer */
679 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
680 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
681 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
682
683 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
684 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
685 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
686
d8f4a9ed
TR		 687 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
688 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 689
690 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
691 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 692}
693
694static void tegra_crtc_commit(struct drm_crtc *crtc)
695{
696 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 697 unsigned long value;
698
3b9e71ea
TR		 699 value = GENERAL_UPDATE | WIN_A_UPDATE;
700 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 701
3b9e71ea 702 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 703 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 704
6e5ff998 705 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 706}
707
708static void tegra_crtc_load_lut(struct drm_crtc *crtc)
709{
710}
711
712static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 713 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 714 .mode_fixup = tegra_crtc_mode_fixup,
715 .mode_set = tegra_crtc_mode_set,
23fb4740 716 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 717 .prepare = tegra_crtc_prepare,
718 .commit = tegra_crtc_commit,
719 .load_lut = tegra_crtc_load_lut,
720};
721
6e5ff998 722static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 723{
724 struct tegra_dc *dc = data;
725 unsigned long status;
726
727 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
728 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
729
730 if (status & FRAME_END_INT) {
731 /*
732 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
733 */
734 }
735
736 if (status & VBLANK_INT) {
737 /*
738 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
739 */
740 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 741 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 742 }
743
744 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
745 /*
746 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
747 */
748 }
749
750 return IRQ_HANDLED;
751}
752
753static int tegra_dc_show_regs(struct seq_file *s, void *data)
754{
755 struct drm_info_node *node = s->private;
756 struct tegra_dc *dc = node->info_ent->data;
757
758#define DUMP_REG(name) \
759 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
760 tegra_dc_readl(dc, name))
761
762 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
763 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
764 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
765 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
766 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
767 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
768 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
769 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
770 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
771 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
772 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
773 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
774 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
775 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
776 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
777 DUMP_REG(DC_CMD_SIGNAL_RAISE);
778 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
779 DUMP_REG(DC_CMD_INT_STATUS);
780 DUMP_REG(DC_CMD_INT_MASK);
781 DUMP_REG(DC_CMD_INT_ENABLE);
782 DUMP_REG(DC_CMD_INT_TYPE);
783 DUMP_REG(DC_CMD_INT_POLARITY);
784 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
785 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
786 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
787 DUMP_REG(DC_CMD_STATE_ACCESS);
788 DUMP_REG(DC_CMD_STATE_CONTROL);
789 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
790 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
791 DUMP_REG(DC_COM_CRC_CONTROL);
792 DUMP_REG(DC_COM_CRC_CHECKSUM);
793 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
794 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
795 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
796 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
797 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
798 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
799 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
800 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
801 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
802 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
803 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
804 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
805 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
806 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
807 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
808 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
809 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
810 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
811 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
812 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
813 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
814 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
815 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
816 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
817 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
818 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
819 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
820 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
821 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
822 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
823 DUMP_REG(DC_COM_SPI_CONTROL);
824 DUMP_REG(DC_COM_SPI_START_BYTE);
825 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
826 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
827 DUMP_REG(DC_COM_HSPI_CS_DC);
828 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
829 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
830 DUMP_REG(DC_COM_GPIO_CTRL);
831 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
832 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
833 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
834 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
835 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
836 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
837 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
838 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
839 DUMP_REG(DC_DISP_REF_TO_SYNC);
840 DUMP_REG(DC_DISP_SYNC_WIDTH);
841 DUMP_REG(DC_DISP_BACK_PORCH);
842 DUMP_REG(DC_DISP_ACTIVE);
843 DUMP_REG(DC_DISP_FRONT_PORCH);
844 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
845 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
846 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
847 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
848 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
849 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
850 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
851 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
852 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
853 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
854 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
855 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
856 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
857 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
858 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
859 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
860 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
861 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
862 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
863 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
864 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
865 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
866 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
867 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
868 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
869 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
870 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
871 DUMP_REG(DC_DISP_M0_CONTROL);
872 DUMP_REG(DC_DISP_M1_CONTROL);
873 DUMP_REG(DC_DISP_DI_CONTROL);
874 DUMP_REG(DC_DISP_PP_CONTROL);
875 DUMP_REG(DC_DISP_PP_SELECT_A);
876 DUMP_REG(DC_DISP_PP_SELECT_B);
877 DUMP_REG(DC_DISP_PP_SELECT_C);
878 DUMP_REG(DC_DISP_PP_SELECT_D);
879 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
880 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
881 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
882 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
883 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
884 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
885 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
886 DUMP_REG(DC_DISP_BORDER_COLOR);
887 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
888 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
889 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
890 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
891 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
892 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
893 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
894 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
895 DUMP_REG(DC_DISP_CURSOR_POSITION);
896 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
897 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
898 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
899 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
900 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
901 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
902 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
903 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
904 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
905 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
906 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
907 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
908 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
909 DUMP_REG(DC_DISP_SD_CONTROL);
910 DUMP_REG(DC_DISP_SD_CSC_COEFF);
911 DUMP_REG(DC_DISP_SD_LUT(0));
912 DUMP_REG(DC_DISP_SD_LUT(1));
913 DUMP_REG(DC_DISP_SD_LUT(2));
914 DUMP_REG(DC_DISP_SD_LUT(3));
915 DUMP_REG(DC_DISP_SD_LUT(4));
916 DUMP_REG(DC_DISP_SD_LUT(5));
917 DUMP_REG(DC_DISP_SD_LUT(6));
918 DUMP_REG(DC_DISP_SD_LUT(7));
919 DUMP_REG(DC_DISP_SD_LUT(8));
920 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
921 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
922 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
923 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
924 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
925 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
926 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
927 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
928 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
929 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
930 DUMP_REG(DC_DISP_SD_BL_TF(0));
931 DUMP_REG(DC_DISP_SD_BL_TF(1));
932 DUMP_REG(DC_DISP_SD_BL_TF(2));
933 DUMP_REG(DC_DISP_SD_BL_TF(3));
934 DUMP_REG(DC_DISP_SD_BL_CONTROL);
935 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
936 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
937 DUMP_REG(DC_WIN_WIN_OPTIONS);
938 DUMP_REG(DC_WIN_BYTE_SWAP);
939 DUMP_REG(DC_WIN_BUFFER_CONTROL);
940 DUMP_REG(DC_WIN_COLOR_DEPTH);
941 DUMP_REG(DC_WIN_POSITION);
942 DUMP_REG(DC_WIN_SIZE);
943 DUMP_REG(DC_WIN_PRESCALED_SIZE);
944 DUMP_REG(DC_WIN_H_INITIAL_DDA);
945 DUMP_REG(DC_WIN_V_INITIAL_DDA);
946 DUMP_REG(DC_WIN_DDA_INC);
947 DUMP_REG(DC_WIN_LINE_STRIDE);
948 DUMP_REG(DC_WIN_BUF_STRIDE);
949 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
950 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
951 DUMP_REG(DC_WIN_DV_CONTROL);
952 DUMP_REG(DC_WIN_BLEND_NOKEY);
953 DUMP_REG(DC_WIN_BLEND_1WIN);
954 DUMP_REG(DC_WIN_BLEND_2WIN_X);
955 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 956 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 957 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
958 DUMP_REG(DC_WINBUF_START_ADDR);
959 DUMP_REG(DC_WINBUF_START_ADDR_NS);
960 DUMP_REG(DC_WINBUF_START_ADDR_U);
961 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
962 DUMP_REG(DC_WINBUF_START_ADDR_V);
963 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
964 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
965 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
966 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
967 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
968 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
969 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
970 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
971 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
972
973#undef DUMP_REG
974
975 return 0;
976}
977
978static struct drm_info_list debugfs_files[] = {
979 { "regs", tegra_dc_show_regs, 0, NULL },
980};
981
982static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
983{
984 unsigned int i;
985 char *name;
986 int err;
987
988 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
989 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
990 kfree(name);
991
992 if (!dc->debugfs)
993 return -ENOMEM;
994
995 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
996 GFP_KERNEL);
997 if (!dc->debugfs_files) {
998 err = -ENOMEM;
999 goto remove;
1000 }
1001
1002 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1003 dc->debugfs_files[i].data = dc;
1004
1005 err = drm_debugfs_create_files(dc->debugfs_files,
1006 ARRAY_SIZE(debugfs_files),
1007 dc->debugfs, minor);
1008 if (err < 0)
1009 goto free;
1010
1011 dc->minor = minor;
1012
1013 return 0;
1014
1015free:
1016 kfree(dc->debugfs_files);
1017 dc->debugfs_files = NULL;
1018remove:
1019 debugfs_remove(dc->debugfs);
1020 dc->debugfs = NULL;
1021
1022 return err;
1023}
1024
1025static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1026{
1027 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1028 dc->minor);
1029 dc->minor = NULL;
1030
1031 kfree(dc->debugfs_files);
1032 dc->debugfs_files = NULL;
1033
1034 debugfs_remove(dc->debugfs);
1035 dc->debugfs = NULL;
1036
1037 return 0;
1038}
1039
53fa7f72 1040static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1041{
776dc384
TR		 1042 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1043 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1044 int err;
1045
776dc384 1046 dc->pipe = tegra->drm->mode_config.num_crtc;
d8f4a9ed 1047
776dc384 1048 drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs);
d8f4a9ed
TR		 1049 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1050 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1051
776dc384 1052 err = tegra_dc_rgb_init(tegra->drm, dc);
d8f4a9ed
TR		 1053 if (err < 0 && err != -ENODEV) {
1054 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1055 return err;
1056 }
1057
776dc384 1058 err = tegra_dc_add_planes(tegra->drm, dc);
f34bc787
TR		 1059 if (err < 0)
1060 return err;
1061
d8f4a9ed 1062 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
776dc384 1063 err = tegra_dc_debugfs_init(dc, tegra->drm->primary);
d8f4a9ed
TR		 1064 if (err < 0)
1065 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1066 }
1067
6e5ff998 1068 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1069 dev_name(dc->dev), dc);
1070 if (err < 0) {
1071 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1072 err);
1073 return err;
1074 }
1075
1076 return 0;
1077}
1078
53fa7f72 1079static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1080{
776dc384 1081 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1082 int err;
1083
1084 devm_free_irq(dc->dev, dc->irq, dc);
1085
1086 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1087 err = tegra_dc_debugfs_exit(dc);
1088 if (err < 0)
1089 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1090 }
1091
1092 err = tegra_dc_rgb_exit(dc);
1093 if (err) {
1094 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1095 return err;
1096 }
1097
1098 return 0;
1099}
1100
1101static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1102 .init = tegra_dc_init,
1103 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1104};
1105
1106static int tegra_dc_probe(struct platform_device *pdev)
1107{
d8f4a9ed
TR		 1108 struct resource *regs;
1109 struct tegra_dc *dc;
1110 int err;
1111
1112 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1113 if (!dc)
1114 return -ENOMEM;
1115
6e5ff998 1116 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1117 INIT_LIST_HEAD(&dc->list);
1118 dc->dev = &pdev->dev;
1119
1120 dc->clk = devm_clk_get(&pdev->dev, NULL);
1121 if (IS_ERR(dc->clk)) {
1122 dev_err(&pdev->dev, "failed to get clock\n");
1123 return PTR_ERR(dc->clk);
1124 }
1125
1126 err = clk_prepare_enable(dc->clk);
1127 if (err < 0)
1128 return err;
1129
1130 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1131 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1132 if (IS_ERR(dc->regs))
1133 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1134
1135 dc->irq = platform_get_irq(pdev, 0);
1136 if (dc->irq < 0) {
1137 dev_err(&pdev->dev, "failed to get IRQ\n");
1138 return -ENXIO;
1139 }
1140
776dc384
TR		 1141 INIT_LIST_HEAD(&dc->client.list);
1142 dc->client.ops = &dc_client_ops;
1143 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1144
1145 err = tegra_dc_rgb_probe(dc);
1146 if (err < 0 && err != -ENODEV) {
1147 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1148 return err;
1149 }
1150
776dc384 1151 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1152 if (err < 0) {
1153 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1154 err);
1155 return err;
1156 }
1157
1158 platform_set_drvdata(pdev, dc);
1159
1160 return 0;
1161}
1162
1163static int tegra_dc_remove(struct platform_device *pdev)
1164{
d8f4a9ed
TR		 1165 struct tegra_dc *dc = platform_get_drvdata(pdev);
1166 int err;
1167
776dc384 1168 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1169 if (err < 0) {
1170 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1171 err);
1172 return err;
1173 }
1174
1175 clk_disable_unprepare(dc->clk);
1176
1177 return 0;
1178}
1179
1180static struct of_device_id tegra_dc_of_match[] = {
219e8153 1181 { .compatible = "nvidia,tegra30-dc", },
d8f4a9ed
TR		 1182 { .compatible = "nvidia,tegra20-dc", },
1183 { },
1184};
1185
1186struct platform_driver tegra_dc_driver = {
1187 .driver = {
1188 .name = "tegra-dc",
1189 .owner = THIS_MODULE,
1190 .of_match_table = tegra_dc_of_match,
1191 },
1192 .probe = tegra_dc_probe,
1193 .remove = tegra_dc_remove,
1194};
Linux kernel - Deliverables
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