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drm/tegra: dc - Rename INVERT_V to V_DIRECTION
[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
9eb9b220 11#include <linux/debugfs.h>
ca48080a 12#include <linux/reset.h>
d8f4a9ed 13
de2ba664
AM		 14#include "dc.h"
15#include "drm.h"
16#include "gem.h"
d8f4a9ed 17
8620fc62
TR		 18struct tegra_dc_soc_info {
19 bool supports_interlacing;
20};
21
f34bc787
TR		 22struct tegra_plane {
23 struct drm_plane base;
24 unsigned int index;
d8f4a9ed
TR		 25};
26
f34bc787
TR		 27static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
28{
29 return container_of(plane, struct tegra_plane, base);
30}
31
32static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
33 struct drm_framebuffer *fb, int crtc_x,
34 int crtc_y, unsigned int crtc_w,
35 unsigned int crtc_h, uint32_t src_x,
36 uint32_t src_y, uint32_t src_w, uint32_t src_h)
37{
38 struct tegra_plane *p = to_tegra_plane(plane);
39 struct tegra_dc *dc = to_tegra_dc(crtc);
40 struct tegra_dc_window window;
41 unsigned int i;
42
43 memset(&window, 0, sizeof(window));
44 window.src.x = src_x >> 16;
45 window.src.y = src_y >> 16;
46 window.src.w = src_w >> 16;
47 window.src.h = src_h >> 16;
48 window.dst.x = crtc_x;
49 window.dst.y = crtc_y;
50 window.dst.w = crtc_w;
51 window.dst.h = crtc_h;
f925390e 52 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
f34bc787 53 window.bits_per_pixel = fb->bits_per_pixel;
db7fbdfd 54 window.bottom_up = tegra_fb_is_bottom_up(fb);
773af77f 55 window.tiled = tegra_fb_is_tiled(fb);
f34bc787
TR		 56
57 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 58 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 59
de2ba664 60 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 61
62 /*
63 * Tegra doesn't support different strides for U and V planes
64 * so we display a warning if the user tries to display a
65 * framebuffer with such a configuration.
66 */
67 if (i >= 2) {
68 if (fb->pitches[i] != window.stride[1])
69 DRM_ERROR("unsupported UV-plane configuration\n");
70 } else {
71 window.stride[i] = fb->pitches[i];
72 }
73 }
74
75 return tegra_dc_setup_window(dc, p->index, &window);
76}
77
78static int tegra_plane_disable(struct drm_plane *plane)
79{
80 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
81 struct tegra_plane *p = to_tegra_plane(plane);
82 unsigned long value;
83
2678aeba
TR		 84 if (!plane->crtc)
85 return 0;
86
f34bc787
TR		 87 value = WINDOW_A_SELECT << p->index;
88 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
89
90 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
91 value &= ~WIN_ENABLE;
92 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
93
94 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
95 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
96
97 return 0;
98}
99
100static void tegra_plane_destroy(struct drm_plane *plane)
101{
f002abc1
TR		 102 struct tegra_plane *p = to_tegra_plane(plane);
103
f34bc787
TR		 104 tegra_plane_disable(plane);
105 drm_plane_cleanup(plane);
f002abc1 106 kfree(p);
f34bc787
TR		 107}
108
109static const struct drm_plane_funcs tegra_plane_funcs = {
110 .update_plane = tegra_plane_update,
111 .disable_plane = tegra_plane_disable,
112 .destroy = tegra_plane_destroy,
113};
114
115static const uint32_t plane_formats[] = {
dbe4d9a7 116 DRM_FORMAT_XBGR8888,
f34bc787 117 DRM_FORMAT_XRGB8888,
dbe4d9a7 118 DRM_FORMAT_RGB565,
f34bc787 119 DRM_FORMAT_UYVY,
f925390e 120 DRM_FORMAT_YUYV,
f34bc787
TR		 121 DRM_FORMAT_YUV420,
122 DRM_FORMAT_YUV422,
123};
124
125static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
126{
127 unsigned int i;
128 int err = 0;
129
130 for (i = 0; i < 2; i++) {
131 struct tegra_plane *plane;
132
f002abc1 133 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
f34bc787
TR		 134 if (!plane)
135 return -ENOMEM;
136
137 plane->index = 1 + i;
138
139 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
140 &tegra_plane_funcs, plane_formats,
141 ARRAY_SIZE(plane_formats), false);
f002abc1
TR		 142 if (err < 0) {
143 kfree(plane);
f34bc787 144 return err;
f002abc1 145 }
f34bc787
TR		 146 }
147
148 return 0;
149}
150
23fb4740
TR		 151static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
152 struct drm_framebuffer *fb)
153{
de2ba664 154 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
db7fbdfd 155 unsigned int h_offset = 0, v_offset = 0;
f925390e 156 unsigned int format, swap;
23fb4740
TR		 157 unsigned long value;
158
159 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
160
161 value = fb->offsets[0] + y * fb->pitches[0] +
162 x * fb->bits_per_pixel / 8;
163
de2ba664 164 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 165 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
f925390e
TR		 166
167 format = tegra_dc_format(fb->pixel_format, &swap);
ed683aea 168 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
f925390e 169 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
23fb4740 170
773af77f
TR		 171 if (tegra_fb_is_tiled(fb)) {
172 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
173 DC_WIN_BUFFER_ADDR_MODE_TILE;
174 } else {
175 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
176 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
177 }
178
179 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
180
db7fbdfd
TR		 181 /* make sure bottom-up buffers are properly displayed */
182 if (tegra_fb_is_bottom_up(fb)) {
183 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 184 value |= V_DIRECTION;
db7fbdfd
TR		 185 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
186
187 v_offset += fb->height - 1;
188 } else {
189 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
eba66501 190 value &= ~V_DIRECTION;
db7fbdfd
TR		 191 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
192 }
193
194 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
195 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
196
23fb4740
TR		 197 value = GENERAL_UPDATE | WIN_A_UPDATE;
198 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
199
200 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
201 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
202
203 return 0;
204}
205
6e5ff998
TR		 206void tegra_dc_enable_vblank(struct tegra_dc *dc)
207{
208 unsigned long value, flags;
209
210 spin_lock_irqsave(&dc->lock, flags);
211
212 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
213 value |= VBLANK_INT;
214 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
215
216 spin_unlock_irqrestore(&dc->lock, flags);
217}
218
219void tegra_dc_disable_vblank(struct tegra_dc *dc)
220{
221 unsigned long value, flags;
222
223 spin_lock_irqsave(&dc->lock, flags);
224
225 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
226 value &= ~VBLANK_INT;
227 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
228
229 spin_unlock_irqrestore(&dc->lock, flags);
230}
231
3c03c46a
TR		 232static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
233{
234 struct drm_device *drm = dc->base.dev;
235 struct drm_crtc *crtc = &dc->base;
3c03c46a 236 unsigned long flags, base;
de2ba664 237 struct tegra_bo *bo;
3c03c46a
TR		 238
239 if (!dc->event)
240 return;
241
f4510a27 242 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
3c03c46a
TR		 243
244 /* check if new start address has been latched */
245 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
246 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
247 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
248
f4510a27 249 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
3c03c46a
TR		 250 spin_lock_irqsave(&drm->event_lock, flags);
251 drm_send_vblank_event(drm, dc->pipe, dc->event);
252 drm_vblank_put(drm, dc->pipe);
253 dc->event = NULL;
254 spin_unlock_irqrestore(&drm->event_lock, flags);
255 }
256}
257
258void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
259{
260 struct tegra_dc *dc = to_tegra_dc(crtc);
261 struct drm_device *drm = crtc->dev;
262 unsigned long flags;
263
264 spin_lock_irqsave(&drm->event_lock, flags);
265
266 if (dc->event && dc->event->base.file_priv == file) {
267 dc->event->base.destroy(&dc->event->base);
268 drm_vblank_put(drm, dc->pipe);
269 dc->event = NULL;
270 }
271
272 spin_unlock_irqrestore(&drm->event_lock, flags);
273}
274
275static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 276 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a
TR		 277{
278 struct tegra_dc *dc = to_tegra_dc(crtc);
279 struct drm_device *drm = crtc->dev;
280
281 if (dc->event)
282 return -EBUSY;
283
284 if (event) {
285 event->pipe = dc->pipe;
286 dc->event = event;
287 drm_vblank_get(drm, dc->pipe);
288 }
289
290 tegra_dc_set_base(dc, 0, 0, fb);
f4510a27 291 crtc->primary->fb = fb;
3c03c46a
TR		 292
293 return 0;
294}
295
f002abc1
TR		 296static void drm_crtc_clear(struct drm_crtc *crtc)
297{
298 memset(crtc, 0, sizeof(*crtc));
299}
300
301static void tegra_dc_destroy(struct drm_crtc *crtc)
302{
303 drm_crtc_cleanup(crtc);
304 drm_crtc_clear(crtc);
305}
306
d8f4a9ed 307static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 308 .page_flip = tegra_dc_page_flip,
d8f4a9ed 309 .set_config = drm_crtc_helper_set_config,
f002abc1 310 .destroy = tegra_dc_destroy,
d8f4a9ed
TR		 311};
312
f34bc787 313static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 314{
f002abc1 315 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787
TR		 316 struct drm_device *drm = crtc->dev;
317 struct drm_plane *plane;
318
2b4c3661 319 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
f34bc787
TR		 320 if (plane->crtc == crtc) {
321 tegra_plane_disable(plane);
322 plane->crtc = NULL;
323
324 if (plane->fb) {
325 drm_framebuffer_unreference(plane->fb);
326 plane->fb = NULL;
327 }
328 }
329 }
f002abc1
TR		 330
331 drm_vblank_off(drm, dc->pipe);
d8f4a9ed
TR		 332}
333
334static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
335 const struct drm_display_mode *mode,
336 struct drm_display_mode *adjusted)
337{
338 return true;
339}
340
f34bc787 341static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 342 unsigned int bpp)
343{
344 fixed20_12 outf = dfixed_init(out);
f34bc787 345 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 346 u32 dda_inc;
347 int max;
348
349 if (v)
350 max = 15;
351 else {
352 switch (bpp) {
353 case 2:
354 max = 8;
355 break;
356
357 default:
358 WARN_ON_ONCE(1);
359 /* fallthrough */
360 case 4:
361 max = 4;
362 break;
363 }
364 }
365
366 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
367 inf.full -= dfixed_const(1);
368
369 dda_inc = dfixed_div(inf, outf);
370 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
371
372 return dda_inc;
373}
374
f34bc787 375static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 376{
f34bc787
TR		 377 fixed20_12 inf = dfixed_init(in);
378 return dfixed_frac(inf);
d8f4a9ed
TR		 379}
380
381static int tegra_dc_set_timings(struct tegra_dc *dc,
382 struct drm_display_mode *mode)
383{
384 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
385 unsigned int h_ref_to_sync = 0;
386 unsigned int v_ref_to_sync = 0;
387 unsigned long value;
388
389 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
390
391 value = (v_ref_to_sync << 16) | h_ref_to_sync;
392 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
393
394 value = ((mode->vsync_end - mode->vsync_start) << 16) |
395 ((mode->hsync_end - mode->hsync_start) << 0);
396 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
397
d8f4a9ed
TR		 398 value = ((mode->vtotal - mode->vsync_end) << 16) |
399 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 400 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
401
402 value = ((mode->vsync_start - mode->vdisplay) << 16) |
403 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 404 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
405
406 value = (mode->vdisplay << 16) | mode->hdisplay;
407 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
408
409 return 0;
410}
411
412static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
413 struct drm_display_mode *mode,
414 unsigned long *div)
415{
416 unsigned long pclk = mode->clock * 1000, rate;
417 struct tegra_dc *dc = to_tegra_dc(crtc);
418 struct tegra_output *output = NULL;
419 struct drm_encoder *encoder;
420 long err;
421
422 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
423 if (encoder->crtc == crtc) {
424 output = encoder_to_output(encoder);
425 break;
426 }
427
428 if (!output)
429 return -ENODEV;
430
431 /*
432 * This assumes that the display controller will divide its parent
433 * clock by 2 to generate the pixel clock.
434 */
435 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
436 if (err < 0) {
437 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
438 return err;
439 }
440
441 rate = clk_get_rate(dc->clk);
442 *div = (rate * 2 / pclk) - 2;
443
444 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
445
446 return 0;
447}
448
f34bc787
TR		 449static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
450{
451 switch (format) {
452 case WIN_COLOR_DEPTH_YCbCr422:
453 case WIN_COLOR_DEPTH_YUV422:
454 if (planar)
455 *planar = false;
456
457 return true;
458
459 case WIN_COLOR_DEPTH_YCbCr420P:
460 case WIN_COLOR_DEPTH_YUV420P:
461 case WIN_COLOR_DEPTH_YCbCr422P:
462 case WIN_COLOR_DEPTH_YUV422P:
463 case WIN_COLOR_DEPTH_YCbCr422R:
464 case WIN_COLOR_DEPTH_YUV422R:
465 case WIN_COLOR_DEPTH_YCbCr422RA:
466 case WIN_COLOR_DEPTH_YUV422RA:
467 if (planar)
468 *planar = true;
469
470 return true;
471 }
472
473 return false;
474}
475
476int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
477 const struct tegra_dc_window *window)
478{
479 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
480 unsigned long value;
481 bool yuv, planar;
482
483 /*
484 * For YUV planar modes, the number of bytes per pixel takes into
485 * account only the luma component and therefore is 1.
486 */
487 yuv = tegra_dc_format_is_yuv(window->format, &planar);
488 if (!yuv)
489 bpp = window->bits_per_pixel / 8;
490 else
491 bpp = planar ? 1 : 2;
492
493 value = WINDOW_A_SELECT << index;
494 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
495
496 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
f925390e 497 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
f34bc787
TR		 498
499 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
500 tegra_dc_writel(dc, value, DC_WIN_POSITION);
501
502 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
503 tegra_dc_writel(dc, value, DC_WIN_SIZE);
504
505 h_offset = window->src.x * bpp;
506 v_offset = window->src.y;
507 h_size = window->src.w * bpp;
508 v_size = window->src.h;
509
510 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
511 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
512
513 /*
514 * For DDA computations the number of bytes per pixel for YUV planar
515 * modes needs to take into account all Y, U and V components.
516 */
517 if (yuv && planar)
518 bpp = 2;
519
520 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
521 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
522
523 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
524 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
525
526 h_dda = compute_initial_dda(window->src.x);
527 v_dda = compute_initial_dda(window->src.y);
528
529 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
530 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
531
532 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
533 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
534
535 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
536
537 if (yuv && planar) {
538 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
539 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
540 value = window->stride[1] << 16 | window->stride[0];
541 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
542 } else {
543 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
544 }
545
db7fbdfd
TR		 546 if (window->bottom_up)
547 v_offset += window->src.h - 1;
548
f34bc787
TR		 549 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
550 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
551
773af77f
TR		 552 if (window->tiled) {
553 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
554 DC_WIN_BUFFER_ADDR_MODE_TILE;
555 } else {
556 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
557 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
558 }
559
560 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
561
f34bc787
TR		 562 value = WIN_ENABLE;
563
564 if (yuv) {
565 /* setup default colorspace conversion coefficients */
566 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
567 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
568 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
569 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
570 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
571 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
572 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
573 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
574
575 value |= CSC_ENABLE;
84ff6b27 576 } else if (window->bits_per_pixel < 24) {
f34bc787
TR		 577 value |= COLOR_EXPAND;
578 }
579
db7fbdfd 580 if (window->bottom_up)
eba66501 581 value |= V_DIRECTION;
db7fbdfd 582
f34bc787
TR		 583 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
584
585 /*
586 * Disable blending and assume Window A is the bottom-most window,
587 * Window C is the top-most window and Window B is in the middle.
588 */
589 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
590 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
591
592 switch (index) {
593 case 0:
594 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
595 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
596 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
597 break;
598
599 case 1:
600 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
601 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
602 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
603 break;
604
605 case 2:
606 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
607 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
608 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
609 break;
610 }
611
612 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
613 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
614
615 return 0;
616}
617
f925390e 618unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
f34bc787 619{
f925390e
TR		 620 /* assume no swapping of fetched data */
621 if (swap)
622 *swap = BYTE_SWAP_NOSWAP;
623
f34bc787 624 switch (format) {
dbe4d9a7
TR		 625 case DRM_FORMAT_XBGR8888:
626 return WIN_COLOR_DEPTH_R8G8B8A8;
627
f34bc787
TR		 628 case DRM_FORMAT_XRGB8888:
629 return WIN_COLOR_DEPTH_B8G8R8A8;
630
631 case DRM_FORMAT_RGB565:
632 return WIN_COLOR_DEPTH_B5G6R5;
633
634 case DRM_FORMAT_UYVY:
635 return WIN_COLOR_DEPTH_YCbCr422;
636
f925390e
TR		 637 case DRM_FORMAT_YUYV:
638 if (swap)
639 *swap = BYTE_SWAP_SWAP2;
640
641 return WIN_COLOR_DEPTH_YCbCr422;
642
f34bc787
TR		 643 case DRM_FORMAT_YUV420:
644 return WIN_COLOR_DEPTH_YCbCr420P;
645
646 case DRM_FORMAT_YUV422:
647 return WIN_COLOR_DEPTH_YCbCr422P;
648
649 default:
650 break;
651 }
652
653 WARN(1, "unsupported pixel format %u, using default\n", format);
654 return WIN_COLOR_DEPTH_B8G8R8A8;
655}
656
d8f4a9ed
TR		 657static int tegra_crtc_mode_set(struct drm_crtc *crtc,
658 struct drm_display_mode *mode,
659 struct drm_display_mode *adjusted,
660 int x, int y, struct drm_framebuffer *old_fb)
661{
f4510a27 662 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
d8f4a9ed 663 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 664 struct tegra_dc_window window;
d8f4a9ed
TR		 665 unsigned long div, value;
666 int err;
667
6e5ff998
TR		 668 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
669
d8f4a9ed
TR		 670 err = tegra_crtc_setup_clk(crtc, mode, &div);
671 if (err) {
672 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
673 return err;
674 }
675
676 /* program display mode */
677 tegra_dc_set_timings(dc, mode);
678
8620fc62
TR		 679 /* interlacing isn't supported yet, so disable it */
680 if (dc->soc->supports_interlacing) {
681 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
682 value &= ~INTERLACE_ENABLE;
683 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
684 }
685
d8f4a9ed
TR		 686 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
687 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
688
689 /* setup window parameters */
f34bc787
TR		 690 memset(&window, 0, sizeof(window));
691 window.src.x = 0;
692 window.src.y = 0;
693 window.src.w = mode->hdisplay;
694 window.src.h = mode->vdisplay;
695 window.dst.x = 0;
696 window.dst.y = 0;
697 window.dst.w = mode->hdisplay;
698 window.dst.h = mode->vdisplay;
f925390e
TR		 699 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
700 &window.swap);
f4510a27
MR		 701 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
702 window.stride[0] = crtc->primary->fb->pitches[0];
de2ba664 703 window.base[0] = bo->paddr;
f34bc787
TR		 704
705 err = tegra_dc_setup_window(dc, 0, &window);
706 if (err < 0)
707 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 708
d8f4a9ed
TR		 709 return 0;
710}
d8f4a9ed 711
23fb4740
TR		 712static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
713 struct drm_framebuffer *old_fb)
714{
715 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 716
f4510a27 717 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
d8f4a9ed
TR		 718}
719
720static void tegra_crtc_prepare(struct drm_crtc *crtc)
721{
722 struct tegra_dc *dc = to_tegra_dc(crtc);
723 unsigned int syncpt;
724 unsigned long value;
725
726 /* hardware initialization */
ca48080a 727 reset_control_deassert(dc->rst);
d8f4a9ed
TR		 728 usleep_range(10000, 20000);
729
730 if (dc->pipe)
731 syncpt = SYNCPT_VBLANK1;
732 else
733 syncpt = SYNCPT_VBLANK0;
734
735 /* initialize display controller */
736 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
737 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
738
739 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
740 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
741
742 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
743 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
744 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
745
746 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
747 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
748 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
749
d8f4a9ed
TR		 750 /* initialize timer */
751 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
752 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
753 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
754
755 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
756 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
757 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
758
d8f4a9ed
TR		 759 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
760 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 761
762 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
763 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 764}
765
766static void tegra_crtc_commit(struct drm_crtc *crtc)
767{
768 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 769 unsigned long value;
770
3b9e71ea
TR		 771 value = GENERAL_UPDATE | WIN_A_UPDATE;
772 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 773
3b9e71ea 774 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 775 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 776
6e5ff998 777 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 778}
779
780static void tegra_crtc_load_lut(struct drm_crtc *crtc)
781{
782}
783
784static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 785 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 786 .mode_fixup = tegra_crtc_mode_fixup,
787 .mode_set = tegra_crtc_mode_set,
23fb4740 788 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 789 .prepare = tegra_crtc_prepare,
790 .commit = tegra_crtc_commit,
791 .load_lut = tegra_crtc_load_lut,
792};
793
6e5ff998 794static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 795{
796 struct tegra_dc *dc = data;
797 unsigned long status;
798
799 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
800 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
801
802 if (status & FRAME_END_INT) {
803 /*
804 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
805 */
806 }
807
808 if (status & VBLANK_INT) {
809 /*
810 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
811 */
812 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 813 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 814 }
815
816 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
817 /*
818 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
819 */
820 }
821
822 return IRQ_HANDLED;
823}
824
825static int tegra_dc_show_regs(struct seq_file *s, void *data)
826{
827 struct drm_info_node *node = s->private;
828 struct tegra_dc *dc = node->info_ent->data;
829
830#define DUMP_REG(name) \
831 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
832 tegra_dc_readl(dc, name))
833
834 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
835 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
836 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
837 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
838 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
839 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
840 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
841 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
842 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
843 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
844 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
845 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
846 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
847 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
848 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
849 DUMP_REG(DC_CMD_SIGNAL_RAISE);
850 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
851 DUMP_REG(DC_CMD_INT_STATUS);
852 DUMP_REG(DC_CMD_INT_MASK);
853 DUMP_REG(DC_CMD_INT_ENABLE);
854 DUMP_REG(DC_CMD_INT_TYPE);
855 DUMP_REG(DC_CMD_INT_POLARITY);
856 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
857 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
858 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
859 DUMP_REG(DC_CMD_STATE_ACCESS);
860 DUMP_REG(DC_CMD_STATE_CONTROL);
861 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
862 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
863 DUMP_REG(DC_COM_CRC_CONTROL);
864 DUMP_REG(DC_COM_CRC_CHECKSUM);
865 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
866 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
867 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
868 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
869 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
870 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
871 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
872 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
873 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
874 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
875 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
876 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
877 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
878 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
879 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
880 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
881 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
882 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
883 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
884 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
885 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
886 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
887 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
888 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
889 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
890 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
891 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
892 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
893 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
894 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
895 DUMP_REG(DC_COM_SPI_CONTROL);
896 DUMP_REG(DC_COM_SPI_START_BYTE);
897 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
898 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
899 DUMP_REG(DC_COM_HSPI_CS_DC);
900 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
901 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
902 DUMP_REG(DC_COM_GPIO_CTRL);
903 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
904 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
905 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
906 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
907 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
908 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
909 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
910 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
911 DUMP_REG(DC_DISP_REF_TO_SYNC);
912 DUMP_REG(DC_DISP_SYNC_WIDTH);
913 DUMP_REG(DC_DISP_BACK_PORCH);
914 DUMP_REG(DC_DISP_ACTIVE);
915 DUMP_REG(DC_DISP_FRONT_PORCH);
916 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
917 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
918 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
919 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
920 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
921 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
922 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
923 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
924 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
925 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
926 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
927 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
928 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
929 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
930 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
931 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
932 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
933 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
934 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
935 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
936 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
937 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
938 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
939 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
940 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
941 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
942 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
943 DUMP_REG(DC_DISP_M0_CONTROL);
944 DUMP_REG(DC_DISP_M1_CONTROL);
945 DUMP_REG(DC_DISP_DI_CONTROL);
946 DUMP_REG(DC_DISP_PP_CONTROL);
947 DUMP_REG(DC_DISP_PP_SELECT_A);
948 DUMP_REG(DC_DISP_PP_SELECT_B);
949 DUMP_REG(DC_DISP_PP_SELECT_C);
950 DUMP_REG(DC_DISP_PP_SELECT_D);
951 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
952 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
953 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
954 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
955 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
956 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
957 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
958 DUMP_REG(DC_DISP_BORDER_COLOR);
959 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
960 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
961 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
962 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
963 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
964 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
965 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
966 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
967 DUMP_REG(DC_DISP_CURSOR_POSITION);
968 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
969 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
970 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
971 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
972 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
973 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
974 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
975 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
976 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
977 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
978 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
979 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
980 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
981 DUMP_REG(DC_DISP_SD_CONTROL);
982 DUMP_REG(DC_DISP_SD_CSC_COEFF);
983 DUMP_REG(DC_DISP_SD_LUT(0));
984 DUMP_REG(DC_DISP_SD_LUT(1));
985 DUMP_REG(DC_DISP_SD_LUT(2));
986 DUMP_REG(DC_DISP_SD_LUT(3));
987 DUMP_REG(DC_DISP_SD_LUT(4));
988 DUMP_REG(DC_DISP_SD_LUT(5));
989 DUMP_REG(DC_DISP_SD_LUT(6));
990 DUMP_REG(DC_DISP_SD_LUT(7));
991 DUMP_REG(DC_DISP_SD_LUT(8));
992 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
993 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
994 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
995 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
996 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
997 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
998 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
999 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1000 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1001 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1002 DUMP_REG(DC_DISP_SD_BL_TF(0));
1003 DUMP_REG(DC_DISP_SD_BL_TF(1));
1004 DUMP_REG(DC_DISP_SD_BL_TF(2));
1005 DUMP_REG(DC_DISP_SD_BL_TF(3));
1006 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1007 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1008 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1009 DUMP_REG(DC_WIN_WIN_OPTIONS);
1010 DUMP_REG(DC_WIN_BYTE_SWAP);
1011 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1012 DUMP_REG(DC_WIN_COLOR_DEPTH);
1013 DUMP_REG(DC_WIN_POSITION);
1014 DUMP_REG(DC_WIN_SIZE);
1015 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1016 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1017 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1018 DUMP_REG(DC_WIN_DDA_INC);
1019 DUMP_REG(DC_WIN_LINE_STRIDE);
1020 DUMP_REG(DC_WIN_BUF_STRIDE);
1021 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1022 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1023 DUMP_REG(DC_WIN_DV_CONTROL);
1024 DUMP_REG(DC_WIN_BLEND_NOKEY);
1025 DUMP_REG(DC_WIN_BLEND_1WIN);
1026 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1027 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 1028 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 1029 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1030 DUMP_REG(DC_WINBUF_START_ADDR);
1031 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1032 DUMP_REG(DC_WINBUF_START_ADDR_U);
1033 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1034 DUMP_REG(DC_WINBUF_START_ADDR_V);
1035 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1036 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1037 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1038 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1039 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1040 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1041 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1042 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1043 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1044
1045#undef DUMP_REG
1046
1047 return 0;
1048}
1049
1050static struct drm_info_list debugfs_files[] = {
1051 { "regs", tegra_dc_show_regs, 0, NULL },
1052};
1053
1054static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1055{
1056 unsigned int i;
1057 char *name;
1058 int err;
1059
1060 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1061 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1062 kfree(name);
1063
1064 if (!dc->debugfs)
1065 return -ENOMEM;
1066
1067 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1068 GFP_KERNEL);
1069 if (!dc->debugfs_files) {
1070 err = -ENOMEM;
1071 goto remove;
1072 }
1073
1074 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1075 dc->debugfs_files[i].data = dc;
1076
1077 err = drm_debugfs_create_files(dc->debugfs_files,
1078 ARRAY_SIZE(debugfs_files),
1079 dc->debugfs, minor);
1080 if (err < 0)
1081 goto free;
1082
1083 dc->minor = minor;
1084
1085 return 0;
1086
1087free:
1088 kfree(dc->debugfs_files);
1089 dc->debugfs_files = NULL;
1090remove:
1091 debugfs_remove(dc->debugfs);
1092 dc->debugfs = NULL;
1093
1094 return err;
1095}
1096
1097static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1098{
1099 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1100 dc->minor);
1101 dc->minor = NULL;
1102
1103 kfree(dc->debugfs_files);
1104 dc->debugfs_files = NULL;
1105
1106 debugfs_remove(dc->debugfs);
1107 dc->debugfs = NULL;
1108
1109 return 0;
1110}
1111
53fa7f72 1112static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1113{
776dc384
TR		 1114 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1115 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1116 int err;
1117
776dc384 1118 drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs);
d8f4a9ed
TR		 1119 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1120 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1121
776dc384 1122 err = tegra_dc_rgb_init(tegra->drm, dc);
d8f4a9ed
TR		 1123 if (err < 0 && err != -ENODEV) {
1124 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1125 return err;
1126 }
1127
776dc384 1128 err = tegra_dc_add_planes(tegra->drm, dc);
f34bc787
TR		 1129 if (err < 0)
1130 return err;
1131
d8f4a9ed 1132 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
776dc384 1133 err = tegra_dc_debugfs_init(dc, tegra->drm->primary);
d8f4a9ed
TR		 1134 if (err < 0)
1135 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1136 }
1137
6e5ff998 1138 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1139 dev_name(dc->dev), dc);
1140 if (err < 0) {
1141 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1142 err);
1143 return err;
1144 }
1145
1146 return 0;
1147}
1148
53fa7f72 1149static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1150{
776dc384 1151 struct tegra_dc *dc = host1x_client_to_dc(client);
d8f4a9ed
TR		 1152 int err;
1153
1154 devm_free_irq(dc->dev, dc->irq, dc);
1155
1156 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1157 err = tegra_dc_debugfs_exit(dc);
1158 if (err < 0)
1159 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1160 }
1161
1162 err = tegra_dc_rgb_exit(dc);
1163 if (err) {
1164 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1165 return err;
1166 }
1167
1168 return 0;
1169}
1170
1171static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1172 .init = tegra_dc_init,
1173 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1174};
1175
8620fc62
TR		 1176static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1177 .supports_interlacing = false,
1178};
1179
1180static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1181 .supports_interlacing = false,
1182};
1183
1184static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1185 .supports_interlacing = true,
1186};
1187
1188static const struct of_device_id tegra_dc_of_match[] = {
1189 {
1190 .compatible = "nvidia,tegra124-dc",
1191 .data = &tegra124_dc_soc_info,
1192 }, {
1193 .compatible = "nvidia,tegra30-dc",
1194 .data = &tegra30_dc_soc_info,
1195 }, {
1196 .compatible = "nvidia,tegra20-dc",
1197 .data = &tegra20_dc_soc_info,
1198 }, {
1199 /* sentinel */
1200 }
1201};
1202
13411ddd
TR		 1203static int tegra_dc_parse_dt(struct tegra_dc *dc)
1204{
1205 struct device_node *np;
1206 u32 value = 0;
1207 int err;
1208
1209 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1210 if (err < 0) {
1211 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1212
1213 /*
1214 * If the nvidia,head property isn't present, try to find the
1215 * correct head number by looking up the position of this
1216 * display controller's node within the device tree. Assuming
1217 * that the nodes are ordered properly in the DTS file and
1218 * that the translation into a flattened device tree blob
1219 * preserves that ordering this will actually yield the right
1220 * head number.
1221 *
1222 * If those assumptions don't hold, this will still work for
1223 * cases where only a single display controller is used.
1224 */
1225 for_each_matching_node(np, tegra_dc_of_match) {
1226 if (np == dc->dev->of_node)
1227 break;
1228
1229 value++;
1230 }
1231 }
1232
1233 dc->pipe = value;
1234
1235 return 0;
1236}
1237
d8f4a9ed
TR		 1238static int tegra_dc_probe(struct platform_device *pdev)
1239{
8620fc62 1240 const struct of_device_id *id;
d8f4a9ed
TR		 1241 struct resource *regs;
1242 struct tegra_dc *dc;
1243 int err;
1244
1245 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1246 if (!dc)
1247 return -ENOMEM;
1248
8620fc62
TR		 1249 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1250 if (!id)
1251 return -ENODEV;
1252
6e5ff998 1253 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1254 INIT_LIST_HEAD(&dc->list);
1255 dc->dev = &pdev->dev;
8620fc62 1256 dc->soc = id->data;
d8f4a9ed 1257
13411ddd
TR		 1258 err = tegra_dc_parse_dt(dc);
1259 if (err < 0)
1260 return err;
1261
d8f4a9ed
TR		 1262 dc->clk = devm_clk_get(&pdev->dev, NULL);
1263 if (IS_ERR(dc->clk)) {
1264 dev_err(&pdev->dev, "failed to get clock\n");
1265 return PTR_ERR(dc->clk);
1266 }
1267
ca48080a
SW		 1268 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1269 if (IS_ERR(dc->rst)) {
1270 dev_err(&pdev->dev, "failed to get reset\n");
1271 return PTR_ERR(dc->rst);
1272 }
1273
d8f4a9ed
TR		 1274 err = clk_prepare_enable(dc->clk);
1275 if (err < 0)
1276 return err;
1277
1278 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1279 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1280 if (IS_ERR(dc->regs))
1281 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1282
1283 dc->irq = platform_get_irq(pdev, 0);
1284 if (dc->irq < 0) {
1285 dev_err(&pdev->dev, "failed to get IRQ\n");
1286 return -ENXIO;
1287 }
1288
776dc384
TR		 1289 INIT_LIST_HEAD(&dc->client.list);
1290 dc->client.ops = &dc_client_ops;
1291 dc->client.dev = &pdev->dev;
d8f4a9ed
TR		 1292
1293 err = tegra_dc_rgb_probe(dc);
1294 if (err < 0 && err != -ENODEV) {
1295 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1296 return err;
1297 }
1298
776dc384 1299 err = host1x_client_register(&dc->client);
d8f4a9ed
TR		 1300 if (err < 0) {
1301 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1302 err);
1303 return err;
1304 }
1305
1306 platform_set_drvdata(pdev, dc);
1307
1308 return 0;
1309}
1310
1311static int tegra_dc_remove(struct platform_device *pdev)
1312{
d8f4a9ed
TR		 1313 struct tegra_dc *dc = platform_get_drvdata(pdev);
1314 int err;
1315
776dc384 1316 err = host1x_client_unregister(&dc->client);
d8f4a9ed
TR		 1317 if (err < 0) {
1318 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1319 err);
1320 return err;
1321 }
1322
59d29c0e
TR		 1323 err = tegra_dc_rgb_remove(dc);
1324 if (err < 0) {
1325 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1326 return err;
1327 }
1328
d8f4a9ed
TR		 1329 clk_disable_unprepare(dc->clk);
1330
1331 return 0;
1332}
1333
d8f4a9ed
TR		 1334struct platform_driver tegra_dc_driver = {
1335 .driver = {
1336 .name = "tegra-dc",
1337 .owner = THIS_MODULE,
1338 .of_match_table = tegra_dc_of_match,
1339 },
1340 .probe = tegra_dc_probe,
1341 .remove = tegra_dc_remove,
1342};
Linux kernel - Deliverables
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