Commit | Line | Data |
---|---|---|
6b6b6042 TR |
1 | /* |
2 | * Copyright (C) 2013 NVIDIA Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/gpio.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/of_gpio.h> | |
0751bb5c JH |
15 | #include <linux/pinctrl/pinconf-generic.h> |
16 | #include <linux/pinctrl/pinctrl.h> | |
17 | #include <linux/pinctrl/pinmux.h> | |
6b6b6042 TR |
18 | #include <linux/platform_device.h> |
19 | #include <linux/reset.h> | |
20 | #include <linux/regulator/consumer.h> | |
2fff79d3 | 21 | #include <linux/workqueue.h> |
6b6b6042 TR |
22 | |
23 | #include <drm/drm_dp_helper.h> | |
24 | #include <drm/drm_panel.h> | |
25 | ||
26 | #include "dpaux.h" | |
27 | #include "drm.h" | |
28 | ||
29 | static DEFINE_MUTEX(dpaux_lock); | |
30 | static LIST_HEAD(dpaux_list); | |
31 | ||
32 | struct tegra_dpaux { | |
33 | struct drm_dp_aux aux; | |
34 | struct device *dev; | |
35 | ||
36 | void __iomem *regs; | |
37 | int irq; | |
38 | ||
39 | struct tegra_output *output; | |
40 | ||
41 | struct reset_control *rst; | |
42 | struct clk *clk_parent; | |
43 | struct clk *clk; | |
44 | ||
45 | struct regulator *vdd; | |
46 | ||
47 | struct completion complete; | |
2fff79d3 | 48 | struct work_struct work; |
6b6b6042 | 49 | struct list_head list; |
0751bb5c JH |
50 | |
51 | #ifdef CONFIG_GENERIC_PINCONF | |
52 | struct pinctrl_dev *pinctrl; | |
53 | struct pinctrl_desc desc; | |
54 | #endif | |
6b6b6042 TR |
55 | }; |
56 | ||
57 | static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux) | |
58 | { | |
59 | return container_of(aux, struct tegra_dpaux, aux); | |
60 | } | |
61 | ||
2fff79d3 TR |
62 | static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work) |
63 | { | |
64 | return container_of(work, struct tegra_dpaux, work); | |
65 | } | |
66 | ||
8a8005e3 TR |
67 | static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, |
68 | unsigned long offset) | |
6b6b6042 TR |
69 | { |
70 | return readl(dpaux->regs + (offset << 2)); | |
71 | } | |
72 | ||
73 | static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, | |
8a8005e3 | 74 | u32 value, unsigned long offset) |
6b6b6042 TR |
75 | { |
76 | writel(value, dpaux->regs + (offset << 2)); | |
77 | } | |
78 | ||
79 | static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, | |
80 | size_t size) | |
81 | { | |
6b6b6042 TR |
82 | size_t i, j; |
83 | ||
3c1dae0a TR |
84 | for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { |
85 | size_t num = min_t(size_t, size - i * 4, 4); | |
8a8005e3 | 86 | u32 value = 0; |
6b6b6042 TR |
87 | |
88 | for (j = 0; j < num; j++) | |
3c1dae0a | 89 | value |= buffer[i * 4 + j] << (j * 8); |
6b6b6042 | 90 | |
3c1dae0a | 91 | tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i)); |
6b6b6042 TR |
92 | } |
93 | } | |
94 | ||
95 | static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, | |
96 | size_t size) | |
97 | { | |
6b6b6042 TR |
98 | size_t i, j; |
99 | ||
3c1dae0a TR |
100 | for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { |
101 | size_t num = min_t(size_t, size - i * 4, 4); | |
8a8005e3 | 102 | u32 value; |
6b6b6042 | 103 | |
3c1dae0a | 104 | value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i)); |
6b6b6042 TR |
105 | |
106 | for (j = 0; j < num; j++) | |
3c1dae0a | 107 | buffer[i * 4 + j] = value >> (j * 8); |
6b6b6042 TR |
108 | } |
109 | } | |
110 | ||
111 | static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux, | |
112 | struct drm_dp_aux_msg *msg) | |
113 | { | |
6b6b6042 TR |
114 | unsigned long timeout = msecs_to_jiffies(250); |
115 | struct tegra_dpaux *dpaux = to_dpaux(aux); | |
116 | unsigned long status; | |
117 | ssize_t ret = 0; | |
1ca20305 | 118 | u32 value; |
6b6b6042 | 119 | |
1ca20305 TR |
120 | /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */ |
121 | if (msg->size > 16) | |
6b6b6042 TR |
122 | return -EINVAL; |
123 | ||
1ca20305 TR |
124 | /* |
125 | * Allow zero-sized messages only for I2C, in which case they specify | |
126 | * address-only transactions. | |
127 | */ | |
128 | if (msg->size < 1) { | |
129 | switch (msg->request & ~DP_AUX_I2C_MOT) { | |
f9934061 | 130 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
1ca20305 TR |
131 | case DP_AUX_I2C_WRITE: |
132 | case DP_AUX_I2C_READ: | |
133 | value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY; | |
134 | break; | |
135 | ||
136 | default: | |
137 | return -EINVAL; | |
138 | } | |
139 | } else { | |
140 | /* For non-zero-sized messages, set the CMDLEN field. */ | |
141 | value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1); | |
142 | } | |
6b6b6042 TR |
143 | |
144 | switch (msg->request & ~DP_AUX_I2C_MOT) { | |
145 | case DP_AUX_I2C_WRITE: | |
146 | if (msg->request & DP_AUX_I2C_MOT) | |
1ca20305 | 147 | value |= DPAUX_DP_AUXCTL_CMD_MOT_WR; |
6b6b6042 | 148 | else |
1ca20305 | 149 | value |= DPAUX_DP_AUXCTL_CMD_I2C_WR; |
6b6b6042 TR |
150 | |
151 | break; | |
152 | ||
153 | case DP_AUX_I2C_READ: | |
154 | if (msg->request & DP_AUX_I2C_MOT) | |
1ca20305 | 155 | value |= DPAUX_DP_AUXCTL_CMD_MOT_RD; |
6b6b6042 | 156 | else |
1ca20305 | 157 | value |= DPAUX_DP_AUXCTL_CMD_I2C_RD; |
6b6b6042 TR |
158 | |
159 | break; | |
160 | ||
2b712be7 | 161 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
6b6b6042 | 162 | if (msg->request & DP_AUX_I2C_MOT) |
1ca20305 | 163 | value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ; |
6b6b6042 | 164 | else |
1ca20305 | 165 | value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ; |
6b6b6042 TR |
166 | |
167 | break; | |
168 | ||
169 | case DP_AUX_NATIVE_WRITE: | |
1ca20305 | 170 | value |= DPAUX_DP_AUXCTL_CMD_AUX_WR; |
6b6b6042 TR |
171 | break; |
172 | ||
173 | case DP_AUX_NATIVE_READ: | |
1ca20305 | 174 | value |= DPAUX_DP_AUXCTL_CMD_AUX_RD; |
6b6b6042 TR |
175 | break; |
176 | ||
177 | default: | |
178 | return -EINVAL; | |
179 | } | |
180 | ||
1ca20305 | 181 | tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); |
6b6b6042 TR |
182 | tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); |
183 | ||
184 | if ((msg->request & DP_AUX_I2C_READ) == 0) { | |
185 | tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); | |
186 | ret = msg->size; | |
187 | } | |
188 | ||
189 | /* start transaction */ | |
190 | value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL); | |
191 | value |= DPAUX_DP_AUXCTL_TRANSACTREQ; | |
192 | tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); | |
193 | ||
194 | status = wait_for_completion_timeout(&dpaux->complete, timeout); | |
195 | if (!status) | |
196 | return -ETIMEDOUT; | |
197 | ||
198 | /* read status and clear errors */ | |
199 | value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); | |
200 | tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT); | |
201 | ||
202 | if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR) | |
203 | return -ETIMEDOUT; | |
204 | ||
205 | if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) || | |
206 | (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) || | |
207 | (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR)) | |
208 | return -EIO; | |
209 | ||
210 | switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) { | |
211 | case 0x00: | |
212 | msg->reply = DP_AUX_NATIVE_REPLY_ACK; | |
213 | break; | |
214 | ||
215 | case 0x01: | |
216 | msg->reply = DP_AUX_NATIVE_REPLY_NACK; | |
217 | break; | |
218 | ||
219 | case 0x02: | |
220 | msg->reply = DP_AUX_NATIVE_REPLY_DEFER; | |
221 | break; | |
222 | ||
223 | case 0x04: | |
224 | msg->reply = DP_AUX_I2C_REPLY_NACK; | |
225 | break; | |
226 | ||
227 | case 0x08: | |
228 | msg->reply = DP_AUX_I2C_REPLY_DEFER; | |
229 | break; | |
230 | } | |
231 | ||
1ca20305 | 232 | if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) { |
6b6b6042 TR |
233 | if (msg->request & DP_AUX_I2C_READ) { |
234 | size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK; | |
235 | ||
236 | if (WARN_ON(count != msg->size)) | |
237 | count = min_t(size_t, count, msg->size); | |
238 | ||
239 | tegra_dpaux_read_fifo(dpaux, msg->buffer, count); | |
240 | ret = count; | |
241 | } | |
242 | } | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
2fff79d3 TR |
247 | static void tegra_dpaux_hotplug(struct work_struct *work) |
248 | { | |
249 | struct tegra_dpaux *dpaux = work_to_dpaux(work); | |
250 | ||
251 | if (dpaux->output) | |
252 | drm_helper_hpd_irq_event(dpaux->output->connector.dev); | |
253 | } | |
254 | ||
6b6b6042 TR |
255 | static irqreturn_t tegra_dpaux_irq(int irq, void *data) |
256 | { | |
257 | struct tegra_dpaux *dpaux = data; | |
258 | irqreturn_t ret = IRQ_HANDLED; | |
8a8005e3 | 259 | u32 value; |
6b6b6042 TR |
260 | |
261 | /* clear interrupts */ | |
262 | value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); | |
263 | tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); | |
264 | ||
2fff79d3 TR |
265 | if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT)) |
266 | schedule_work(&dpaux->work); | |
6b6b6042 TR |
267 | |
268 | if (value & DPAUX_INTR_IRQ_EVENT) { | |
269 | /* TODO: handle this */ | |
270 | } | |
271 | ||
272 | if (value & DPAUX_INTR_AUX_DONE) | |
273 | complete(&dpaux->complete); | |
274 | ||
275 | return ret; | |
276 | } | |
277 | ||
0751bb5c JH |
278 | enum tegra_dpaux_functions { |
279 | DPAUX_PADCTL_FUNC_AUX, | |
280 | DPAUX_PADCTL_FUNC_I2C, | |
281 | DPAUX_PADCTL_FUNC_OFF, | |
282 | }; | |
283 | ||
9d0e09c1 JH |
284 | static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux) |
285 | { | |
286 | u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); | |
287 | ||
288 | value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; | |
289 | ||
290 | tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); | |
291 | } | |
292 | ||
293 | static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux) | |
294 | { | |
295 | u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); | |
296 | ||
297 | value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; | |
298 | ||
299 | tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); | |
300 | } | |
301 | ||
302 | static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function) | |
303 | { | |
304 | u32 value; | |
305 | ||
306 | switch (function) { | |
0751bb5c | 307 | case DPAUX_PADCTL_FUNC_AUX: |
9d0e09c1 JH |
308 | value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) | |
309 | DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) | | |
310 | DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) | | |
311 | DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV | | |
312 | DPAUX_HYBRID_PADCTL_MODE_AUX; | |
313 | break; | |
314 | ||
0751bb5c | 315 | case DPAUX_PADCTL_FUNC_I2C: |
9d0e09c1 JH |
316 | value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV | |
317 | DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV | | |
318 | DPAUX_HYBRID_PADCTL_MODE_I2C; | |
319 | break; | |
320 | ||
0751bb5c JH |
321 | case DPAUX_PADCTL_FUNC_OFF: |
322 | tegra_dpaux_pad_power_down(dpaux); | |
323 | return 0; | |
324 | ||
9d0e09c1 JH |
325 | default: |
326 | return -ENOTSUPP; | |
327 | } | |
328 | ||
329 | tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); | |
330 | tegra_dpaux_pad_power_up(dpaux); | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
0751bb5c JH |
335 | #ifdef CONFIG_GENERIC_PINCONF |
336 | static const struct pinctrl_pin_desc tegra_dpaux_pins[] = { | |
337 | PINCTRL_PIN(0, "DP_AUX_CHx_P"), | |
338 | PINCTRL_PIN(1, "DP_AUX_CHx_N"), | |
339 | }; | |
340 | ||
341 | static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 }; | |
342 | ||
343 | static const char * const tegra_dpaux_groups[] = { | |
344 | "dpaux-io", | |
345 | }; | |
346 | ||
347 | static const char * const tegra_dpaux_functions[] = { | |
348 | "aux", | |
349 | "i2c", | |
350 | "off", | |
351 | }; | |
352 | ||
353 | static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl) | |
354 | { | |
355 | return ARRAY_SIZE(tegra_dpaux_groups); | |
356 | } | |
357 | ||
358 | static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl, | |
359 | unsigned int group) | |
360 | { | |
361 | return tegra_dpaux_groups[group]; | |
362 | } | |
363 | ||
364 | static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl, | |
365 | unsigned group, const unsigned **pins, | |
366 | unsigned *num_pins) | |
367 | { | |
368 | *pins = tegra_dpaux_pin_numbers; | |
369 | *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = { | |
375 | .get_groups_count = tegra_dpaux_get_groups_count, | |
376 | .get_group_name = tegra_dpaux_get_group_name, | |
377 | .get_group_pins = tegra_dpaux_get_group_pins, | |
378 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
379 | .dt_free_map = pinconf_generic_dt_free_map, | |
380 | }; | |
381 | ||
382 | static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl) | |
383 | { | |
384 | return ARRAY_SIZE(tegra_dpaux_functions); | |
385 | } | |
386 | ||
387 | static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl, | |
388 | unsigned int function) | |
389 | { | |
390 | return tegra_dpaux_functions[function]; | |
391 | } | |
392 | ||
393 | static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl, | |
394 | unsigned int function, | |
395 | const char * const **groups, | |
396 | unsigned * const num_groups) | |
397 | { | |
398 | *num_groups = ARRAY_SIZE(tegra_dpaux_groups); | |
399 | *groups = tegra_dpaux_groups; | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
404 | static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl, | |
405 | unsigned int function, unsigned int group) | |
406 | { | |
407 | struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl); | |
408 | ||
409 | return tegra_dpaux_pad_config(dpaux, function); | |
410 | } | |
411 | ||
412 | static const struct pinmux_ops tegra_dpaux_pinmux_ops = { | |
413 | .get_functions_count = tegra_dpaux_get_functions_count, | |
414 | .get_function_name = tegra_dpaux_get_function_name, | |
415 | .get_function_groups = tegra_dpaux_get_function_groups, | |
416 | .set_mux = tegra_dpaux_set_mux, | |
417 | }; | |
418 | #endif | |
419 | ||
6b6b6042 TR |
420 | static int tegra_dpaux_probe(struct platform_device *pdev) |
421 | { | |
422 | struct tegra_dpaux *dpaux; | |
423 | struct resource *regs; | |
8a8005e3 | 424 | u32 value; |
6b6b6042 TR |
425 | int err; |
426 | ||
427 | dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); | |
428 | if (!dpaux) | |
429 | return -ENOMEM; | |
430 | ||
2fff79d3 | 431 | INIT_WORK(&dpaux->work, tegra_dpaux_hotplug); |
6b6b6042 TR |
432 | init_completion(&dpaux->complete); |
433 | INIT_LIST_HEAD(&dpaux->list); | |
434 | dpaux->dev = &pdev->dev; | |
435 | ||
436 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
437 | dpaux->regs = devm_ioremap_resource(&pdev->dev, regs); | |
438 | if (IS_ERR(dpaux->regs)) | |
439 | return PTR_ERR(dpaux->regs); | |
440 | ||
441 | dpaux->irq = platform_get_irq(pdev, 0); | |
442 | if (dpaux->irq < 0) { | |
443 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
444 | return -ENXIO; | |
445 | } | |
446 | ||
9b99044a JH |
447 | if (!pdev->dev.pm_domain) { |
448 | dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); | |
449 | if (IS_ERR(dpaux->rst)) { | |
450 | dev_err(&pdev->dev, | |
451 | "failed to get reset control: %ld\n", | |
452 | PTR_ERR(dpaux->rst)); | |
453 | return PTR_ERR(dpaux->rst); | |
454 | } | |
08f580ef | 455 | } |
6b6b6042 TR |
456 | |
457 | dpaux->clk = devm_clk_get(&pdev->dev, NULL); | |
08f580ef TR |
458 | if (IS_ERR(dpaux->clk)) { |
459 | dev_err(&pdev->dev, "failed to get module clock: %ld\n", | |
460 | PTR_ERR(dpaux->clk)); | |
6b6b6042 | 461 | return PTR_ERR(dpaux->clk); |
08f580ef | 462 | } |
6b6b6042 TR |
463 | |
464 | err = clk_prepare_enable(dpaux->clk); | |
08f580ef TR |
465 | if (err < 0) { |
466 | dev_err(&pdev->dev, "failed to enable module clock: %d\n", | |
467 | err); | |
6b6b6042 | 468 | return err; |
08f580ef | 469 | } |
6b6b6042 | 470 | |
9b99044a JH |
471 | if (dpaux->rst) |
472 | reset_control_deassert(dpaux->rst); | |
6b6b6042 TR |
473 | |
474 | dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); | |
08f580ef TR |
475 | if (IS_ERR(dpaux->clk_parent)) { |
476 | dev_err(&pdev->dev, "failed to get parent clock: %ld\n", | |
477 | PTR_ERR(dpaux->clk_parent)); | |
bcbd63df JH |
478 | err = PTR_ERR(dpaux->clk_parent); |
479 | goto assert_reset; | |
08f580ef | 480 | } |
6b6b6042 TR |
481 | |
482 | err = clk_prepare_enable(dpaux->clk_parent); | |
08f580ef TR |
483 | if (err < 0) { |
484 | dev_err(&pdev->dev, "failed to enable parent clock: %d\n", | |
485 | err); | |
bcbd63df | 486 | goto assert_reset; |
08f580ef | 487 | } |
6b6b6042 TR |
488 | |
489 | err = clk_set_rate(dpaux->clk_parent, 270000000); | |
490 | if (err < 0) { | |
491 | dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", | |
492 | err); | |
bcbd63df | 493 | goto disable_parent_clk; |
6b6b6042 TR |
494 | } |
495 | ||
496 | dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd"); | |
08f580ef TR |
497 | if (IS_ERR(dpaux->vdd)) { |
498 | dev_err(&pdev->dev, "failed to get VDD supply: %ld\n", | |
499 | PTR_ERR(dpaux->vdd)); | |
bcbd63df JH |
500 | err = PTR_ERR(dpaux->vdd); |
501 | goto disable_parent_clk; | |
08f580ef | 502 | } |
6b6b6042 TR |
503 | |
504 | err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, | |
505 | dev_name(dpaux->dev), dpaux); | |
506 | if (err < 0) { | |
507 | dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", | |
508 | dpaux->irq, err); | |
bcbd63df | 509 | goto disable_parent_clk; |
6b6b6042 TR |
510 | } |
511 | ||
9e532b3a TR |
512 | disable_irq(dpaux->irq); |
513 | ||
6b6b6042 TR |
514 | dpaux->aux.transfer = tegra_dpaux_transfer; |
515 | dpaux->aux.dev = &pdev->dev; | |
516 | ||
4f71d0cb | 517 | err = drm_dp_aux_register(&dpaux->aux); |
6b6b6042 | 518 | if (err < 0) |
bcbd63df | 519 | goto disable_parent_clk; |
6b6b6042 | 520 | |
3227166c TR |
521 | /* |
522 | * Assume that by default the DPAUX/I2C pads will be used for HDMI, | |
523 | * so power them up and configure them in I2C mode. | |
524 | * | |
525 | * The DPAUX code paths reconfigure the pads in AUX mode, but there | |
526 | * is no possibility to perform the I2C mode configuration in the | |
527 | * HDMI path. | |
528 | */ | |
9d0e09c1 JH |
529 | err = tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_I2C); |
530 | if (err < 0) | |
531 | return err; | |
3227166c | 532 | |
0751bb5c JH |
533 | #ifdef CONFIG_GENERIC_PINCONF |
534 | dpaux->desc.name = dev_name(&pdev->dev); | |
535 | dpaux->desc.pins = tegra_dpaux_pins; | |
536 | dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins); | |
537 | dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops; | |
538 | dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops; | |
539 | dpaux->desc.owner = THIS_MODULE; | |
540 | ||
541 | dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux); | |
542 | if (!dpaux->pinctrl) { | |
543 | dev_err(&pdev->dev, "failed to register pincontrol\n"); | |
544 | return -ENODEV; | |
545 | } | |
546 | #endif | |
6b6b6042 TR |
547 | /* enable and clear all interrupts */ |
548 | value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT | | |
549 | DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT; | |
550 | tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX); | |
551 | tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); | |
552 | ||
553 | mutex_lock(&dpaux_lock); | |
554 | list_add_tail(&dpaux->list, &dpaux_list); | |
555 | mutex_unlock(&dpaux_lock); | |
556 | ||
557 | platform_set_drvdata(pdev, dpaux); | |
558 | ||
559 | return 0; | |
bcbd63df JH |
560 | |
561 | disable_parent_clk: | |
562 | clk_disable_unprepare(dpaux->clk_parent); | |
563 | assert_reset: | |
9b99044a JH |
564 | if (dpaux->rst) |
565 | reset_control_assert(dpaux->rst); | |
566 | ||
bcbd63df JH |
567 | clk_disable_unprepare(dpaux->clk); |
568 | ||
569 | return err; | |
6b6b6042 TR |
570 | } |
571 | ||
572 | static int tegra_dpaux_remove(struct platform_device *pdev) | |
573 | { | |
574 | struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); | |
3227166c TR |
575 | |
576 | /* make sure pads are powered down when not in use */ | |
9d0e09c1 | 577 | tegra_dpaux_pad_power_down(dpaux); |
6b6b6042 | 578 | |
4f71d0cb | 579 | drm_dp_aux_unregister(&dpaux->aux); |
6b6b6042 TR |
580 | |
581 | mutex_lock(&dpaux_lock); | |
582 | list_del(&dpaux->list); | |
583 | mutex_unlock(&dpaux_lock); | |
584 | ||
2fff79d3 TR |
585 | cancel_work_sync(&dpaux->work); |
586 | ||
6b6b6042 | 587 | clk_disable_unprepare(dpaux->clk_parent); |
9b99044a JH |
588 | |
589 | if (dpaux->rst) | |
590 | reset_control_assert(dpaux->rst); | |
591 | ||
6b6b6042 TR |
592 | clk_disable_unprepare(dpaux->clk); |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static const struct of_device_id tegra_dpaux_of_match[] = { | |
3227166c | 598 | { .compatible = "nvidia,tegra210-dpaux", }, |
6b6b6042 TR |
599 | { .compatible = "nvidia,tegra124-dpaux", }, |
600 | { }, | |
601 | }; | |
ef70728c | 602 | MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match); |
6b6b6042 TR |
603 | |
604 | struct platform_driver tegra_dpaux_driver = { | |
605 | .driver = { | |
606 | .name = "tegra-dpaux", | |
607 | .of_match_table = tegra_dpaux_of_match, | |
608 | }, | |
609 | .probe = tegra_dpaux_probe, | |
610 | .remove = tegra_dpaux_remove, | |
611 | }; | |
612 | ||
9542c237 | 613 | struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np) |
6b6b6042 TR |
614 | { |
615 | struct tegra_dpaux *dpaux; | |
616 | ||
617 | mutex_lock(&dpaux_lock); | |
618 | ||
619 | list_for_each_entry(dpaux, &dpaux_list, list) | |
620 | if (np == dpaux->dev->of_node) { | |
621 | mutex_unlock(&dpaux_lock); | |
9542c237 | 622 | return &dpaux->aux; |
6b6b6042 TR |
623 | } |
624 | ||
625 | mutex_unlock(&dpaux_lock); | |
626 | ||
627 | return NULL; | |
628 | } | |
629 | ||
9542c237 | 630 | int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output) |
6b6b6042 | 631 | { |
9542c237 | 632 | struct tegra_dpaux *dpaux = to_dpaux(aux); |
6b6b6042 TR |
633 | unsigned long timeout; |
634 | int err; | |
635 | ||
7c463386 | 636 | output->connector.polled = DRM_CONNECTOR_POLL_HPD; |
6b6b6042 TR |
637 | dpaux->output = output; |
638 | ||
639 | err = regulator_enable(dpaux->vdd); | |
640 | if (err < 0) | |
641 | return err; | |
642 | ||
643 | timeout = jiffies + msecs_to_jiffies(250); | |
644 | ||
645 | while (time_before(jiffies, timeout)) { | |
646 | enum drm_connector_status status; | |
647 | ||
9542c237 | 648 | status = drm_dp_aux_detect(aux); |
9e532b3a TR |
649 | if (status == connector_status_connected) { |
650 | enable_irq(dpaux->irq); | |
6b6b6042 | 651 | return 0; |
9e532b3a | 652 | } |
6b6b6042 TR |
653 | |
654 | usleep_range(1000, 2000); | |
655 | } | |
656 | ||
657 | return -ETIMEDOUT; | |
658 | } | |
659 | ||
9542c237 | 660 | int drm_dp_aux_detach(struct drm_dp_aux *aux) |
6b6b6042 | 661 | { |
9542c237 | 662 | struct tegra_dpaux *dpaux = to_dpaux(aux); |
6b6b6042 TR |
663 | unsigned long timeout; |
664 | int err; | |
665 | ||
9e532b3a TR |
666 | disable_irq(dpaux->irq); |
667 | ||
6b6b6042 TR |
668 | err = regulator_disable(dpaux->vdd); |
669 | if (err < 0) | |
670 | return err; | |
671 | ||
672 | timeout = jiffies + msecs_to_jiffies(250); | |
673 | ||
674 | while (time_before(jiffies, timeout)) { | |
675 | enum drm_connector_status status; | |
676 | ||
9542c237 | 677 | status = drm_dp_aux_detect(aux); |
6b6b6042 TR |
678 | if (status == connector_status_disconnected) { |
679 | dpaux->output = NULL; | |
680 | return 0; | |
681 | } | |
682 | ||
683 | usleep_range(1000, 2000); | |
684 | } | |
685 | ||
686 | return -ETIMEDOUT; | |
687 | } | |
688 | ||
9542c237 | 689 | enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux) |
6b6b6042 | 690 | { |
9542c237 | 691 | struct tegra_dpaux *dpaux = to_dpaux(aux); |
8a8005e3 | 692 | u32 value; |
6b6b6042 TR |
693 | |
694 | value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); | |
695 | ||
696 | if (value & DPAUX_DP_AUXSTAT_HPD_STATUS) | |
697 | return connector_status_connected; | |
698 | ||
699 | return connector_status_disconnected; | |
700 | } | |
701 | ||
9542c237 | 702 | int drm_dp_aux_enable(struct drm_dp_aux *aux) |
6b6b6042 | 703 | { |
9542c237 | 704 | struct tegra_dpaux *dpaux = to_dpaux(aux); |
6b6b6042 | 705 | |
0751bb5c | 706 | return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX); |
6b6b6042 TR |
707 | } |
708 | ||
9542c237 | 709 | int drm_dp_aux_disable(struct drm_dp_aux *aux) |
6b6b6042 | 710 | { |
9542c237 | 711 | struct tegra_dpaux *dpaux = to_dpaux(aux); |
6b6b6042 | 712 | |
9d0e09c1 | 713 | tegra_dpaux_pad_power_down(dpaux); |
6b6b6042 TR |
714 | |
715 | return 0; | |
716 | } | |
717 | ||
9542c237 | 718 | int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding) |
6b6b6042 TR |
719 | { |
720 | int err; | |
721 | ||
9542c237 | 722 | err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, |
6b6b6042 TR |
723 | encoding); |
724 | if (err < 0) | |
725 | return err; | |
726 | ||
727 | return 0; | |
728 | } | |
729 | ||
9542c237 TR |
730 | int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, |
731 | u8 pattern) | |
6b6b6042 TR |
732 | { |
733 | u8 tp = pattern & DP_TRAINING_PATTERN_MASK; | |
734 | u8 status[DP_LINK_STATUS_SIZE], values[4]; | |
735 | unsigned int i; | |
736 | int err; | |
737 | ||
9542c237 | 738 | err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern); |
6b6b6042 TR |
739 | if (err < 0) |
740 | return err; | |
741 | ||
742 | if (tp == DP_TRAINING_PATTERN_DISABLE) | |
743 | return 0; | |
744 | ||
745 | for (i = 0; i < link->num_lanes; i++) | |
746 | values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | | |
eeb82a5c | 747 | DP_TRAIN_PRE_EMPH_LEVEL_0 | |
6b6b6042 | 748 | DP_TRAIN_MAX_SWING_REACHED | |
eeb82a5c | 749 | DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
6b6b6042 | 750 | |
9542c237 | 751 | err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, |
6b6b6042 TR |
752 | link->num_lanes); |
753 | if (err < 0) | |
754 | return err; | |
755 | ||
756 | usleep_range(500, 1000); | |
757 | ||
9542c237 | 758 | err = drm_dp_dpcd_read_link_status(aux, status); |
6b6b6042 TR |
759 | if (err < 0) |
760 | return err; | |
761 | ||
762 | switch (tp) { | |
763 | case DP_TRAINING_PATTERN_1: | |
764 | if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) | |
765 | return -EAGAIN; | |
766 | ||
767 | break; | |
768 | ||
769 | case DP_TRAINING_PATTERN_2: | |
770 | if (!drm_dp_channel_eq_ok(status, link->num_lanes)) | |
771 | return -EAGAIN; | |
772 | ||
773 | break; | |
774 | ||
775 | default: | |
9542c237 | 776 | dev_err(aux->dev, "unsupported training pattern %u\n", tp); |
6b6b6042 TR |
777 | return -EINVAL; |
778 | } | |
779 | ||
9542c237 | 780 | err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0); |
6b6b6042 TR |
781 | if (err < 0) |
782 | return err; | |
783 | ||
784 | return 0; | |
785 | } |