projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 6b6b6042 TR |
1 | /* |
| 2 | * Copyright (C) 2013 NVIDIA Corporation | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef DRM_TEGRA_DPAUX_H | |
| 10 | #define DRM_TEGRA_DPAUX_H | |
| 11 | ||
| 12 | #define DPAUX_CTXSW 0x00 | |
| 13 | ||
| 14 | #define DPAUX_INTR_EN_AUX 0x01 | |
| 15 | #define DPAUX_INTR_AUX 0x05 | |
| 16 | #define DPAUX_INTR_AUX_DONE (1 << 3) | |
| 17 | #define DPAUX_INTR_IRQ_EVENT (1 << 2) | |
| 18 | #define DPAUX_INTR_UNPLUG_EVENT (1 << 1) | |
| 19 | #define DPAUX_INTR_PLUG_EVENT (1 << 0) | |
| 20 | ||
| 21 | #define DPAUX_DP_AUXDATA_WRITE(x) (0x09 + ((x) << 2)) | |
| 22 | #define DPAUX_DP_AUXDATA_READ(x) (0x19 + ((x) << 2)) | |
| 23 | #define DPAUX_DP_AUXADDR 0x29 | |
| 24 | ||
| 25 | #define DPAUX_DP_AUXCTL 0x2d | |
| 26 | #define DPAUX_DP_AUXCTL_TRANSACTREQ (1 << 16) | |
| 27 | #define DPAUX_DP_AUXCTL_CMD_AUX_RD (9 << 12) | |
| 28 | #define DPAUX_DP_AUXCTL_CMD_AUX_WR (8 << 12) | |
| 29 | #define DPAUX_DP_AUXCTL_CMD_MOT_RQ (6 << 12) | |
| 30 | #define DPAUX_DP_AUXCTL_CMD_MOT_RD (5 << 12) | |
| 31 | #define DPAUX_DP_AUXCTL_CMD_MOT_WR (4 << 12) | |
| 32 | #define DPAUX_DP_AUXCTL_CMD_I2C_RQ (2 << 12) | |
| 33 | #define DPAUX_DP_AUXCTL_CMD_I2C_RD (1 << 12) | |
| 34 | #define DPAUX_DP_AUXCTL_CMD_I2C_WR (0 << 12) | |
| 1ca20305 | 35 | #define DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY (1 << 8) |
| 6b6b6042 TR |
36 | #define DPAUX_DP_AUXCTL_CMDLEN(x) ((x) & 0xff) |
| 37 | ||
| 38 | #define DPAUX_DP_AUXSTAT 0x31 | |
| 39 | #define DPAUX_DP_AUXSTAT_HPD_STATUS (1 << 28) | |
| 40 | #define DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK (0xf0000) | |
| 41 | #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR (1 << 11) | |
| 42 | #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR (1 << 10) | |
| 43 | #define DPAUX_DP_AUXSTAT_RX_ERROR (1 << 9) | |
| 44 | #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR (1 << 8) | |
| 45 | #define DPAUX_DP_AUXSTAT_REPLY_MASK (0xff) | |
| 46 | ||
| 47 | #define DPAUX_DP_AUX_SINKSTAT_LO 0x35 | |
| 48 | #define DPAUX_DP_AUX_SINKSTAT_HI 0x39 | |
| 49 | ||
| 50 | #define DPAUX_HPD_CONFIG 0x3d | |
| 51 | #define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME(x) (((x) & 0xffff) << 16) | |
| 52 | #define DPAUX_HPD_CONFIG_PLUG_MIN_TIME(x) ((x) & 0xffff) | |
| 53 | ||
| 54 | #define DPAUX_HPD_IRQ_CONFIG 0x41 | |
| 55 | #define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME(x) ((x) & 0xffff) | |
| 56 | ||
| 57 | #define DPAUX_DP_AUX_CONFIG 0x45 | |
| 58 | ||
| 59 | #define DPAUX_HYBRID_PADCTL 0x49 | |
| 3227166c TR |
60 | #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV (1 << 15) |
| 61 | #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV (1 << 14) | |
| 6b6b6042 TR |
62 | #define DPAUX_HYBRID_PADCTL_AUX_CMH(x) (((x) & 0x3) << 12) |
| 63 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ(x) (((x) & 0x7) << 8) | |
| 64 | #define DPAUX_HYBRID_PADCTL_AUX_DRVI(x) (((x) & 0x3f) << 2) | |
| 65 | #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV (1 << 1) | |
| 66 | #define DPAUX_HYBRID_PADCTL_MODE_I2C (1 << 0) | |
| 67 | #define DPAUX_HYBRID_PADCTL_MODE_AUX (0 << 0) | |
| 68 | ||
| 69 | #define DPAUX_HYBRID_SPARE 0x4d | |
| 70 | #define DPAUX_HYBRID_SPARE_PAD_POWER_DOWN (1 << 0) | |
| 71 | ||
| 72 | #define DPAUX_SCRATCH_REG0 0x51 | |
| 73 | #define DPAUX_SCRATCH_REG1 0x55 | |
| 74 | #define DPAUX_SCRATCH_REG2 0x59 | |
| 75 | ||
| 76 | #endif |