Commit | Line | Data |
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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
4231c6b0 TB |
10 | #ifndef HOST1X_DRM_H |
11 | #define HOST1X_DRM_H 1 | |
d8f4a9ed | 12 | |
e1e90644 TR |
13 | #include <uapi/drm/tegra_drm.h> |
14 | #include <linux/host1x.h> | |
15 | ||
d8f4a9ed TR |
16 | #include <drm/drmP.h> |
17 | #include <drm/drm_crtc_helper.h> | |
18 | #include <drm/drm_edid.h> | |
19 | #include <drm/drm_fb_helper.h> | |
d8f4a9ed TR |
20 | #include <drm/drm_fixed.h> |
21 | ||
c134f019 TR |
22 | #include "gem.h" |
23 | ||
ca48080a SW |
24 | struct reset_control; |
25 | ||
de2ba664 AM |
26 | struct tegra_fb { |
27 | struct drm_framebuffer base; | |
28 | struct tegra_bo **planes; | |
29 | unsigned int num_planes; | |
30 | }; | |
31 | ||
60c2f709 | 32 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
de2ba664 AM |
33 | struct tegra_fbdev { |
34 | struct drm_fb_helper base; | |
35 | struct tegra_fb *fb; | |
36 | }; | |
60c2f709 | 37 | #endif |
de2ba664 | 38 | |
386a2a71 | 39 | struct tegra_drm { |
d8f4a9ed | 40 | struct drm_device *drm; |
d8f4a9ed TR |
41 | |
42 | struct mutex clients_lock; | |
43 | struct list_head clients; | |
44 | ||
60c2f709 | 45 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
de2ba664 | 46 | struct tegra_fbdev *fbdev; |
60c2f709 | 47 | #endif |
d1f3e1e0 TR |
48 | |
49 | unsigned int pitch_align; | |
d8f4a9ed TR |
50 | }; |
51 | ||
53fa7f72 | 52 | struct tegra_drm_client; |
d8f4a9ed | 53 | |
c88c3630 | 54 | struct tegra_drm_context { |
53fa7f72 | 55 | struct tegra_drm_client *client; |
d43f81cb TB |
56 | struct host1x_channel *channel; |
57 | struct list_head list; | |
58 | }; | |
59 | ||
53fa7f72 TR |
60 | struct tegra_drm_client_ops { |
61 | int (*open_channel)(struct tegra_drm_client *client, | |
c88c3630 TR |
62 | struct tegra_drm_context *context); |
63 | void (*close_channel)(struct tegra_drm_context *context); | |
c40f0f1a | 64 | int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); |
c88c3630 | 65 | int (*submit)(struct tegra_drm_context *context, |
d43f81cb TB |
66 | struct drm_tegra_submit *args, struct drm_device *drm, |
67 | struct drm_file *file); | |
68 | }; | |
69 | ||
c40f0f1a TR |
70 | int tegra_drm_submit(struct tegra_drm_context *context, |
71 | struct drm_tegra_submit *args, struct drm_device *drm, | |
72 | struct drm_file *file); | |
73 | ||
53fa7f72 TR |
74 | struct tegra_drm_client { |
75 | struct host1x_client base; | |
776dc384 | 76 | struct list_head list; |
d43f81cb | 77 | |
53fa7f72 | 78 | const struct tegra_drm_client_ops *ops; |
d8f4a9ed TR |
79 | }; |
80 | ||
53fa7f72 | 81 | static inline struct tegra_drm_client * |
776dc384 | 82 | host1x_to_drm_client(struct host1x_client *client) |
53fa7f72 TR |
83 | { |
84 | return container_of(client, struct tegra_drm_client, base); | |
85 | } | |
86 | ||
688c59af TR |
87 | int tegra_drm_register_client(struct tegra_drm *tegra, |
88 | struct tegra_drm_client *client); | |
89 | int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
90 | struct tegra_drm_client *client); | |
776dc384 | 91 | |
688c59af TR |
92 | int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
93 | int tegra_drm_exit(struct tegra_drm *tegra); | |
d8f4a9ed | 94 | |
8620fc62 | 95 | struct tegra_dc_soc_info; |
d8f4a9ed TR |
96 | struct tegra_output; |
97 | ||
98 | struct tegra_dc { | |
776dc384 | 99 | struct host1x_client client; |
d8f4a9ed | 100 | struct device *dev; |
d18d3033 | 101 | spinlock_t lock; |
d8f4a9ed TR |
102 | |
103 | struct drm_crtc base; | |
104 | int pipe; | |
105 | ||
106 | struct clk *clk; | |
ca48080a | 107 | struct reset_control *rst; |
d8f4a9ed TR |
108 | void __iomem *regs; |
109 | int irq; | |
110 | ||
111 | struct tegra_output *rgb; | |
112 | ||
113 | struct list_head list; | |
114 | ||
115 | struct drm_info_list *debugfs_files; | |
116 | struct drm_minor *minor; | |
117 | struct dentry *debugfs; | |
3c03c46a TR |
118 | |
119 | /* page-flip handling */ | |
120 | struct drm_pending_vblank_event *event; | |
8620fc62 TR |
121 | |
122 | const struct tegra_dc_soc_info *soc; | |
d8f4a9ed TR |
123 | }; |
124 | ||
53fa7f72 | 125 | static inline struct tegra_dc * |
776dc384 | 126 | host1x_client_to_dc(struct host1x_client *client) |
d8f4a9ed TR |
127 | { |
128 | return container_of(client, struct tegra_dc, client); | |
129 | } | |
130 | ||
131 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) | |
132 | { | |
37826519 | 133 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; |
d8f4a9ed TR |
134 | } |
135 | ||
136 | static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, | |
137 | unsigned long reg) | |
138 | { | |
139 | writel(value, dc->regs + (reg << 2)); | |
140 | } | |
141 | ||
142 | static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, | |
143 | unsigned long reg) | |
144 | { | |
145 | return readl(dc->regs + (reg << 2)); | |
146 | } | |
147 | ||
f34bc787 TR |
148 | struct tegra_dc_window { |
149 | struct { | |
150 | unsigned int x; | |
151 | unsigned int y; | |
152 | unsigned int w; | |
153 | unsigned int h; | |
154 | } src; | |
155 | struct { | |
156 | unsigned int x; | |
157 | unsigned int y; | |
158 | unsigned int w; | |
159 | unsigned int h; | |
160 | } dst; | |
161 | unsigned int bits_per_pixel; | |
162 | unsigned int format; | |
f925390e | 163 | unsigned int swap; |
f34bc787 TR |
164 | unsigned int stride[2]; |
165 | unsigned long base[3]; | |
db7fbdfd | 166 | bool bottom_up; |
c134f019 TR |
167 | |
168 | struct tegra_bo_tiling tiling; | |
f34bc787 TR |
169 | }; |
170 | ||
171 | /* from dc.c */ | |
688c59af TR |
172 | void tegra_dc_enable_vblank(struct tegra_dc *dc); |
173 | void tegra_dc_disable_vblank(struct tegra_dc *dc); | |
174 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); | |
f34bc787 | 175 | |
d8f4a9ed TR |
176 | struct tegra_output_ops { |
177 | int (*enable)(struct tegra_output *output); | |
178 | int (*disable)(struct tegra_output *output); | |
179 | int (*setup_clock)(struct tegra_output *output, struct clk *clk, | |
91eded9b | 180 | unsigned long pclk, unsigned int *div); |
d8f4a9ed TR |
181 | int (*check_mode)(struct tegra_output *output, |
182 | struct drm_display_mode *mode, | |
183 | enum drm_mode_status *status); | |
6b6b6042 | 184 | enum drm_connector_status (*detect)(struct tegra_output *output); |
d8f4a9ed TR |
185 | }; |
186 | ||
187 | enum tegra_output_type { | |
188 | TEGRA_OUTPUT_RGB, | |
edec4af4 | 189 | TEGRA_OUTPUT_HDMI, |
dec72739 | 190 | TEGRA_OUTPUT_DSI, |
6b6b6042 | 191 | TEGRA_OUTPUT_EDP, |
d8f4a9ed TR |
192 | }; |
193 | ||
194 | struct tegra_output { | |
195 | struct device_node *of_node; | |
196 | struct device *dev; | |
197 | ||
198 | const struct tegra_output_ops *ops; | |
199 | enum tegra_output_type type; | |
200 | ||
9be7d864 | 201 | struct drm_panel *panel; |
d8f4a9ed TR |
202 | struct i2c_adapter *ddc; |
203 | const struct edid *edid; | |
204 | unsigned int hpd_irq; | |
205 | int hpd_gpio; | |
206 | ||
207 | struct drm_encoder encoder; | |
208 | struct drm_connector connector; | |
209 | }; | |
210 | ||
211 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) | |
212 | { | |
213 | return container_of(e, struct tegra_output, encoder); | |
214 | } | |
215 | ||
216 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) | |
217 | { | |
218 | return container_of(c, struct tegra_output, connector); | |
219 | } | |
220 | ||
221 | static inline int tegra_output_enable(struct tegra_output *output) | |
222 | { | |
223 | if (output && output->ops && output->ops->enable) | |
224 | return output->ops->enable(output); | |
225 | ||
226 | return output ? -ENOSYS : -EINVAL; | |
227 | } | |
228 | ||
229 | static inline int tegra_output_disable(struct tegra_output *output) | |
230 | { | |
231 | if (output && output->ops && output->ops->disable) | |
232 | return output->ops->disable(output); | |
233 | ||
234 | return output ? -ENOSYS : -EINVAL; | |
235 | } | |
236 | ||
237 | static inline int tegra_output_setup_clock(struct tegra_output *output, | |
91eded9b TR |
238 | struct clk *clk, unsigned long pclk, |
239 | unsigned int *div) | |
d8f4a9ed TR |
240 | { |
241 | if (output && output->ops && output->ops->setup_clock) | |
91eded9b | 242 | return output->ops->setup_clock(output, clk, pclk, div); |
d8f4a9ed TR |
243 | |
244 | return output ? -ENOSYS : -EINVAL; | |
245 | } | |
246 | ||
247 | static inline int tegra_output_check_mode(struct tegra_output *output, | |
248 | struct drm_display_mode *mode, | |
249 | enum drm_mode_status *status) | |
250 | { | |
251 | if (output && output->ops && output->ops->check_mode) | |
252 | return output->ops->check_mode(output, mode, status); | |
253 | ||
254 | return output ? -ENOSYS : -EINVAL; | |
255 | } | |
256 | ||
257 | /* from rgb.c */ | |
688c59af TR |
258 | int tegra_dc_rgb_probe(struct tegra_dc *dc); |
259 | int tegra_dc_rgb_remove(struct tegra_dc *dc); | |
260 | int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); | |
261 | int tegra_dc_rgb_exit(struct tegra_dc *dc); | |
d8f4a9ed TR |
262 | |
263 | /* from output.c */ | |
688c59af TR |
264 | int tegra_output_probe(struct tegra_output *output); |
265 | int tegra_output_remove(struct tegra_output *output); | |
266 | int tegra_output_init(struct drm_device *drm, struct tegra_output *output); | |
267 | int tegra_output_exit(struct tegra_output *output); | |
d8f4a9ed | 268 | |
6b6b6042 | 269 | /* from dpaux.c */ |
6b6b6042 TR |
270 | struct tegra_dpaux; |
271 | struct drm_dp_link; | |
6b6b6042 TR |
272 | |
273 | struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np); | |
274 | enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux); | |
275 | int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output); | |
276 | int tegra_dpaux_detach(struct tegra_dpaux *dpaux); | |
277 | int tegra_dpaux_enable(struct tegra_dpaux *dpaux); | |
278 | int tegra_dpaux_disable(struct tegra_dpaux *dpaux); | |
279 | int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding); | |
280 | int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link, | |
281 | u8 pattern); | |
282 | ||
d8f4a9ed | 283 | /* from fb.c */ |
de2ba664 AM |
284 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
285 | unsigned int index); | |
db7fbdfd | 286 | bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); |
c134f019 TR |
287 | int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, |
288 | struct tegra_bo_tiling *tiling); | |
e2215321 | 289 | int tegra_drm_fb_prepare(struct drm_device *drm); |
688c59af TR |
290 | int tegra_drm_fb_init(struct drm_device *drm); |
291 | void tegra_drm_fb_exit(struct drm_device *drm); | |
60c2f709 | 292 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
688c59af | 293 | void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
60c2f709 | 294 | #endif |
d8f4a9ed | 295 | |
776dc384 | 296 | extern struct platform_driver tegra_dc_driver; |
dec72739 | 297 | extern struct platform_driver tegra_dsi_driver; |
6b6b6042 | 298 | extern struct platform_driver tegra_sor_driver; |
776dc384 | 299 | extern struct platform_driver tegra_hdmi_driver; |
6b6b6042 | 300 | extern struct platform_driver tegra_dpaux_driver; |
776dc384 | 301 | extern struct platform_driver tegra_gr2d_driver; |
5f60ed0d | 302 | extern struct platform_driver tegra_gr3d_driver; |
d8f4a9ed | 303 | |
4231c6b0 | 304 | #endif /* HOST1X_DRM_H */ |