Commit | Line | Data |
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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
4231c6b0 TB |
10 | #ifndef HOST1X_DRM_H |
11 | #define HOST1X_DRM_H 1 | |
d8f4a9ed | 12 | |
e1e90644 TR |
13 | #include <uapi/drm/tegra_drm.h> |
14 | #include <linux/host1x.h> | |
15 | ||
d8f4a9ed TR |
16 | #include <drm/drmP.h> |
17 | #include <drm/drm_crtc_helper.h> | |
18 | #include <drm/drm_edid.h> | |
19 | #include <drm/drm_fb_helper.h> | |
d8f4a9ed TR |
20 | #include <drm/drm_fixed.h> |
21 | ||
de2ba664 AM |
22 | struct tegra_fb { |
23 | struct drm_framebuffer base; | |
24 | struct tegra_bo **planes; | |
25 | unsigned int num_planes; | |
26 | }; | |
27 | ||
28 | struct tegra_fbdev { | |
29 | struct drm_fb_helper base; | |
30 | struct tegra_fb *fb; | |
31 | }; | |
32 | ||
386a2a71 | 33 | struct tegra_drm { |
d8f4a9ed | 34 | struct drm_device *drm; |
d8f4a9ed TR |
35 | |
36 | struct mutex clients_lock; | |
37 | struct list_head clients; | |
38 | ||
de2ba664 | 39 | struct tegra_fbdev *fbdev; |
d8f4a9ed TR |
40 | }; |
41 | ||
53fa7f72 | 42 | struct tegra_drm_client; |
d8f4a9ed | 43 | |
c88c3630 | 44 | struct tegra_drm_context { |
53fa7f72 | 45 | struct tegra_drm_client *client; |
d43f81cb TB |
46 | struct host1x_channel *channel; |
47 | struct list_head list; | |
48 | }; | |
49 | ||
53fa7f72 TR |
50 | struct tegra_drm_client_ops { |
51 | int (*open_channel)(struct tegra_drm_client *client, | |
c88c3630 TR |
52 | struct tegra_drm_context *context); |
53 | void (*close_channel)(struct tegra_drm_context *context); | |
c40f0f1a | 54 | int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); |
c88c3630 | 55 | int (*submit)(struct tegra_drm_context *context, |
d43f81cb TB |
56 | struct drm_tegra_submit *args, struct drm_device *drm, |
57 | struct drm_file *file); | |
58 | }; | |
59 | ||
c40f0f1a TR |
60 | int tegra_drm_submit(struct tegra_drm_context *context, |
61 | struct drm_tegra_submit *args, struct drm_device *drm, | |
62 | struct drm_file *file); | |
63 | ||
53fa7f72 TR |
64 | struct tegra_drm_client { |
65 | struct host1x_client base; | |
776dc384 | 66 | struct list_head list; |
d43f81cb | 67 | |
53fa7f72 | 68 | const struct tegra_drm_client_ops *ops; |
d8f4a9ed TR |
69 | }; |
70 | ||
53fa7f72 | 71 | static inline struct tegra_drm_client * |
776dc384 | 72 | host1x_to_drm_client(struct host1x_client *client) |
53fa7f72 TR |
73 | { |
74 | return container_of(client, struct tegra_drm_client, base); | |
75 | } | |
76 | ||
776dc384 TR |
77 | extern int tegra_drm_register_client(struct tegra_drm *tegra, |
78 | struct tegra_drm_client *client); | |
79 | extern int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
80 | struct tegra_drm_client *client); | |
81 | ||
386a2a71 TR |
82 | extern int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
83 | extern int tegra_drm_exit(struct tegra_drm *tegra); | |
d8f4a9ed | 84 | |
d8f4a9ed TR |
85 | struct tegra_output; |
86 | ||
87 | struct tegra_dc { | |
776dc384 | 88 | struct host1x_client client; |
d8f4a9ed | 89 | struct device *dev; |
d18d3033 | 90 | spinlock_t lock; |
d8f4a9ed TR |
91 | |
92 | struct drm_crtc base; | |
93 | int pipe; | |
94 | ||
95 | struct clk *clk; | |
d8f4a9ed TR |
96 | void __iomem *regs; |
97 | int irq; | |
98 | ||
99 | struct tegra_output *rgb; | |
100 | ||
101 | struct list_head list; | |
102 | ||
103 | struct drm_info_list *debugfs_files; | |
104 | struct drm_minor *minor; | |
105 | struct dentry *debugfs; | |
3c03c46a TR |
106 | |
107 | /* page-flip handling */ | |
108 | struct drm_pending_vblank_event *event; | |
d8f4a9ed TR |
109 | }; |
110 | ||
53fa7f72 | 111 | static inline struct tegra_dc * |
776dc384 | 112 | host1x_client_to_dc(struct host1x_client *client) |
d8f4a9ed TR |
113 | { |
114 | return container_of(client, struct tegra_dc, client); | |
115 | } | |
116 | ||
117 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) | |
118 | { | |
119 | return container_of(crtc, struct tegra_dc, base); | |
120 | } | |
121 | ||
122 | static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, | |
123 | unsigned long reg) | |
124 | { | |
125 | writel(value, dc->regs + (reg << 2)); | |
126 | } | |
127 | ||
128 | static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, | |
129 | unsigned long reg) | |
130 | { | |
131 | return readl(dc->regs + (reg << 2)); | |
132 | } | |
133 | ||
f34bc787 TR |
134 | struct tegra_dc_window { |
135 | struct { | |
136 | unsigned int x; | |
137 | unsigned int y; | |
138 | unsigned int w; | |
139 | unsigned int h; | |
140 | } src; | |
141 | struct { | |
142 | unsigned int x; | |
143 | unsigned int y; | |
144 | unsigned int w; | |
145 | unsigned int h; | |
146 | } dst; | |
147 | unsigned int bits_per_pixel; | |
148 | unsigned int format; | |
149 | unsigned int stride[2]; | |
150 | unsigned long base[3]; | |
773af77f | 151 | bool tiled; |
f34bc787 TR |
152 | }; |
153 | ||
154 | /* from dc.c */ | |
155 | extern unsigned int tegra_dc_format(uint32_t format); | |
156 | extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |
157 | const struct tegra_dc_window *window); | |
6e5ff998 TR |
158 | extern void tegra_dc_enable_vblank(struct tegra_dc *dc); |
159 | extern void tegra_dc_disable_vblank(struct tegra_dc *dc); | |
3c03c46a TR |
160 | extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, |
161 | struct drm_file *file); | |
f34bc787 | 162 | |
d8f4a9ed TR |
163 | struct tegra_output_ops { |
164 | int (*enable)(struct tegra_output *output); | |
165 | int (*disable)(struct tegra_output *output); | |
166 | int (*setup_clock)(struct tegra_output *output, struct clk *clk, | |
167 | unsigned long pclk); | |
168 | int (*check_mode)(struct tegra_output *output, | |
169 | struct drm_display_mode *mode, | |
170 | enum drm_mode_status *status); | |
171 | }; | |
172 | ||
173 | enum tegra_output_type { | |
174 | TEGRA_OUTPUT_RGB, | |
edec4af4 | 175 | TEGRA_OUTPUT_HDMI, |
d8f4a9ed TR |
176 | }; |
177 | ||
178 | struct tegra_output { | |
179 | struct device_node *of_node; | |
180 | struct device *dev; | |
181 | ||
182 | const struct tegra_output_ops *ops; | |
183 | enum tegra_output_type type; | |
184 | ||
185 | struct i2c_adapter *ddc; | |
186 | const struct edid *edid; | |
187 | unsigned int hpd_irq; | |
188 | int hpd_gpio; | |
189 | ||
190 | struct drm_encoder encoder; | |
191 | struct drm_connector connector; | |
192 | }; | |
193 | ||
194 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) | |
195 | { | |
196 | return container_of(e, struct tegra_output, encoder); | |
197 | } | |
198 | ||
199 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) | |
200 | { | |
201 | return container_of(c, struct tegra_output, connector); | |
202 | } | |
203 | ||
204 | static inline int tegra_output_enable(struct tegra_output *output) | |
205 | { | |
206 | if (output && output->ops && output->ops->enable) | |
207 | return output->ops->enable(output); | |
208 | ||
209 | return output ? -ENOSYS : -EINVAL; | |
210 | } | |
211 | ||
212 | static inline int tegra_output_disable(struct tegra_output *output) | |
213 | { | |
214 | if (output && output->ops && output->ops->disable) | |
215 | return output->ops->disable(output); | |
216 | ||
217 | return output ? -ENOSYS : -EINVAL; | |
218 | } | |
219 | ||
220 | static inline int tegra_output_setup_clock(struct tegra_output *output, | |
221 | struct clk *clk, unsigned long pclk) | |
222 | { | |
223 | if (output && output->ops && output->ops->setup_clock) | |
224 | return output->ops->setup_clock(output, clk, pclk); | |
225 | ||
226 | return output ? -ENOSYS : -EINVAL; | |
227 | } | |
228 | ||
229 | static inline int tegra_output_check_mode(struct tegra_output *output, | |
230 | struct drm_display_mode *mode, | |
231 | enum drm_mode_status *status) | |
232 | { | |
233 | if (output && output->ops && output->ops->check_mode) | |
234 | return output->ops->check_mode(output, mode, status); | |
235 | ||
236 | return output ? -ENOSYS : -EINVAL; | |
237 | } | |
238 | ||
776dc384 TR |
239 | /* from bus.c */ |
240 | int drm_host1x_init(struct drm_driver *driver, struct host1x_device *device); | |
241 | void drm_host1x_exit(struct drm_driver *driver, struct host1x_device *device); | |
242 | ||
d8f4a9ed TR |
243 | /* from rgb.c */ |
244 | extern int tegra_dc_rgb_probe(struct tegra_dc *dc); | |
59d29c0e | 245 | extern int tegra_dc_rgb_remove(struct tegra_dc *dc); |
d8f4a9ed TR |
246 | extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); |
247 | extern int tegra_dc_rgb_exit(struct tegra_dc *dc); | |
248 | ||
249 | /* from output.c */ | |
59d29c0e TR |
250 | extern int tegra_output_probe(struct tegra_output *output); |
251 | extern int tegra_output_remove(struct tegra_output *output); | |
d8f4a9ed TR |
252 | extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output); |
253 | extern int tegra_output_exit(struct tegra_output *output); | |
254 | ||
d8f4a9ed | 255 | /* from fb.c */ |
de2ba664 AM |
256 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
257 | unsigned int index); | |
773af77f | 258 | bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer); |
d8f4a9ed TR |
259 | extern int tegra_drm_fb_init(struct drm_device *drm); |
260 | extern void tegra_drm_fb_exit(struct drm_device *drm); | |
de2ba664 | 261 | extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
d8f4a9ed | 262 | |
776dc384 TR |
263 | extern struct platform_driver tegra_dc_driver; |
264 | extern struct platform_driver tegra_hdmi_driver; | |
265 | extern struct platform_driver tegra_gr2d_driver; | |
5f60ed0d | 266 | extern struct platform_driver tegra_gr3d_driver; |
d8f4a9ed | 267 | |
4231c6b0 | 268 | #endif /* HOST1X_DRM_H */ |