Commit | Line | Data |
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d43f81cb | 1 | /* |
d43f81cb TB |
2 | * Copyright (c) 2012-2013, NVIDIA Corporation. |
3 | * | |
d105a6c9 TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
d43f81cb TB |
7 | */ |
8 | ||
d43f81cb TB |
9 | #include <linux/clk.h> |
10 | ||
d43f81cb TB |
11 | #include "drm.h" |
12 | #include "gem.h" | |
497c56a5 | 13 | #include "gr2d.h" |
c1bef81f | 14 | |
d43f81cb | 15 | struct gr2d { |
53fa7f72 | 16 | struct tegra_drm_client client; |
d43f81cb | 17 | struct host1x_channel *channel; |
c1bef81f TR |
18 | struct clk *clk; |
19 | ||
20 | DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS); | |
d43f81cb TB |
21 | }; |
22 | ||
53fa7f72 | 23 | static inline struct gr2d *to_gr2d(struct tegra_drm_client *client) |
d43f81cb TB |
24 | { |
25 | return container_of(client, struct gr2d, client); | |
26 | } | |
27 | ||
776dc384 | 28 | static int gr2d_init(struct host1x_client *client) |
d43f81cb | 29 | { |
776dc384 | 30 | struct tegra_drm_client *drm = host1x_to_drm_client(client); |
9910f5c4 | 31 | struct drm_device *dev = dev_get_drvdata(client->parent); |
61644dc7 | 32 | unsigned long flags = HOST1X_SYNCPT_HAS_BASE; |
776dc384 TR |
33 | struct gr2d *gr2d = to_gr2d(drm); |
34 | ||
35 | gr2d->channel = host1x_channel_request(client->dev); | |
36 | if (!gr2d->channel) | |
37 | return -ENOMEM; | |
38 | ||
61644dc7 | 39 | client->syncpts[0] = host1x_syncpt_request(client->dev, flags); |
776dc384 TR |
40 | if (!client->syncpts[0]) { |
41 | host1x_channel_free(gr2d->channel); | |
42 | return -ENOMEM; | |
43 | } | |
44 | ||
9910f5c4 | 45 | return tegra_drm_register_client(dev->dev_private, drm); |
d43f81cb TB |
46 | } |
47 | ||
776dc384 | 48 | static int gr2d_exit(struct host1x_client *client) |
d43f81cb | 49 | { |
776dc384 | 50 | struct tegra_drm_client *drm = host1x_to_drm_client(client); |
9910f5c4 | 51 | struct drm_device *dev = dev_get_drvdata(client->parent); |
776dc384 TR |
52 | struct gr2d *gr2d = to_gr2d(drm); |
53 | int err; | |
54 | ||
9910f5c4 | 55 | err = tegra_drm_unregister_client(dev->dev_private, drm); |
776dc384 TR |
56 | if (err < 0) |
57 | return err; | |
58 | ||
59 | host1x_syncpt_free(client->syncpts[0]); | |
60 | host1x_channel_free(gr2d->channel); | |
61 | ||
d43f81cb TB |
62 | return 0; |
63 | } | |
64 | ||
53fa7f72 | 65 | static const struct host1x_client_ops gr2d_client_ops = { |
776dc384 TR |
66 | .init = gr2d_init, |
67 | .exit = gr2d_exit, | |
53fa7f72 TR |
68 | }; |
69 | ||
70 | static int gr2d_open_channel(struct tegra_drm_client *client, | |
c88c3630 | 71 | struct tegra_drm_context *context) |
d43f81cb TB |
72 | { |
73 | struct gr2d *gr2d = to_gr2d(client); | |
74 | ||
75 | context->channel = host1x_channel_get(gr2d->channel); | |
d43f81cb TB |
76 | if (!context->channel) |
77 | return -ENOMEM; | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
c88c3630 | 82 | static void gr2d_close_channel(struct tegra_drm_context *context) |
d43f81cb TB |
83 | { |
84 | host1x_channel_put(context->channel); | |
85 | } | |
86 | ||
c1bef81f TR |
87 | static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset) |
88 | { | |
89 | struct gr2d *gr2d = dev_get_drvdata(dev); | |
90 | ||
91 | switch (class) { | |
92 | case HOST1X_CLASS_HOST1X: | |
93 | if (offset == 0x2b) | |
94 | return 1; | |
95 | ||
96 | break; | |
97 | ||
98 | case HOST1X_CLASS_GR2D: | |
99 | case HOST1X_CLASS_GR2D_SB: | |
100 | if (offset >= GR2D_NUM_REGS) | |
101 | break; | |
102 | ||
103 | if (test_bit(offset, gr2d->addr_regs)) | |
104 | return 1; | |
105 | ||
106 | break; | |
107 | } | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
53fa7f72 | 112 | static const struct tegra_drm_client_ops gr2d_ops = { |
d43f81cb TB |
113 | .open_channel = gr2d_open_channel, |
114 | .close_channel = gr2d_close_channel, | |
c40f0f1a TR |
115 | .is_addr_reg = gr2d_is_addr_reg, |
116 | .submit = tegra_drm_submit, | |
d43f81cb TB |
117 | }; |
118 | ||
d43f81cb TB |
119 | static const struct of_device_id gr2d_match[] = { |
120 | { .compatible = "nvidia,tegra30-gr2d" }, | |
121 | { .compatible = "nvidia,tegra20-gr2d" }, | |
122 | { }, | |
123 | }; | |
ef70728c | 124 | MODULE_DEVICE_TABLE(of, gr2d_match); |
d43f81cb | 125 | |
c1bef81f | 126 | static const u32 gr2d_addr_regs[] = { |
497c56a5 TR |
127 | GR2D_UA_BASE_ADDR, |
128 | GR2D_VA_BASE_ADDR, | |
129 | GR2D_PAT_BASE_ADDR, | |
130 | GR2D_DSTA_BASE_ADDR, | |
131 | GR2D_DSTB_BASE_ADDR, | |
132 | GR2D_DSTC_BASE_ADDR, | |
133 | GR2D_SRCA_BASE_ADDR, | |
134 | GR2D_SRCB_BASE_ADDR, | |
135 | GR2D_SRC_BASE_ADDR_SB, | |
136 | GR2D_DSTA_BASE_ADDR_SB, | |
137 | GR2D_DSTB_BASE_ADDR_SB, | |
138 | GR2D_UA_BASE_ADDR_SB, | |
139 | GR2D_VA_BASE_ADDR_SB, | |
c1bef81f TR |
140 | }; |
141 | ||
d43f81cb TB |
142 | static int gr2d_probe(struct platform_device *pdev) |
143 | { | |
144 | struct device *dev = &pdev->dev; | |
d43f81cb | 145 | struct host1x_syncpt **syncpts; |
c1bef81f TR |
146 | struct gr2d *gr2d; |
147 | unsigned int i; | |
148 | int err; | |
d43f81cb TB |
149 | |
150 | gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL); | |
151 | if (!gr2d) | |
152 | return -ENOMEM; | |
153 | ||
154 | syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); | |
155 | if (!syncpts) | |
156 | return -ENOMEM; | |
157 | ||
158 | gr2d->clk = devm_clk_get(dev, NULL); | |
159 | if (IS_ERR(gr2d->clk)) { | |
160 | dev_err(dev, "cannot get clock\n"); | |
161 | return PTR_ERR(gr2d->clk); | |
162 | } | |
163 | ||
164 | err = clk_prepare_enable(gr2d->clk); | |
165 | if (err) { | |
166 | dev_err(dev, "cannot turn on clock\n"); | |
167 | return err; | |
168 | } | |
169 | ||
53fa7f72 TR |
170 | INIT_LIST_HEAD(&gr2d->client.base.list); |
171 | gr2d->client.base.ops = &gr2d_client_ops; | |
172 | gr2d->client.base.dev = dev; | |
173 | gr2d->client.base.class = HOST1X_CLASS_GR2D; | |
174 | gr2d->client.base.syncpts = syncpts; | |
175 | gr2d->client.base.num_syncpts = 1; | |
776dc384 TR |
176 | |
177 | INIT_LIST_HEAD(&gr2d->client.list); | |
53fa7f72 | 178 | gr2d->client.ops = &gr2d_ops; |
d43f81cb | 179 | |
776dc384 | 180 | err = host1x_client_register(&gr2d->client.base); |
d43f81cb TB |
181 | if (err < 0) { |
182 | dev_err(dev, "failed to register host1x client: %d\n", err); | |
b0084031 | 183 | clk_disable_unprepare(gr2d->clk); |
d43f81cb TB |
184 | return err; |
185 | } | |
186 | ||
c1bef81f TR |
187 | /* initialize address register map */ |
188 | for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++) | |
189 | set_bit(gr2d_addr_regs[i], gr2d->addr_regs); | |
d43f81cb TB |
190 | |
191 | platform_set_drvdata(pdev, gr2d); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
c1bef81f | 196 | static int gr2d_remove(struct platform_device *pdev) |
d43f81cb | 197 | { |
d43f81cb | 198 | struct gr2d *gr2d = platform_get_drvdata(pdev); |
d43f81cb TB |
199 | int err; |
200 | ||
776dc384 | 201 | err = host1x_client_unregister(&gr2d->client.base); |
d43f81cb | 202 | if (err < 0) { |
c1bef81f TR |
203 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
204 | err); | |
d43f81cb TB |
205 | return err; |
206 | } | |
207 | ||
d43f81cb TB |
208 | clk_disable_unprepare(gr2d->clk); |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | struct platform_driver tegra_gr2d_driver = { | |
d43f81cb | 214 | .driver = { |
a137ce34 | 215 | .name = "tegra-gr2d", |
d43f81cb | 216 | .of_match_table = gr2d_match, |
c1bef81f TR |
217 | }, |
218 | .probe = gr2d_probe, | |
219 | .remove = gr2d_remove, | |
d43f81cb | 220 | }; |