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edec4af4 TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/debugfs.h> | |
ac24c220 | 12 | #include <linux/hdmi.h> |
edec4af4 | 13 | #include <linux/regulator/consumer.h> |
ca48080a | 14 | #include <linux/reset.h> |
ac24c220 | 15 | |
edec4af4 TR |
16 | #include "hdmi.h" |
17 | #include "drm.h" | |
18 | #include "dc.h" | |
19 | ||
59af0595 TR |
20 | struct tmds_config { |
21 | unsigned int pclk; | |
22 | u32 pll0; | |
23 | u32 pll1; | |
24 | u32 pe_current; | |
25 | u32 drive_current; | |
7d1d28ac | 26 | u32 peak_current; |
59af0595 TR |
27 | }; |
28 | ||
29 | struct tegra_hdmi_config { | |
30 | const struct tmds_config *tmds; | |
31 | unsigned int num_tmds; | |
32 | ||
33 | unsigned long fuse_override_offset; | |
34 | unsigned long fuse_override_value; | |
7d1d28ac MP |
35 | |
36 | bool has_sor_io_peak_current; | |
59af0595 TR |
37 | }; |
38 | ||
edec4af4 | 39 | struct tegra_hdmi { |
776dc384 | 40 | struct host1x_client client; |
edec4af4 TR |
41 | struct tegra_output output; |
42 | struct device *dev; | |
365765fc | 43 | bool enabled; |
edec4af4 | 44 | |
fb50a116 | 45 | struct regulator *hdmi; |
edec4af4 | 46 | struct regulator *pll; |
88685687 | 47 | struct regulator *vdd; |
edec4af4 TR |
48 | |
49 | void __iomem *regs; | |
50 | unsigned int irq; | |
51 | ||
52 | struct clk *clk_parent; | |
53 | struct clk *clk; | |
ca48080a | 54 | struct reset_control *rst; |
edec4af4 | 55 | |
59af0595 TR |
56 | const struct tegra_hdmi_config *config; |
57 | ||
edec4af4 TR |
58 | unsigned int audio_source; |
59 | unsigned int audio_freq; | |
60 | bool stereo; | |
61 | bool dvi; | |
62 | ||
63 | struct drm_info_list *debugfs_files; | |
64 | struct drm_minor *minor; | |
65 | struct dentry *debugfs; | |
66 | }; | |
67 | ||
68 | static inline struct tegra_hdmi * | |
776dc384 | 69 | host1x_client_to_hdmi(struct host1x_client *client) |
edec4af4 TR |
70 | { |
71 | return container_of(client, struct tegra_hdmi, client); | |
72 | } | |
73 | ||
74 | static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output) | |
75 | { | |
76 | return container_of(output, struct tegra_hdmi, output); | |
77 | } | |
78 | ||
79 | #define HDMI_AUDIOCLK_FREQ 216000000 | |
80 | #define HDMI_REKEY_DEFAULT 56 | |
81 | ||
82 | enum { | |
83 | AUTO = 0, | |
84 | SPDIF, | |
85 | HDA, | |
86 | }; | |
87 | ||
88 | static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi, | |
89 | unsigned long reg) | |
90 | { | |
91 | return readl(hdmi->regs + (reg << 2)); | |
92 | } | |
93 | ||
94 | static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val, | |
95 | unsigned long reg) | |
96 | { | |
97 | writel(val, hdmi->regs + (reg << 2)); | |
98 | } | |
99 | ||
100 | struct tegra_hdmi_audio_config { | |
101 | unsigned int pclk; | |
102 | unsigned int n; | |
103 | unsigned int cts; | |
104 | unsigned int aval; | |
105 | }; | |
106 | ||
107 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = { | |
108 | { 25200000, 4096, 25200, 24000 }, | |
109 | { 27000000, 4096, 27000, 24000 }, | |
110 | { 74250000, 4096, 74250, 24000 }, | |
111 | { 148500000, 4096, 148500, 24000 }, | |
112 | { 0, 0, 0, 0 }, | |
113 | }; | |
114 | ||
115 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = { | |
116 | { 25200000, 5880, 26250, 25000 }, | |
117 | { 27000000, 5880, 28125, 25000 }, | |
118 | { 74250000, 4704, 61875, 20000 }, | |
119 | { 148500000, 4704, 123750, 20000 }, | |
120 | { 0, 0, 0, 0 }, | |
121 | }; | |
122 | ||
123 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = { | |
124 | { 25200000, 6144, 25200, 24000 }, | |
125 | { 27000000, 6144, 27000, 24000 }, | |
126 | { 74250000, 6144, 74250, 24000 }, | |
127 | { 148500000, 6144, 148500, 24000 }, | |
128 | { 0, 0, 0, 0 }, | |
129 | }; | |
130 | ||
131 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = { | |
132 | { 25200000, 11760, 26250, 25000 }, | |
133 | { 27000000, 11760, 28125, 25000 }, | |
134 | { 74250000, 9408, 61875, 20000 }, | |
135 | { 148500000, 9408, 123750, 20000 }, | |
136 | { 0, 0, 0, 0 }, | |
137 | }; | |
138 | ||
139 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = { | |
140 | { 25200000, 12288, 25200, 24000 }, | |
141 | { 27000000, 12288, 27000, 24000 }, | |
142 | { 74250000, 12288, 74250, 24000 }, | |
143 | { 148500000, 12288, 148500, 24000 }, | |
144 | { 0, 0, 0, 0 }, | |
145 | }; | |
146 | ||
147 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = { | |
148 | { 25200000, 23520, 26250, 25000 }, | |
149 | { 27000000, 23520, 28125, 25000 }, | |
150 | { 74250000, 18816, 61875, 20000 }, | |
151 | { 148500000, 18816, 123750, 20000 }, | |
152 | { 0, 0, 0, 0 }, | |
153 | }; | |
154 | ||
155 | static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = { | |
156 | { 25200000, 24576, 25200, 24000 }, | |
157 | { 27000000, 24576, 27000, 24000 }, | |
158 | { 74250000, 24576, 74250, 24000 }, | |
159 | { 148500000, 24576, 148500, 24000 }, | |
160 | { 0, 0, 0, 0 }, | |
161 | }; | |
162 | ||
f27db961 | 163 | static const struct tmds_config tegra20_tmds_config[] = { |
fa416ddc | 164 | { /* slow pixel clock modes */ |
edec4af4 TR |
165 | .pclk = 27000000, |
166 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | |
167 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | | |
168 | SOR_PLL_TX_REG_LOAD(3), | |
169 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE, | |
170 | .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | | |
171 | PE_CURRENT1(PE_CURRENT_0_0_mA) | | |
172 | PE_CURRENT2(PE_CURRENT_0_0_mA) | | |
173 | PE_CURRENT3(PE_CURRENT_0_0_mA), | |
174 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | | |
175 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | | |
176 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | | |
177 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), | |
fa416ddc LS |
178 | }, |
179 | { /* high pixel clock modes */ | |
edec4af4 TR |
180 | .pclk = UINT_MAX, |
181 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | |
182 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | | |
183 | SOR_PLL_TX_REG_LOAD(3), | |
184 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, | |
185 | .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | | |
186 | PE_CURRENT1(PE_CURRENT_6_0_mA) | | |
187 | PE_CURRENT2(PE_CURRENT_6_0_mA) | | |
188 | PE_CURRENT3(PE_CURRENT_6_0_mA), | |
189 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | | |
190 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | | |
191 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | | |
192 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), | |
193 | }, | |
194 | }; | |
195 | ||
f27db961 | 196 | static const struct tmds_config tegra30_tmds_config[] = { |
edec4af4 TR |
197 | { /* 480p modes */ |
198 | .pclk = 27000000, | |
199 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | |
200 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | | |
201 | SOR_PLL_TX_REG_LOAD(0), | |
202 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE, | |
203 | .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | | |
204 | PE_CURRENT1(PE_CURRENT_0_0_mA) | | |
205 | PE_CURRENT2(PE_CURRENT_0_0_mA) | | |
206 | PE_CURRENT3(PE_CURRENT_0_0_mA), | |
207 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | | |
208 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | | |
209 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | | |
210 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), | |
211 | }, { /* 720p modes */ | |
212 | .pclk = 74250000, | |
213 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | |
214 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | | |
215 | SOR_PLL_TX_REG_LOAD(0), | |
216 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, | |
217 | .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | | |
218 | PE_CURRENT1(PE_CURRENT_5_0_mA) | | |
219 | PE_CURRENT2(PE_CURRENT_5_0_mA) | | |
220 | PE_CURRENT3(PE_CURRENT_5_0_mA), | |
221 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | | |
222 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | | |
223 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | | |
224 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), | |
225 | }, { /* 1080p modes */ | |
226 | .pclk = UINT_MAX, | |
227 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | |
228 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) | | |
229 | SOR_PLL_TX_REG_LOAD(0), | |
230 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, | |
231 | .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | | |
232 | PE_CURRENT1(PE_CURRENT_5_0_mA) | | |
233 | PE_CURRENT2(PE_CURRENT_5_0_mA) | | |
234 | PE_CURRENT3(PE_CURRENT_5_0_mA), | |
235 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | | |
236 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | | |
237 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | | |
238 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), | |
239 | }, | |
240 | }; | |
241 | ||
7d1d28ac MP |
242 | static const struct tmds_config tegra114_tmds_config[] = { |
243 | { /* 480p/576p / 25.2MHz/27MHz modes */ | |
244 | .pclk = 27000000, | |
245 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
246 | SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, | |
247 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), | |
248 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | | |
249 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | | |
250 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | | |
251 | PE_CURRENT3(PE_CURRENT_0_mA_T114), | |
252 | .drive_current = | |
253 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
254 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
255 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
256 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), | |
257 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | | |
258 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | | |
259 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | | |
260 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), | |
261 | }, { /* 720p / 74.25MHz modes */ | |
262 | .pclk = 74250000, | |
263 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
264 | SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, | |
265 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | | |
266 | SOR_PLL_TMDS_TERMADJ(0), | |
267 | .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | | |
268 | PE_CURRENT1(PE_CURRENT_15_mA_T114) | | |
269 | PE_CURRENT2(PE_CURRENT_15_mA_T114) | | |
270 | PE_CURRENT3(PE_CURRENT_15_mA_T114), | |
271 | .drive_current = | |
272 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
273 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
274 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
275 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), | |
276 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | | |
277 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | | |
278 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | | |
279 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), | |
280 | }, { /* 1080p / 148.5MHz modes */ | |
281 | .pclk = 148500000, | |
282 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
283 | SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, | |
284 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | | |
285 | SOR_PLL_TMDS_TERMADJ(0), | |
286 | .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | | |
287 | PE_CURRENT1(PE_CURRENT_10_mA_T114) | | |
288 | PE_CURRENT2(PE_CURRENT_10_mA_T114) | | |
289 | PE_CURRENT3(PE_CURRENT_10_mA_T114), | |
290 | .drive_current = | |
291 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | | |
292 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | | |
293 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | | |
294 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), | |
295 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | | |
296 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | | |
297 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | | |
298 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), | |
299 | }, { /* 225/297MHz modes */ | |
300 | .pclk = UINT_MAX, | |
301 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
302 | SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, | |
303 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) | |
304 | | SOR_PLL_TMDS_TERM_ENABLE, | |
305 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | | |
306 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | | |
307 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | | |
308 | PE_CURRENT3(PE_CURRENT_0_mA_T114), | |
309 | .drive_current = | |
310 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | | |
311 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | | |
312 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | | |
313 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), | |
314 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | | |
315 | PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | | |
316 | PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | | |
317 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), | |
318 | }, | |
319 | }; | |
320 | ||
fb7be70e TR |
321 | static const struct tmds_config tegra124_tmds_config[] = { |
322 | { /* 480p/576p / 25.2MHz/27MHz modes */ | |
323 | .pclk = 27000000, | |
324 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
325 | SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, | |
326 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), | |
327 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | | |
328 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | | |
329 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | | |
330 | PE_CURRENT3(PE_CURRENT_0_mA_T114), | |
331 | .drive_current = | |
332 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
333 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
334 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
335 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), | |
336 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | | |
337 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | | |
338 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | | |
339 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), | |
340 | }, { /* 720p / 74.25MHz modes */ | |
341 | .pclk = 74250000, | |
342 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
343 | SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, | |
344 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | | |
345 | SOR_PLL_TMDS_TERMADJ(0), | |
346 | .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | | |
347 | PE_CURRENT1(PE_CURRENT_15_mA_T114) | | |
348 | PE_CURRENT2(PE_CURRENT_15_mA_T114) | | |
349 | PE_CURRENT3(PE_CURRENT_15_mA_T114), | |
350 | .drive_current = | |
351 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
352 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
353 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | | |
354 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), | |
355 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | | |
356 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | | |
357 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | | |
358 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), | |
359 | }, { /* 1080p / 148.5MHz modes */ | |
360 | .pclk = 148500000, | |
361 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
362 | SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, | |
363 | .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | | |
364 | SOR_PLL_TMDS_TERMADJ(0), | |
365 | .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | | |
366 | PE_CURRENT1(PE_CURRENT_10_mA_T114) | | |
367 | PE_CURRENT2(PE_CURRENT_10_mA_T114) | | |
368 | PE_CURRENT3(PE_CURRENT_10_mA_T114), | |
369 | .drive_current = | |
370 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | | |
371 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | | |
372 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | | |
373 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), | |
374 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | | |
375 | PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | | |
376 | PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | | |
377 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), | |
378 | }, { /* 225/297MHz modes */ | |
379 | .pclk = UINT_MAX, | |
380 | .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | | |
381 | SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, | |
382 | .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) | |
383 | | SOR_PLL_TMDS_TERM_ENABLE, | |
384 | .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | | |
385 | PE_CURRENT1(PE_CURRENT_0_mA_T114) | | |
386 | PE_CURRENT2(PE_CURRENT_0_mA_T114) | | |
387 | PE_CURRENT3(PE_CURRENT_0_mA_T114), | |
388 | .drive_current = | |
389 | DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | | |
390 | DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | | |
391 | DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | | |
392 | DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), | |
393 | .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | | |
394 | PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | | |
395 | PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | | |
396 | PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), | |
397 | }, | |
398 | }; | |
399 | ||
edec4af4 TR |
400 | static const struct tegra_hdmi_audio_config * |
401 | tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) | |
402 | { | |
403 | const struct tegra_hdmi_audio_config *table; | |
404 | ||
405 | switch (audio_freq) { | |
406 | case 32000: | |
407 | table = tegra_hdmi_audio_32k; | |
408 | break; | |
409 | ||
410 | case 44100: | |
411 | table = tegra_hdmi_audio_44_1k; | |
412 | break; | |
413 | ||
414 | case 48000: | |
415 | table = tegra_hdmi_audio_48k; | |
416 | break; | |
417 | ||
418 | case 88200: | |
419 | table = tegra_hdmi_audio_88_2k; | |
420 | break; | |
421 | ||
422 | case 96000: | |
423 | table = tegra_hdmi_audio_96k; | |
424 | break; | |
425 | ||
426 | case 176400: | |
427 | table = tegra_hdmi_audio_176_4k; | |
428 | break; | |
429 | ||
430 | case 192000: | |
431 | table = tegra_hdmi_audio_192k; | |
432 | break; | |
433 | ||
434 | default: | |
435 | return NULL; | |
436 | } | |
437 | ||
438 | while (table->pclk) { | |
439 | if (table->pclk == pclk) | |
440 | return table; | |
441 | ||
442 | table++; | |
443 | } | |
444 | ||
445 | return NULL; | |
446 | } | |
447 | ||
448 | static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi) | |
449 | { | |
450 | const unsigned int freqs[] = { | |
451 | 32000, 44100, 48000, 88200, 96000, 176400, 192000 | |
452 | }; | |
453 | unsigned int i; | |
454 | ||
455 | for (i = 0; i < ARRAY_SIZE(freqs); i++) { | |
456 | unsigned int f = freqs[i]; | |
457 | unsigned int eight_half; | |
458 | unsigned long value; | |
459 | unsigned int delta; | |
460 | ||
461 | if (f > 96000) | |
462 | delta = 2; | |
17a8b6b0 | 463 | else if (f > 48000) |
edec4af4 TR |
464 | delta = 6; |
465 | else | |
466 | delta = 9; | |
467 | ||
468 | eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); | |
469 | value = AUDIO_FS_LOW(eight_half - delta) | | |
470 | AUDIO_FS_HIGH(eight_half + delta); | |
471 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i)); | |
472 | } | |
473 | } | |
474 | ||
475 | static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk) | |
476 | { | |
477 | struct device_node *node = hdmi->dev->of_node; | |
478 | const struct tegra_hdmi_audio_config *config; | |
479 | unsigned int offset = 0; | |
480 | unsigned long value; | |
481 | ||
482 | switch (hdmi->audio_source) { | |
483 | case HDA: | |
484 | value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL; | |
485 | break; | |
486 | ||
487 | case SPDIF: | |
488 | value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; | |
489 | break; | |
490 | ||
491 | default: | |
492 | value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO; | |
493 | break; | |
494 | } | |
495 | ||
496 | if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { | |
497 | value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) | | |
498 | AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0); | |
499 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); | |
500 | } else { | |
501 | value |= AUDIO_CNTRL0_INJECT_NULLSMPL; | |
502 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); | |
503 | ||
504 | value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) | | |
505 | AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0); | |
506 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); | |
507 | } | |
508 | ||
509 | config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk); | |
510 | if (!config) { | |
511 | dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n", | |
512 | hdmi->audio_freq, pclk); | |
513 | return -EINVAL; | |
514 | } | |
515 | ||
516 | tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL); | |
517 | ||
518 | value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE | | |
519 | AUDIO_N_VALUE(config->n - 1); | |
520 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); | |
521 | ||
522 | tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE, | |
523 | HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); | |
524 | ||
525 | value = ACR_SUBPACK_CTS(config->cts); | |
526 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); | |
527 | ||
528 | value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1); | |
529 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE); | |
530 | ||
531 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N); | |
532 | value &= ~AUDIO_N_RESETF; | |
533 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); | |
534 | ||
535 | if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { | |
536 | switch (hdmi->audio_freq) { | |
537 | case 32000: | |
538 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320; | |
539 | break; | |
540 | ||
541 | case 44100: | |
542 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441; | |
543 | break; | |
544 | ||
545 | case 48000: | |
546 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480; | |
547 | break; | |
548 | ||
549 | case 88200: | |
550 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882; | |
551 | break; | |
552 | ||
553 | case 96000: | |
554 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960; | |
555 | break; | |
556 | ||
557 | case 176400: | |
558 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764; | |
559 | break; | |
560 | ||
561 | case 192000: | |
562 | offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920; | |
563 | break; | |
564 | } | |
565 | ||
566 | tegra_hdmi_writel(hdmi, config->aval, offset); | |
567 | } | |
568 | ||
569 | tegra_hdmi_setup_audio_fs_tables(hdmi); | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
ac24c220 | 574 | static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size) |
edec4af4 | 575 | { |
ac24c220 | 576 | unsigned long value = 0; |
edec4af4 | 577 | size_t i; |
edec4af4 | 578 | |
ac24c220 TR |
579 | for (i = size; i > 0; i--) |
580 | value = (value << 8) | ptr[i - 1]; | |
edec4af4 | 581 | |
ac24c220 TR |
582 | return value; |
583 | } | |
edec4af4 | 584 | |
ac24c220 TR |
585 | static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data, |
586 | size_t size) | |
587 | { | |
588 | const u8 *ptr = data; | |
589 | unsigned long offset; | |
590 | unsigned long value; | |
591 | size_t i, j; | |
edec4af4 | 592 | |
ac24c220 TR |
593 | switch (ptr[0]) { |
594 | case HDMI_INFOFRAME_TYPE_AVI: | |
595 | offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER; | |
596 | break; | |
edec4af4 | 597 | |
ac24c220 TR |
598 | case HDMI_INFOFRAME_TYPE_AUDIO: |
599 | offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER; | |
600 | break; | |
edec4af4 | 601 | |
ac24c220 TR |
602 | case HDMI_INFOFRAME_TYPE_VENDOR: |
603 | offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER; | |
604 | break; | |
605 | ||
606 | default: | |
607 | dev_err(hdmi->dev, "unsupported infoframe type: %02x\n", | |
608 | ptr[0]); | |
609 | return; | |
610 | } | |
edec4af4 | 611 | |
ac24c220 TR |
612 | value = INFOFRAME_HEADER_TYPE(ptr[0]) | |
613 | INFOFRAME_HEADER_VERSION(ptr[1]) | | |
614 | INFOFRAME_HEADER_LEN(ptr[2]); | |
615 | tegra_hdmi_writel(hdmi, value, offset); | |
616 | offset++; | |
edec4af4 | 617 | |
ac24c220 TR |
618 | /* |
619 | * Each subpack contains 7 bytes, divided into: | |
620 | * - subpack_low: bytes 0 - 3 | |
621 | * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) | |
622 | */ | |
623 | for (i = 3, j = 0; i < size; i += 7, j += 8) { | |
624 | size_t rem = size - i, num = min_t(size_t, rem, 4); | |
edec4af4 | 625 | |
ac24c220 TR |
626 | value = tegra_hdmi_subpack(&ptr[i], num); |
627 | tegra_hdmi_writel(hdmi, value, offset++); | |
edec4af4 | 628 | |
ac24c220 TR |
629 | num = min_t(size_t, rem - num, 3); |
630 | ||
631 | value = tegra_hdmi_subpack(&ptr[i + 4], num); | |
632 | tegra_hdmi_writel(hdmi, value, offset++); | |
edec4af4 TR |
633 | } |
634 | } | |
635 | ||
636 | static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi, | |
637 | struct drm_display_mode *mode) | |
638 | { | |
639 | struct hdmi_avi_infoframe frame; | |
ac24c220 TR |
640 | u8 buffer[17]; |
641 | ssize_t err; | |
edec4af4 TR |
642 | |
643 | if (hdmi->dvi) { | |
644 | tegra_hdmi_writel(hdmi, 0, | |
645 | HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); | |
646 | return; | |
647 | } | |
648 | ||
ac24c220 TR |
649 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
650 | if (err < 0) { | |
651 | dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err); | |
652 | return; | |
653 | } | |
edec4af4 | 654 | |
ac24c220 TR |
655 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
656 | if (err < 0) { | |
657 | dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err); | |
658 | return; | |
edec4af4 TR |
659 | } |
660 | ||
ac24c220 | 661 | tegra_hdmi_write_infopack(hdmi, buffer, err); |
edec4af4 TR |
662 | |
663 | tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE, | |
664 | HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); | |
665 | } | |
666 | ||
667 | static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi) | |
668 | { | |
669 | struct hdmi_audio_infoframe frame; | |
ac24c220 TR |
670 | u8 buffer[14]; |
671 | ssize_t err; | |
edec4af4 TR |
672 | |
673 | if (hdmi->dvi) { | |
674 | tegra_hdmi_writel(hdmi, 0, | |
675 | HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); | |
676 | return; | |
677 | } | |
678 | ||
ac24c220 TR |
679 | err = hdmi_audio_infoframe_init(&frame); |
680 | if (err < 0) { | |
ef284c75 | 681 | dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n", |
ac24c220 TR |
682 | err); |
683 | return; | |
684 | } | |
685 | ||
686 | frame.channels = 2; | |
687 | ||
688 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
689 | if (err < 0) { | |
690 | dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n", | |
691 | err); | |
692 | return; | |
693 | } | |
edec4af4 | 694 | |
ac24c220 TR |
695 | /* |
696 | * The audio infoframe has only one set of subpack registers, so the | |
697 | * infoframe needs to be truncated. One set of subpack registers can | |
698 | * contain 7 bytes. Including the 3 byte header only the first 10 | |
699 | * bytes can be programmed. | |
700 | */ | |
ef284c75 | 701 | tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err)); |
edec4af4 TR |
702 | |
703 | tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE, | |
704 | HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); | |
705 | } | |
706 | ||
707 | static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi) | |
708 | { | |
ae84b900 | 709 | struct hdmi_vendor_infoframe frame; |
edec4af4 | 710 | unsigned long value; |
ac24c220 TR |
711 | u8 buffer[10]; |
712 | ssize_t err; | |
edec4af4 TR |
713 | |
714 | if (!hdmi->stereo) { | |
715 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); | |
716 | value &= ~GENERIC_CTRL_ENABLE; | |
717 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); | |
718 | return; | |
719 | } | |
720 | ||
ae84b900 | 721 | hdmi_vendor_infoframe_init(&frame); |
a26a58e8 | 722 | frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING; |
ac24c220 | 723 | |
ae84b900 | 724 | err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); |
ac24c220 TR |
725 | if (err < 0) { |
726 | dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n", | |
727 | err); | |
728 | return; | |
edec4af4 TR |
729 | } |
730 | ||
ac24c220 | 731 | tegra_hdmi_write_infopack(hdmi, buffer, err); |
edec4af4 TR |
732 | |
733 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); | |
734 | value |= GENERIC_CTRL_ENABLE; | |
735 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); | |
736 | } | |
737 | ||
738 | static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, | |
739 | const struct tmds_config *tmds) | |
740 | { | |
741 | unsigned long value; | |
742 | ||
743 | tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); | |
744 | tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); | |
745 | tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT); | |
746 | ||
59af0595 TR |
747 | tegra_hdmi_writel(hdmi, tmds->drive_current, |
748 | HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); | |
749 | ||
750 | value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset); | |
751 | value |= hdmi->config->fuse_override_value; | |
752 | tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset); | |
7d1d28ac MP |
753 | |
754 | if (hdmi->config->has_sor_io_peak_current) | |
755 | tegra_hdmi_writel(hdmi, tmds->peak_current, | |
756 | HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); | |
edec4af4 TR |
757 | } |
758 | ||
9f159123 MP |
759 | static bool tegra_output_is_hdmi(struct tegra_output *output) |
760 | { | |
761 | struct edid *edid; | |
762 | ||
763 | if (!output->connector.edid_blob_ptr) | |
764 | return false; | |
765 | ||
766 | edid = (struct edid *)output->connector.edid_blob_ptr->data; | |
767 | ||
768 | return drm_detect_hdmi_monitor(edid); | |
769 | } | |
770 | ||
edec4af4 TR |
771 | static int tegra_output_hdmi_enable(struct tegra_output *output) |
772 | { | |
773 | unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; | |
774 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); | |
775 | struct drm_display_mode *mode = &dc->base.mode; | |
776 | struct tegra_hdmi *hdmi = to_hdmi(output); | |
777 | struct device_node *node = hdmi->dev->of_node; | |
778 | unsigned int pulse_start, div82, pclk; | |
edec4af4 TR |
779 | unsigned long value; |
780 | int retries = 1000; | |
781 | int err; | |
782 | ||
365765fc TR |
783 | if (hdmi->enabled) |
784 | return 0; | |
785 | ||
9f159123 MP |
786 | hdmi->dvi = !tegra_output_is_hdmi(output); |
787 | ||
edec4af4 TR |
788 | pclk = mode->clock * 1000; |
789 | h_sync_width = mode->hsync_end - mode->hsync_start; | |
40495089 LS |
790 | h_back_porch = mode->htotal - mode->hsync_end; |
791 | h_front_porch = mode->hsync_start - mode->hdisplay; | |
edec4af4 | 792 | |
88685687 | 793 | err = regulator_enable(hdmi->pll); |
fb50a116 | 794 | if (err < 0) { |
88685687 | 795 | dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); |
fb50a116 TR |
796 | return err; |
797 | } | |
798 | ||
88685687 | 799 | err = regulator_enable(hdmi->vdd); |
edec4af4 | 800 | if (err < 0) { |
88685687 | 801 | dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); |
edec4af4 TR |
802 | return err; |
803 | } | |
804 | ||
edec4af4 TR |
805 | err = clk_set_rate(hdmi->clk, pclk); |
806 | if (err < 0) | |
807 | return err; | |
808 | ||
d06e7f8f | 809 | err = clk_prepare_enable(hdmi->clk); |
edec4af4 TR |
810 | if (err < 0) { |
811 | dev_err(hdmi->dev, "failed to enable clock: %d\n", err); | |
812 | return err; | |
813 | } | |
814 | ||
ca48080a | 815 | reset_control_assert(hdmi->rst); |
edec4af4 | 816 | usleep_range(1000, 2000); |
ca48080a | 817 | reset_control_deassert(hdmi->rst); |
edec4af4 | 818 | |
8c8282c0 TR |
819 | /* power up sequence */ |
820 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); | |
821 | value &= ~SOR_PLL_PDBG; | |
822 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); | |
823 | ||
824 | usleep_range(10, 20); | |
825 | ||
826 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); | |
827 | value &= ~SOR_PLL_PWR; | |
828 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); | |
829 | ||
edec4af4 TR |
830 | tegra_dc_writel(dc, VSYNC_H_POSITION(1), |
831 | DC_DISP_DISP_TIMING_OPTIONS); | |
832 | tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888, | |
833 | DC_DISP_DISP_COLOR_CONTROL); | |
834 | ||
835 | /* video_preamble uses h_pulse2 */ | |
836 | pulse_start = 1 + h_sync_width + h_back_porch - 10; | |
837 | ||
838 | tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); | |
839 | ||
840 | value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE | | |
841 | PULSE_LAST_END_A; | |
842 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); | |
843 | ||
844 | value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8); | |
845 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); | |
846 | ||
847 | value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) | | |
848 | VSYNC_WINDOW_ENABLE; | |
849 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); | |
850 | ||
851 | if (dc->pipe) | |
852 | value = HDMI_SRC_DISPLAYB; | |
853 | else | |
854 | value = HDMI_SRC_DISPLAYA; | |
855 | ||
856 | if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) || | |
857 | (mode->vdisplay == 576))) | |
858 | tegra_hdmi_writel(hdmi, | |
859 | value | ARM_VIDEO_RANGE_FULL, | |
860 | HDMI_NV_PDISP_INPUT_CONTROL); | |
861 | else | |
862 | tegra_hdmi_writel(hdmi, | |
863 | value | ARM_VIDEO_RANGE_LIMITED, | |
864 | HDMI_NV_PDISP_INPUT_CONTROL); | |
865 | ||
866 | div82 = clk_get_rate(hdmi->clk) / 1000000 * 4; | |
867 | value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); | |
868 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK); | |
869 | ||
870 | if (!hdmi->dvi) { | |
871 | err = tegra_hdmi_setup_audio(hdmi, pclk); | |
872 | if (err < 0) | |
873 | hdmi->dvi = true; | |
874 | } | |
875 | ||
876 | if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) { | |
877 | /* | |
878 | * TODO: add ELD support | |
879 | */ | |
880 | } | |
881 | ||
882 | rekey = HDMI_REKEY_DEFAULT; | |
883 | value = HDMI_CTRL_REKEY(rekey); | |
884 | value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + | |
885 | h_front_porch - rekey - 18) / 32); | |
886 | ||
887 | if (!hdmi->dvi) | |
888 | value |= HDMI_CTRL_ENABLE; | |
889 | ||
890 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL); | |
891 | ||
892 | if (hdmi->dvi) | |
893 | tegra_hdmi_writel(hdmi, 0x0, | |
894 | HDMI_NV_PDISP_HDMI_GENERIC_CTRL); | |
895 | else | |
896 | tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO, | |
897 | HDMI_NV_PDISP_HDMI_GENERIC_CTRL); | |
898 | ||
899 | tegra_hdmi_setup_avi_infoframe(hdmi, mode); | |
900 | tegra_hdmi_setup_audio_infoframe(hdmi); | |
901 | tegra_hdmi_setup_stereo_infoframe(hdmi); | |
902 | ||
903 | /* TMDS CONFIG */ | |
59af0595 TR |
904 | for (i = 0; i < hdmi->config->num_tmds; i++) { |
905 | if (pclk <= hdmi->config->tmds[i].pclk) { | |
906 | tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]); | |
edec4af4 TR |
907 | break; |
908 | } | |
909 | } | |
910 | ||
911 | tegra_hdmi_writel(hdmi, | |
912 | SOR_SEQ_CTL_PU_PC(0) | | |
913 | SOR_SEQ_PU_PC_ALT(0) | | |
914 | SOR_SEQ_PD_PC(8) | | |
915 | SOR_SEQ_PD_PC_ALT(8), | |
916 | HDMI_NV_PDISP_SOR_SEQ_CTL); | |
917 | ||
918 | value = SOR_SEQ_INST_WAIT_TIME(1) | | |
919 | SOR_SEQ_INST_WAIT_UNITS_VSYNC | | |
920 | SOR_SEQ_INST_HALT | | |
921 | SOR_SEQ_INST_PIN_A_LOW | | |
922 | SOR_SEQ_INST_PIN_B_LOW | | |
923 | SOR_SEQ_INST_DRIVE_PWM_OUT_LO; | |
924 | ||
925 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); | |
926 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); | |
927 | ||
9cbfc73e | 928 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM); |
edec4af4 TR |
929 | value &= ~SOR_CSTM_ROTCLK(~0); |
930 | value |= SOR_CSTM_ROTCLK(2); | |
9cbfc73e TR |
931 | value |= SOR_CSTM_PLLDIV; |
932 | value &= ~SOR_CSTM_LVDS_ENABLE; | |
933 | value &= ~SOR_CSTM_MODE_MASK; | |
934 | value |= SOR_CSTM_MODE_TMDS; | |
edec4af4 TR |
935 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); |
936 | ||
edec4af4 TR |
937 | /* start SOR */ |
938 | tegra_hdmi_writel(hdmi, | |
939 | SOR_PWR_NORMAL_STATE_PU | | |
940 | SOR_PWR_NORMAL_START_NORMAL | | |
941 | SOR_PWR_SAFE_STATE_PD | | |
942 | SOR_PWR_SETTING_NEW_TRIGGER, | |
943 | HDMI_NV_PDISP_SOR_PWR); | |
944 | tegra_hdmi_writel(hdmi, | |
945 | SOR_PWR_NORMAL_STATE_PU | | |
946 | SOR_PWR_NORMAL_START_NORMAL | | |
947 | SOR_PWR_SAFE_STATE_PD | | |
948 | SOR_PWR_SETTING_NEW_DONE, | |
949 | HDMI_NV_PDISP_SOR_PWR); | |
950 | ||
951 | do { | |
952 | BUG_ON(--retries < 0); | |
953 | value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR); | |
954 | } while (value & SOR_PWR_SETTING_NEW_PENDING); | |
955 | ||
956 | value = SOR_STATE_ASY_CRCMODE_COMPLETE | | |
957 | SOR_STATE_ASY_OWNER_HEAD0 | | |
958 | SOR_STATE_ASY_SUBOWNER_BOTH | | |
959 | SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A | | |
960 | SOR_STATE_ASY_DEPOL_POS; | |
961 | ||
962 | /* setup sync polarities */ | |
963 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) | |
964 | value |= SOR_STATE_ASY_HSYNCPOL_POS; | |
965 | ||
966 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
967 | value |= SOR_STATE_ASY_HSYNCPOL_NEG; | |
968 | ||
969 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
970 | value |= SOR_STATE_ASY_VSYNCPOL_POS; | |
971 | ||
972 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
973 | value |= SOR_STATE_ASY_VSYNCPOL_NEG; | |
974 | ||
975 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2); | |
976 | ||
977 | value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL; | |
978 | tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1); | |
979 | ||
980 | tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); | |
981 | tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0); | |
982 | tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED, | |
983 | HDMI_NV_PDISP_SOR_STATE1); | |
984 | tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); | |
985 | ||
72d30286 TR |
986 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
987 | value |= HDMI_ENABLE; | |
988 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
edec4af4 | 989 | |
72d30286 TR |
990 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); |
991 | value &= ~DISP_CTRL_MODE_MASK; | |
992 | value |= DISP_CTRL_MODE_C_DISPLAY; | |
edec4af4 TR |
993 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); |
994 | ||
72d30286 TR |
995 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
996 | value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
997 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; | |
998 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
999 | ||
edec4af4 TR |
1000 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
1001 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
1002 | ||
1003 | /* TODO: add HDCP support */ | |
1004 | ||
365765fc TR |
1005 | hdmi->enabled = true; |
1006 | ||
edec4af4 TR |
1007 | return 0; |
1008 | } | |
1009 | ||
1010 | static int tegra_output_hdmi_disable(struct tegra_output *output) | |
1011 | { | |
72d30286 | 1012 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
edec4af4 | 1013 | struct tegra_hdmi *hdmi = to_hdmi(output); |
72d30286 | 1014 | unsigned long value; |
edec4af4 | 1015 | |
365765fc TR |
1016 | if (!hdmi->enabled) |
1017 | return 0; | |
1018 | ||
72d30286 TR |
1019 | /* |
1020 | * The following accesses registers of the display controller, so make | |
1021 | * sure it's only executed when the output is attached to one. | |
1022 | */ | |
1023 | if (dc) { | |
7e246430 TR |
1024 | /* |
1025 | * XXX: We can't do this here because it causes HDMI to go | |
1026 | * into an erroneous state with the result that HDMI won't | |
1027 | * properly work once disabled. See also a similar symptom | |
1028 | * for the SOR output. | |
1029 | */ | |
1030 | /* | |
72d30286 TR |
1031 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
1032 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | | |
1033 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); | |
1034 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); | |
7e246430 | 1035 | */ |
72d30286 TR |
1036 | |
1037 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); | |
1038 | value &= ~DISP_CTRL_MODE_MASK; | |
1039 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); | |
1040 | ||
1041 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); | |
1042 | value &= ~HDMI_ENABLE; | |
1043 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); | |
1044 | ||
1045 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); | |
1046 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); | |
1047 | } | |
1048 | ||
d06e7f8f | 1049 | clk_disable_unprepare(hdmi->clk); |
ca48080a | 1050 | reset_control_assert(hdmi->rst); |
fb50a116 | 1051 | regulator_disable(hdmi->vdd); |
88685687 | 1052 | regulator_disable(hdmi->pll); |
edec4af4 | 1053 | |
365765fc TR |
1054 | hdmi->enabled = false; |
1055 | ||
edec4af4 TR |
1056 | return 0; |
1057 | } | |
1058 | ||
1059 | static int tegra_output_hdmi_setup_clock(struct tegra_output *output, | |
91eded9b TR |
1060 | struct clk *clk, unsigned long pclk, |
1061 | unsigned int *div) | |
edec4af4 TR |
1062 | { |
1063 | struct tegra_hdmi *hdmi = to_hdmi(output); | |
edec4af4 TR |
1064 | int err; |
1065 | ||
1066 | err = clk_set_parent(clk, hdmi->clk_parent); | |
1067 | if (err < 0) { | |
1068 | dev_err(output->dev, "failed to set parent: %d\n", err); | |
1069 | return err; | |
1070 | } | |
1071 | ||
91eded9b | 1072 | err = clk_set_rate(hdmi->clk_parent, pclk); |
edec4af4 | 1073 | if (err < 0) |
91eded9b TR |
1074 | dev_err(output->dev, "failed to set clock rate to %lu Hz\n", |
1075 | pclk); | |
1076 | ||
1077 | *div = 0; | |
edec4af4 TR |
1078 | |
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | static int tegra_output_hdmi_check_mode(struct tegra_output *output, | |
1083 | struct drm_display_mode *mode, | |
1084 | enum drm_mode_status *status) | |
1085 | { | |
1086 | struct tegra_hdmi *hdmi = to_hdmi(output); | |
1087 | unsigned long pclk = mode->clock * 1000; | |
1088 | struct clk *parent; | |
1089 | long err; | |
1090 | ||
1091 | parent = clk_get_parent(hdmi->clk_parent); | |
1092 | ||
1093 | err = clk_round_rate(parent, pclk * 4); | |
23a0e27a | 1094 | if (err <= 0) |
edec4af4 TR |
1095 | *status = MODE_NOCLOCK; |
1096 | else | |
1097 | *status = MODE_OK; | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static const struct tegra_output_ops hdmi_ops = { | |
1103 | .enable = tegra_output_hdmi_enable, | |
1104 | .disable = tegra_output_hdmi_disable, | |
1105 | .setup_clock = tegra_output_hdmi_setup_clock, | |
1106 | .check_mode = tegra_output_hdmi_check_mode, | |
1107 | }; | |
1108 | ||
1109 | static int tegra_hdmi_show_regs(struct seq_file *s, void *data) | |
1110 | { | |
1111 | struct drm_info_node *node = s->private; | |
1112 | struct tegra_hdmi *hdmi = node->info_ent->data; | |
ccaddfe1 MP |
1113 | int err; |
1114 | ||
d06e7f8f | 1115 | err = clk_prepare_enable(hdmi->clk); |
ccaddfe1 MP |
1116 | if (err) |
1117 | return err; | |
edec4af4 TR |
1118 | |
1119 | #define DUMP_REG(name) \ | |
1120 | seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \ | |
1121 | tegra_hdmi_readl(hdmi, name)) | |
1122 | ||
1123 | DUMP_REG(HDMI_CTXSW); | |
1124 | DUMP_REG(HDMI_NV_PDISP_SOR_STATE0); | |
1125 | DUMP_REG(HDMI_NV_PDISP_SOR_STATE1); | |
1126 | DUMP_REG(HDMI_NV_PDISP_SOR_STATE2); | |
1127 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB); | |
1128 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB); | |
1129 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB); | |
1130 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB); | |
1131 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB); | |
1132 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB); | |
1133 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB); | |
1134 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB); | |
1135 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB); | |
1136 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB); | |
1137 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB); | |
1138 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB); | |
1139 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL); | |
1140 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE); | |
1141 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB); | |
1142 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB); | |
1143 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB); | |
1144 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2); | |
1145 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1); | |
1146 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI); | |
1147 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB); | |
1148 | DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB); | |
1149 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0); | |
1150 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0); | |
1151 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1); | |
1152 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2); | |
1153 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); | |
1154 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS); | |
1155 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER); | |
1156 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW); | |
1157 | DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH); | |
1158 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); | |
1159 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS); | |
1160 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER); | |
1161 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW); | |
1162 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH); | |
1163 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW); | |
1164 | DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH); | |
1165 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL); | |
1166 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS); | |
1167 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER); | |
1168 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW); | |
1169 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH); | |
1170 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW); | |
1171 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH); | |
1172 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW); | |
1173 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH); | |
1174 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW); | |
1175 | DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH); | |
1176 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL); | |
1177 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW); | |
1178 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH); | |
1179 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); | |
1180 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); | |
1181 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW); | |
1182 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH); | |
1183 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW); | |
1184 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH); | |
1185 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW); | |
1186 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH); | |
1187 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW); | |
1188 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH); | |
1189 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW); | |
1190 | DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH); | |
1191 | DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL); | |
1192 | DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT); | |
1193 | DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); | |
1194 | DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL); | |
1195 | DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS); | |
1196 | DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK); | |
1197 | DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1); | |
1198 | DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2); | |
1199 | DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0); | |
1200 | DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1); | |
1201 | DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA); | |
1202 | DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE); | |
1203 | DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1); | |
1204 | DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2); | |
1205 | DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL); | |
1206 | DUMP_REG(HDMI_NV_PDISP_SOR_CAP); | |
1207 | DUMP_REG(HDMI_NV_PDISP_SOR_PWR); | |
1208 | DUMP_REG(HDMI_NV_PDISP_SOR_TEST); | |
1209 | DUMP_REG(HDMI_NV_PDISP_SOR_PLL0); | |
1210 | DUMP_REG(HDMI_NV_PDISP_SOR_PLL1); | |
1211 | DUMP_REG(HDMI_NV_PDISP_SOR_PLL2); | |
1212 | DUMP_REG(HDMI_NV_PDISP_SOR_CSTM); | |
1213 | DUMP_REG(HDMI_NV_PDISP_SOR_LVDS); | |
1214 | DUMP_REG(HDMI_NV_PDISP_SOR_CRCA); | |
1215 | DUMP_REG(HDMI_NV_PDISP_SOR_CRCB); | |
1216 | DUMP_REG(HDMI_NV_PDISP_SOR_BLANK); | |
1217 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL); | |
1218 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0)); | |
1219 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1)); | |
1220 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2)); | |
1221 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3)); | |
1222 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4)); | |
1223 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5)); | |
1224 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6)); | |
1225 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7)); | |
1226 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8)); | |
1227 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9)); | |
1228 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10)); | |
1229 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11)); | |
1230 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12)); | |
1231 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13)); | |
1232 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14)); | |
1233 | DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15)); | |
1234 | DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0); | |
1235 | DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1); | |
1236 | DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0); | |
1237 | DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1); | |
1238 | DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0); | |
1239 | DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1); | |
1240 | DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0); | |
1241 | DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1); | |
1242 | DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0); | |
1243 | DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1); | |
1244 | DUMP_REG(HDMI_NV_PDISP_SOR_TRIG); | |
1245 | DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK); | |
1246 | DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); | |
1247 | DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0); | |
1248 | DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1); | |
1249 | DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2); | |
1250 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0)); | |
1251 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1)); | |
1252 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2)); | |
1253 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3)); | |
1254 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4)); | |
1255 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5)); | |
1256 | DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6)); | |
1257 | DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH); | |
1258 | DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD); | |
1259 | DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0); | |
1260 | DUMP_REG(HDMI_NV_PDISP_AUDIO_N); | |
1261 | DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING); | |
1262 | DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK); | |
1263 | DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL); | |
1264 | DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL); | |
1265 | DUMP_REG(HDMI_NV_PDISP_SCRATCH); | |
1266 | DUMP_REG(HDMI_NV_PDISP_PE_CURRENT); | |
1267 | DUMP_REG(HDMI_NV_PDISP_KEY_CTRL); | |
1268 | DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0); | |
1269 | DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1); | |
1270 | DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2); | |
1271 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0); | |
1272 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1); | |
1273 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2); | |
1274 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3); | |
1275 | DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG); | |
1276 | DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX); | |
1277 | DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); | |
1278 | DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); | |
1279 | DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); | |
7d1d28ac | 1280 | DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); |
edec4af4 TR |
1281 | |
1282 | #undef DUMP_REG | |
1283 | ||
d06e7f8f | 1284 | clk_disable_unprepare(hdmi->clk); |
ccaddfe1 | 1285 | |
edec4af4 TR |
1286 | return 0; |
1287 | } | |
1288 | ||
1289 | static struct drm_info_list debugfs_files[] = { | |
1290 | { "regs", tegra_hdmi_show_regs, 0, NULL }, | |
1291 | }; | |
1292 | ||
1293 | static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi, | |
1294 | struct drm_minor *minor) | |
1295 | { | |
1296 | unsigned int i; | |
1297 | int err; | |
1298 | ||
1299 | hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root); | |
1300 | if (!hdmi->debugfs) | |
1301 | return -ENOMEM; | |
1302 | ||
1303 | hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), | |
1304 | GFP_KERNEL); | |
1305 | if (!hdmi->debugfs_files) { | |
1306 | err = -ENOMEM; | |
1307 | goto remove; | |
1308 | } | |
1309 | ||
1310 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) | |
1311 | hdmi->debugfs_files[i].data = hdmi; | |
1312 | ||
1313 | err = drm_debugfs_create_files(hdmi->debugfs_files, | |
1314 | ARRAY_SIZE(debugfs_files), | |
1315 | hdmi->debugfs, minor); | |
1316 | if (err < 0) | |
1317 | goto free; | |
1318 | ||
1319 | hdmi->minor = minor; | |
1320 | ||
1321 | return 0; | |
1322 | ||
1323 | free: | |
1324 | kfree(hdmi->debugfs_files); | |
1325 | hdmi->debugfs_files = NULL; | |
1326 | remove: | |
1327 | debugfs_remove(hdmi->debugfs); | |
1328 | hdmi->debugfs = NULL; | |
1329 | ||
1330 | return err; | |
1331 | } | |
1332 | ||
1333 | static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi) | |
1334 | { | |
1335 | drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files), | |
1336 | hdmi->minor); | |
1337 | hdmi->minor = NULL; | |
1338 | ||
1339 | kfree(hdmi->debugfs_files); | |
1340 | hdmi->debugfs_files = NULL; | |
1341 | ||
1342 | debugfs_remove(hdmi->debugfs); | |
1343 | hdmi->debugfs = NULL; | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
53fa7f72 | 1348 | static int tegra_hdmi_init(struct host1x_client *client) |
edec4af4 | 1349 | { |
9910f5c4 | 1350 | struct drm_device *drm = dev_get_drvdata(client->parent); |
776dc384 | 1351 | struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); |
edec4af4 TR |
1352 | int err; |
1353 | ||
1354 | hdmi->output.type = TEGRA_OUTPUT_HDMI; | |
1355 | hdmi->output.dev = client->dev; | |
1356 | hdmi->output.ops = &hdmi_ops; | |
1357 | ||
9910f5c4 | 1358 | err = tegra_output_init(drm, &hdmi->output); |
edec4af4 TR |
1359 | if (err < 0) { |
1360 | dev_err(client->dev, "output setup failed: %d\n", err); | |
1361 | return err; | |
1362 | } | |
1363 | ||
1364 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
9910f5c4 | 1365 | err = tegra_hdmi_debugfs_init(hdmi, drm->primary); |
edec4af4 TR |
1366 | if (err < 0) |
1367 | dev_err(client->dev, "debugfs setup failed: %d\n", err); | |
1368 | } | |
1369 | ||
fb50a116 TR |
1370 | err = regulator_enable(hdmi->hdmi); |
1371 | if (err < 0) { | |
1372 | dev_err(client->dev, "failed to enable HDMI regulator: %d\n", | |
1373 | err); | |
1374 | return err; | |
1375 | } | |
1376 | ||
edec4af4 TR |
1377 | return 0; |
1378 | } | |
1379 | ||
53fa7f72 | 1380 | static int tegra_hdmi_exit(struct host1x_client *client) |
edec4af4 | 1381 | { |
776dc384 | 1382 | struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); |
edec4af4 TR |
1383 | int err; |
1384 | ||
fb50a116 TR |
1385 | regulator_disable(hdmi->hdmi); |
1386 | ||
edec4af4 TR |
1387 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
1388 | err = tegra_hdmi_debugfs_exit(hdmi); | |
1389 | if (err < 0) | |
1390 | dev_err(client->dev, "debugfs cleanup failed: %d\n", | |
1391 | err); | |
1392 | } | |
1393 | ||
1394 | err = tegra_output_disable(&hdmi->output); | |
1395 | if (err < 0) { | |
1396 | dev_err(client->dev, "output failed to disable: %d\n", err); | |
1397 | return err; | |
1398 | } | |
1399 | ||
1400 | err = tegra_output_exit(&hdmi->output); | |
1401 | if (err < 0) { | |
1402 | dev_err(client->dev, "output cleanup failed: %d\n", err); | |
1403 | return err; | |
1404 | } | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static const struct host1x_client_ops hdmi_client_ops = { | |
53fa7f72 TR |
1410 | .init = tegra_hdmi_init, |
1411 | .exit = tegra_hdmi_exit, | |
edec4af4 TR |
1412 | }; |
1413 | ||
59af0595 TR |
1414 | static const struct tegra_hdmi_config tegra20_hdmi_config = { |
1415 | .tmds = tegra20_tmds_config, | |
1416 | .num_tmds = ARRAY_SIZE(tegra20_tmds_config), | |
1417 | .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, | |
1418 | .fuse_override_value = 1 << 31, | |
7d1d28ac | 1419 | .has_sor_io_peak_current = false, |
59af0595 TR |
1420 | }; |
1421 | ||
1422 | static const struct tegra_hdmi_config tegra30_hdmi_config = { | |
1423 | .tmds = tegra30_tmds_config, | |
1424 | .num_tmds = ARRAY_SIZE(tegra30_tmds_config), | |
1425 | .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, | |
1426 | .fuse_override_value = 1 << 31, | |
7d1d28ac MP |
1427 | .has_sor_io_peak_current = false, |
1428 | }; | |
1429 | ||
1430 | static const struct tegra_hdmi_config tegra114_hdmi_config = { | |
1431 | .tmds = tegra114_tmds_config, | |
1432 | .num_tmds = ARRAY_SIZE(tegra114_tmds_config), | |
1433 | .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, | |
1434 | .fuse_override_value = 1 << 31, | |
1435 | .has_sor_io_peak_current = true, | |
59af0595 TR |
1436 | }; |
1437 | ||
fb7be70e TR |
1438 | static const struct tegra_hdmi_config tegra124_hdmi_config = { |
1439 | .tmds = tegra124_tmds_config, | |
1440 | .num_tmds = ARRAY_SIZE(tegra124_tmds_config), | |
1441 | .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, | |
1442 | .fuse_override_value = 1 << 31, | |
1443 | .has_sor_io_peak_current = true, | |
1444 | }; | |
1445 | ||
59af0595 | 1446 | static const struct of_device_id tegra_hdmi_of_match[] = { |
fb7be70e | 1447 | { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config }, |
7d1d28ac | 1448 | { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config }, |
59af0595 TR |
1449 | { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config }, |
1450 | { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, | |
1451 | { }, | |
1452 | }; | |
ef70728c | 1453 | MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match); |
59af0595 | 1454 | |
edec4af4 TR |
1455 | static int tegra_hdmi_probe(struct platform_device *pdev) |
1456 | { | |
59af0595 | 1457 | const struct of_device_id *match; |
edec4af4 TR |
1458 | struct tegra_hdmi *hdmi; |
1459 | struct resource *regs; | |
1460 | int err; | |
1461 | ||
59af0595 TR |
1462 | match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node); |
1463 | if (!match) | |
1464 | return -ENODEV; | |
1465 | ||
edec4af4 TR |
1466 | hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); |
1467 | if (!hdmi) | |
1468 | return -ENOMEM; | |
1469 | ||
59af0595 | 1470 | hdmi->config = match->data; |
edec4af4 TR |
1471 | hdmi->dev = &pdev->dev; |
1472 | hdmi->audio_source = AUTO; | |
1473 | hdmi->audio_freq = 44100; | |
1474 | hdmi->stereo = false; | |
1475 | hdmi->dvi = false; | |
1476 | ||
1477 | hdmi->clk = devm_clk_get(&pdev->dev, NULL); | |
1478 | if (IS_ERR(hdmi->clk)) { | |
1479 | dev_err(&pdev->dev, "failed to get clock\n"); | |
1480 | return PTR_ERR(hdmi->clk); | |
1481 | } | |
1482 | ||
ca48080a SW |
1483 | hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi"); |
1484 | if (IS_ERR(hdmi->rst)) { | |
1485 | dev_err(&pdev->dev, "failed to get reset\n"); | |
1486 | return PTR_ERR(hdmi->rst); | |
1487 | } | |
1488 | ||
edec4af4 TR |
1489 | hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent"); |
1490 | if (IS_ERR(hdmi->clk_parent)) | |
1491 | return PTR_ERR(hdmi->clk_parent); | |
1492 | ||
edec4af4 TR |
1493 | err = clk_set_parent(hdmi->clk, hdmi->clk_parent); |
1494 | if (err < 0) { | |
1495 | dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); | |
1496 | return err; | |
1497 | } | |
1498 | ||
fb50a116 TR |
1499 | hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi"); |
1500 | if (IS_ERR(hdmi->hdmi)) { | |
1501 | dev_err(&pdev->dev, "failed to get HDMI regulator\n"); | |
1502 | return PTR_ERR(hdmi->hdmi); | |
1503 | } | |
1504 | ||
edec4af4 TR |
1505 | hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); |
1506 | if (IS_ERR(hdmi->pll)) { | |
1507 | dev_err(&pdev->dev, "failed to get PLL regulator\n"); | |
1508 | return PTR_ERR(hdmi->pll); | |
1509 | } | |
1510 | ||
88685687 TR |
1511 | hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); |
1512 | if (IS_ERR(hdmi->vdd)) { | |
1513 | dev_err(&pdev->dev, "failed to get VDD regulator\n"); | |
1514 | return PTR_ERR(hdmi->vdd); | |
1515 | } | |
1516 | ||
edec4af4 TR |
1517 | hdmi->output.dev = &pdev->dev; |
1518 | ||
59d29c0e | 1519 | err = tegra_output_probe(&hdmi->output); |
edec4af4 TR |
1520 | if (err < 0) |
1521 | return err; | |
1522 | ||
1523 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1524 | hdmi->regs = devm_ioremap_resource(&pdev->dev, regs); |
1525 | if (IS_ERR(hdmi->regs)) | |
1526 | return PTR_ERR(hdmi->regs); | |
edec4af4 TR |
1527 | |
1528 | err = platform_get_irq(pdev, 0); | |
1529 | if (err < 0) | |
1530 | return err; | |
1531 | ||
1532 | hdmi->irq = err; | |
1533 | ||
776dc384 TR |
1534 | INIT_LIST_HEAD(&hdmi->client.list); |
1535 | hdmi->client.ops = &hdmi_client_ops; | |
1536 | hdmi->client.dev = &pdev->dev; | |
edec4af4 | 1537 | |
776dc384 | 1538 | err = host1x_client_register(&hdmi->client); |
edec4af4 TR |
1539 | if (err < 0) { |
1540 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", | |
1541 | err); | |
1542 | return err; | |
1543 | } | |
1544 | ||
1545 | platform_set_drvdata(pdev, hdmi); | |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
1550 | static int tegra_hdmi_remove(struct platform_device *pdev) | |
1551 | { | |
edec4af4 TR |
1552 | struct tegra_hdmi *hdmi = platform_get_drvdata(pdev); |
1553 | int err; | |
1554 | ||
776dc384 | 1555 | err = host1x_client_unregister(&hdmi->client); |
edec4af4 TR |
1556 | if (err < 0) { |
1557 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", | |
1558 | err); | |
1559 | return err; | |
1560 | } | |
1561 | ||
59d29c0e TR |
1562 | err = tegra_output_remove(&hdmi->output); |
1563 | if (err < 0) { | |
1564 | dev_err(&pdev->dev, "failed to remove output: %d\n", err); | |
1565 | return err; | |
1566 | } | |
1567 | ||
d06e7f8f TR |
1568 | clk_disable_unprepare(hdmi->clk_parent); |
1569 | clk_disable_unprepare(hdmi->clk); | |
edec4af4 TR |
1570 | |
1571 | return 0; | |
1572 | } | |
1573 | ||
edec4af4 TR |
1574 | struct platform_driver tegra_hdmi_driver = { |
1575 | .driver = { | |
1576 | .name = "tegra-hdmi", | |
1577 | .owner = THIS_MODULE, | |
1578 | .of_match_table = tegra_hdmi_of_match, | |
1579 | }, | |
1580 | .probe = tegra_hdmi_probe, | |
1581 | .remove = tegra_hdmi_remove, | |
1582 | }; |