projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| edec4af4 TR |
1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH | |
| 3 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | */ | |
| 9 | ||
| 10 | #ifndef TEGRA_HDMI_H | |
| 11 | #define TEGRA_HDMI_H 1 | |
| 12 | ||
| edec4af4 TR |
13 | /* register definitions */ |
| 14 | #define HDMI_CTXSW 0x00 | |
| 15 | ||
| 16 | #define HDMI_NV_PDISP_SOR_STATE0 0x01 | |
| 17 | #define SOR_STATE_UPDATE (1 << 0) | |
| 18 | ||
| 19 | #define HDMI_NV_PDISP_SOR_STATE1 0x02 | |
| 20 | #define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0) | |
| 21 | #define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2) | |
| 22 | #define SOR_STATE_ATTACHED (1 << 3) | |
| 23 | ||
| 24 | #define HDMI_NV_PDISP_SOR_STATE2 0x03 | |
| 25 | #define SOR_STATE_ASY_OWNER_NONE (0 << 0) | |
| 26 | #define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0) | |
| 27 | #define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4) | |
| 28 | #define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4) | |
| 29 | #define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4) | |
| 30 | #define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4) | |
| 31 | #define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6) | |
| 32 | #define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6) | |
| 33 | #define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6) | |
| 34 | #define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8) | |
| 35 | #define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8) | |
| 36 | #define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12) | |
| 37 | #define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12) | |
| 38 | #define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13) | |
| 39 | #define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13) | |
| 40 | #define SOR_STATE_ASY_DEPOL_POS (0 << 14) | |
| 41 | #define SOR_STATE_ASY_DEPOL_NEG (1 << 14) | |
| 42 | ||
| 43 | #define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04 | |
| 44 | #define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05 | |
| 45 | #define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06 | |
| 46 | #define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07 | |
| 47 | #define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08 | |
| 48 | #define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09 | |
| 49 | #define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a | |
| 50 | #define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b | |
| 51 | #define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c | |
| 52 | #define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d | |
| 53 | #define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e | |
| 54 | #define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f | |
| 55 | #define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10 | |
| 56 | #define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11 | |
| 57 | #define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12 | |
| 58 | #define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13 | |
| 59 | #define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14 | |
| 60 | #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15 | |
| 61 | #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16 | |
| 62 | #define HDMI_NV_PDISP_RG_HDCP_RI 0x17 | |
| 63 | #define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18 | |
| 64 | #define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19 | |
| 65 | #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a | |
| 66 | #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b | |
| 67 | #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c | |
| 68 | #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d | |
| 69 | ||
| 70 | #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e | |
| 71 | #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f | |
| 72 | #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20 | |
| 73 | #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21 | |
| 74 | #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22 | |
| 75 | #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23 | |
| 76 | #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24 | |
| 77 | #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25 | |
| 78 | #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26 | |
| 79 | #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27 | |
| 80 | #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28 | |
| 81 | #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29 | |
| 82 | ||
| 83 | #define INFOFRAME_CTRL_ENABLE (1 << 0) | |
| 84 | ||
| 85 | #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) | |
| 86 | #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) | |
| 87 | #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) | |
| 88 | ||
| 89 | #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a | |
| 90 | #define GENERIC_CTRL_ENABLE (1 << 0) | |
| 91 | #define GENERIC_CTRL_OTHER (1 << 4) | |
| 92 | #define GENERIC_CTRL_SINGLE (1 << 8) | |
| 93 | #define GENERIC_CTRL_HBLANK (1 << 12) | |
| 94 | #define GENERIC_CTRL_AUDIO (1 << 16) | |
| 95 | ||
| 96 | #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b | |
| 97 | #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c | |
| 98 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d | |
| 99 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e | |
| 100 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f | |
| 101 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30 | |
| 102 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31 | |
| 103 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32 | |
| 104 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33 | |
| 105 | #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34 | |
| 106 | ||
| 107 | #define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35 | |
| 108 | #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36 | |
| 109 | #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37 | |
| 110 | #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38 | |
| 111 | #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39 | |
| 112 | #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a | |
| 113 | #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b | |
| 114 | #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c | |
| 115 | #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d | |
| 116 | #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e | |
| 117 | #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f | |
| 118 | #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40 | |
| 119 | #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41 | |
| 120 | #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42 | |
| 121 | #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43 | |
| 122 | ||
| 123 | #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8) | |
| 124 | #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0) | |
| 125 | #define ACR_ENABLE (1 << 31) | |
| 126 | ||
| 127 | #define HDMI_NV_PDISP_HDMI_CTRL 0x44 | |
| 128 | #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0) | |
| 129 | #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16) | |
| 130 | #define HDMI_CTRL_ENABLE (1 << 30) | |
| 131 | ||
| 132 | #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45 | |
| 133 | #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46 | |
| 134 | #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0) | |
| 135 | #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16) | |
| 136 | #define VSYNC_WINDOW_ENABLE (1 << 31) | |
| 137 | ||
| 138 | #define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47 | |
| 139 | #define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48 | |
| 140 | #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49 | |
| 141 | #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a | |
| 142 | #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b | |
| 143 | #define HDMI_NV_PDISP_HDMI_EMU0 0x4c | |
| 144 | #define HDMI_NV_PDISP_HDMI_EMU1 0x4d | |
| 145 | #define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e | |
| 146 | ||
| 147 | #define HDMI_NV_PDISP_HDMI_SPARE 0x4f | |
| 148 | #define SPARE_HW_CTS (1 << 0) | |
| 149 | #define SPARE_FORCE_SW_CTS (1 << 1) | |
| 150 | #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16) | |
| 151 | ||
| 152 | #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50 | |
| 153 | #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51 | |
| 154 | #define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL 0x53 | |
| 155 | #define HDMI_NV_PDISP_SOR_CAP 0x54 | |
| 156 | #define HDMI_NV_PDISP_SOR_PWR 0x55 | |
| 157 | #define SOR_PWR_NORMAL_STATE_PD (0 << 0) | |
| 158 | #define SOR_PWR_NORMAL_STATE_PU (1 << 0) | |
| 159 | #define SOR_PWR_NORMAL_START_NORMAL (0 << 1) | |
| 160 | #define SOR_PWR_NORMAL_START_ALT (1 << 1) | |
| 161 | #define SOR_PWR_SAFE_STATE_PD (0 << 16) | |
| 162 | #define SOR_PWR_SAFE_STATE_PU (1 << 16) | |
| 163 | #define SOR_PWR_SETTING_NEW_DONE (0 << 31) | |
| 164 | #define SOR_PWR_SETTING_NEW_PENDING (1 << 31) | |
| 165 | #define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31) | |
| 166 | ||
| 167 | #define HDMI_NV_PDISP_SOR_TEST 0x56 | |
| 168 | #define HDMI_NV_PDISP_SOR_PLL0 0x57 | |
| 169 | #define SOR_PLL_PWR (1 << 0) | |
| 170 | #define SOR_PLL_PDBG (1 << 1) | |
| 171 | #define SOR_PLL_VCAPD (1 << 2) | |
| 172 | #define SOR_PLL_PDPORT (1 << 3) | |
| 173 | #define SOR_PLL_RESISTORSEL (1 << 4) | |
| 174 | #define SOR_PLL_PULLDOWN (1 << 5) | |
| 175 | #define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8) | |
| 176 | #define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12) | |
| 177 | #define SOR_PLL_FILTER(x) (((x) & 0xf) << 16) | |
| 178 | #define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24) | |
| 179 | #define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28) | |
| 180 | ||
| 181 | #define HDMI_NV_PDISP_SOR_PLL1 0x58 | |
| 182 | #define SOR_PLL_TMDS_TERM_ENABLE (1 << 8) | |
| 183 | #define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9) | |
| 184 | #define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20) | |
| 185 | #define SOR_PLL_PE_EN (1 << 28) | |
| 186 | #define SOR_PLL_HALF_FULL_PE (1 << 29) | |
| 187 | #define SOR_PLL_S_D_PIN_PE (1 << 30) | |
| 188 | ||
| 189 | #define HDMI_NV_PDISP_SOR_PLL2 0x59 | |
| 190 | ||
| 191 | #define HDMI_NV_PDISP_SOR_CSTM 0x5a | |
| 192 | #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24) | |
| 193 | ||
| 194 | #define HDMI_NV_PDISP_SOR_LVDS 0x5b | |
| 195 | #define HDMI_NV_PDISP_SOR_CRCA 0x5c | |
| 196 | #define HDMI_NV_PDISP_SOR_CRCB 0x5d | |
| 197 | #define HDMI_NV_PDISP_SOR_BLANK 0x5e | |
| 198 | #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f | |
| 199 | #define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0) | |
| 200 | #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4) | |
| 201 | #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8) | |
| 202 | #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12) | |
| 203 | #define SOR_SEQ_PC(x) (((x) & 0xf) << 16) | |
| 204 | #define SOR_SEQ_STATUS (1 << 28) | |
| 205 | #define SOR_SEQ_SWITCH (1 << 30) | |
| 206 | ||
| 207 | #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x)) | |
| 208 | ||
| 209 | #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0) | |
| 210 | #define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12) | |
| 211 | #define SOR_SEQ_INST_HALT (1 << 15) | |
| 212 | #define SOR_SEQ_INST_PIN_A_LOW (0 << 21) | |
| 213 | #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21) | |
| 214 | #define SOR_SEQ_INST_PIN_B_LOW (0 << 22) | |
| 215 | #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22) | |
| 216 | #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23) | |
| 217 | ||
| 218 | #define HDMI_NV_PDISP_SOR_VCRCA0 0x72 | |
| 219 | #define HDMI_NV_PDISP_SOR_VCRCA1 0x73 | |
| 220 | #define HDMI_NV_PDISP_SOR_CCRCA0 0x74 | |
| 221 | #define HDMI_NV_PDISP_SOR_CCRCA1 0x75 | |
| 222 | #define HDMI_NV_PDISP_SOR_EDATAA0 0x76 | |
| 223 | #define HDMI_NV_PDISP_SOR_EDATAA1 0x77 | |
| 224 | #define HDMI_NV_PDISP_SOR_COUNTA0 0x78 | |
| 225 | #define HDMI_NV_PDISP_SOR_COUNTA1 0x79 | |
| 226 | #define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a | |
| 227 | #define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b | |
| 228 | #define HDMI_NV_PDISP_SOR_TRIG 0x7c | |
| 229 | #define HDMI_NV_PDISP_SOR_MSCHECK 0x7d | |
| 230 | ||
| 231 | #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e | |
| 232 | #define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0) | |
| 233 | #define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8) | |
| 234 | #define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16) | |
| 235 | #define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24) | |
| edec4af4 TR |
236 | |
| 237 | #define DRIVE_CURRENT_1_500_mA 0x00 | |
| 238 | #define DRIVE_CURRENT_1_875_mA 0x01 | |
| 239 | #define DRIVE_CURRENT_2_250_mA 0x02 | |
| 240 | #define DRIVE_CURRENT_2_625_mA 0x03 | |
| 241 | #define DRIVE_CURRENT_3_000_mA 0x04 | |
| 242 | #define DRIVE_CURRENT_3_375_mA 0x05 | |
| 243 | #define DRIVE_CURRENT_3_750_mA 0x06 | |
| 244 | #define DRIVE_CURRENT_4_125_mA 0x07 | |
| 245 | #define DRIVE_CURRENT_4_500_mA 0x08 | |
| 246 | #define DRIVE_CURRENT_4_875_mA 0x09 | |
| 247 | #define DRIVE_CURRENT_5_250_mA 0x0a | |
| 248 | #define DRIVE_CURRENT_5_625_mA 0x0b | |
| 249 | #define DRIVE_CURRENT_6_000_mA 0x0c | |
| 250 | #define DRIVE_CURRENT_6_375_mA 0x0d | |
| 251 | #define DRIVE_CURRENT_6_750_mA 0x0e | |
| 252 | #define DRIVE_CURRENT_7_125_mA 0x0f | |
| 253 | #define DRIVE_CURRENT_7_500_mA 0x10 | |
| 254 | #define DRIVE_CURRENT_7_875_mA 0x11 | |
| 255 | #define DRIVE_CURRENT_8_250_mA 0x12 | |
| 256 | #define DRIVE_CURRENT_8_625_mA 0x13 | |
| 257 | #define DRIVE_CURRENT_9_000_mA 0x14 | |
| 258 | #define DRIVE_CURRENT_9_375_mA 0x15 | |
| 259 | #define DRIVE_CURRENT_9_750_mA 0x16 | |
| 260 | #define DRIVE_CURRENT_10_125_mA 0x17 | |
| 261 | #define DRIVE_CURRENT_10_500_mA 0x18 | |
| 262 | #define DRIVE_CURRENT_10_875_mA 0x19 | |
| 263 | #define DRIVE_CURRENT_11_250_mA 0x1a | |
| 264 | #define DRIVE_CURRENT_11_625_mA 0x1b | |
| 265 | #define DRIVE_CURRENT_12_000_mA 0x1c | |
| 266 | #define DRIVE_CURRENT_12_375_mA 0x1d | |
| 267 | #define DRIVE_CURRENT_12_750_mA 0x1e | |
| 268 | #define DRIVE_CURRENT_13_125_mA 0x1f | |
| 269 | #define DRIVE_CURRENT_13_500_mA 0x20 | |
| 270 | #define DRIVE_CURRENT_13_875_mA 0x21 | |
| 271 | #define DRIVE_CURRENT_14_250_mA 0x22 | |
| 272 | #define DRIVE_CURRENT_14_625_mA 0x23 | |
| 273 | #define DRIVE_CURRENT_15_000_mA 0x24 | |
| 274 | #define DRIVE_CURRENT_15_375_mA 0x25 | |
| 275 | #define DRIVE_CURRENT_15_750_mA 0x26 | |
| 276 | #define DRIVE_CURRENT_16_125_mA 0x27 | |
| 277 | #define DRIVE_CURRENT_16_500_mA 0x28 | |
| 278 | #define DRIVE_CURRENT_16_875_mA 0x29 | |
| 279 | #define DRIVE_CURRENT_17_250_mA 0x2a | |
| 280 | #define DRIVE_CURRENT_17_625_mA 0x2b | |
| 281 | #define DRIVE_CURRENT_18_000_mA 0x2c | |
| 282 | #define DRIVE_CURRENT_18_375_mA 0x2d | |
| 283 | #define DRIVE_CURRENT_18_750_mA 0x2e | |
| 284 | #define DRIVE_CURRENT_19_125_mA 0x2f | |
| 285 | #define DRIVE_CURRENT_19_500_mA 0x30 | |
| 286 | #define DRIVE_CURRENT_19_875_mA 0x31 | |
| 287 | #define DRIVE_CURRENT_20_250_mA 0x32 | |
| 288 | #define DRIVE_CURRENT_20_625_mA 0x33 | |
| 289 | #define DRIVE_CURRENT_21_000_mA 0x34 | |
| 290 | #define DRIVE_CURRENT_21_375_mA 0x35 | |
| 291 | #define DRIVE_CURRENT_21_750_mA 0x36 | |
| 292 | #define DRIVE_CURRENT_22_125_mA 0x37 | |
| 293 | #define DRIVE_CURRENT_22_500_mA 0x38 | |
| 294 | #define DRIVE_CURRENT_22_875_mA 0x39 | |
| 295 | #define DRIVE_CURRENT_23_250_mA 0x3a | |
| 296 | #define DRIVE_CURRENT_23_625_mA 0x3b | |
| 297 | #define DRIVE_CURRENT_24_000_mA 0x3c | |
| 298 | #define DRIVE_CURRENT_24_375_mA 0x3d | |
| 299 | #define DRIVE_CURRENT_24_750_mA 0x3e | |
| 300 | ||
| 301 | #define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f | |
| 302 | #define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80 | |
| 303 | #define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81 | |
| 304 | ||
| 305 | #define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x)) | |
| 306 | #define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0) | |
| 307 | #define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16) | |
| 308 | ||
| 309 | #define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89 | |
| 310 | #define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a | |
| 311 | #define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b | |
| 312 | #define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0) | |
| 313 | #define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20) | |
| 314 | #define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20) | |
| 315 | #define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20) | |
| 316 | #define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24) | |
| 317 | ||
| 318 | #define HDMI_NV_PDISP_AUDIO_N 0x8c | |
| 319 | #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0) | |
| 320 | #define AUDIO_N_RESETF (1 << 20) | |
| 321 | #define AUDIO_N_GENERATE_NORMAL (0 << 24) | |
| 322 | #define AUDIO_N_GENERATE_ALTERNATE (1 << 24) | |
| 323 | ||
| 324 | #define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94 | |
| 325 | #define HDMI_NV_PDISP_SOR_REFCLK 0x95 | |
| 326 | #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8) | |
| 327 | #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6) | |
| 328 | ||
| 329 | #define HDMI_NV_PDISP_CRC_CONTROL 0x96 | |
| 330 | #define HDMI_NV_PDISP_INPUT_CONTROL 0x97 | |
| 331 | #define HDMI_SRC_DISPLAYA (0 << 0) | |
| 332 | #define HDMI_SRC_DISPLAYB (1 << 0) | |
| 333 | #define ARM_VIDEO_RANGE_FULL (0 << 1) | |
| 334 | #define ARM_VIDEO_RANGE_LIMITED (1 << 1) | |
| 335 | ||
| 336 | #define HDMI_NV_PDISP_SCRATCH 0x98 | |
| 337 | #define HDMI_NV_PDISP_PE_CURRENT 0x99 | |
| 338 | #define PE_CURRENT0(x) (((x) & 0xf) << 0) | |
| 339 | #define PE_CURRENT1(x) (((x) & 0xf) << 8) | |
| 340 | #define PE_CURRENT2(x) (((x) & 0xf) << 16) | |
| 341 | #define PE_CURRENT3(x) (((x) & 0xf) << 24) | |
| 342 | ||
| 343 | #define PE_CURRENT_0_0_mA 0x0 | |
| 344 | #define PE_CURRENT_0_5_mA 0x1 | |
| 345 | #define PE_CURRENT_1_0_mA 0x2 | |
| 346 | #define PE_CURRENT_1_5_mA 0x3 | |
| 347 | #define PE_CURRENT_2_0_mA 0x4 | |
| 348 | #define PE_CURRENT_2_5_mA 0x5 | |
| 349 | #define PE_CURRENT_3_0_mA 0x6 | |
| 350 | #define PE_CURRENT_3_5_mA 0x7 | |
| 351 | #define PE_CURRENT_4_0_mA 0x8 | |
| 352 | #define PE_CURRENT_4_5_mA 0x9 | |
| 353 | #define PE_CURRENT_5_0_mA 0xa | |
| 354 | #define PE_CURRENT_5_5_mA 0xb | |
| 355 | #define PE_CURRENT_6_0_mA 0xc | |
| 356 | #define PE_CURRENT_6_5_mA 0xd | |
| 357 | #define PE_CURRENT_7_0_mA 0xe | |
| 358 | #define PE_CURRENT_7_5_mA 0xf | |
| 359 | ||
| 360 | #define HDMI_NV_PDISP_KEY_CTRL 0x9a | |
| 361 | #define HDMI_NV_PDISP_KEY_DEBUG0 0x9b | |
| 362 | #define HDMI_NV_PDISP_KEY_DEBUG1 0x9c | |
| 363 | #define HDMI_NV_PDISP_KEY_DEBUG2 0x9d | |
| 364 | #define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e | |
| 365 | #define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f | |
| 366 | #define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0 | |
| 367 | #define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1 | |
| 368 | #define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2 | |
| 369 | #define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3 | |
| 370 | ||
| 371 | #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac | |
| 372 | #define AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29) | |
| 373 | #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc | |
| 374 | #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd | |
| 375 | ||
| 376 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf | |
| 377 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0 | |
| 378 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0xc1 | |
| 379 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0xc2 | |
| 380 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0xc3 | |
| 381 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0xc4 | |
| 382 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5 | |
| 383 | #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5 | |
| 384 | ||
| 385 | #endif /* TEGRA_HDMI_H */ |