Commit | Line | Data |
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16ea975e RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
a464d618 | 18 | #include "drm_flip_work.h" |
3cb9ae4f | 19 | #include <drm/drm_plane_helper.h> |
305198de | 20 | #include <drm/drm_atomic_helper.h> |
16ea975e RC |
21 | |
22 | #include "tilcdc_drv.h" | |
23 | #include "tilcdc_regs.h" | |
24 | ||
2b3a8cd7 TV |
25 | #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 |
26 | ||
16ea975e RC |
27 | struct tilcdc_crtc { |
28 | struct drm_crtc base; | |
29 | ||
47f571c6 | 30 | struct drm_plane primary; |
16ea975e | 31 | const struct tilcdc_panel_info *info; |
16ea975e | 32 | struct drm_pending_vblank_event *event; |
47bfd6c0 | 33 | bool enabled; |
16ea975e RC |
34 | wait_queue_head_t frame_done_wq; |
35 | bool frame_done; | |
2b3a8cd7 TV |
36 | spinlock_t irq_lock; |
37 | ||
38 | ktime_t last_vblank; | |
16ea975e | 39 | |
2b2080d7 | 40 | struct drm_framebuffer *curr_fb; |
2b3a8cd7 | 41 | struct drm_framebuffer *next_fb; |
16ea975e RC |
42 | |
43 | /* for deferred fb unref's: */ | |
a464d618 | 44 | struct drm_flip_work unref_work; |
103cd8bc JS |
45 | |
46 | /* Only set if an external encoder is connected */ | |
47 | bool simulate_vesa_sync; | |
5895d08f JS |
48 | |
49 | int sync_lost_count; | |
50 | bool frame_intact; | |
16ea975e RC |
51 | }; |
52 | #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) | |
53 | ||
a464d618 | 54 | static void unref_worker(struct drm_flip_work *work, void *val) |
16ea975e | 55 | { |
f7b45756 | 56 | struct tilcdc_crtc *tilcdc_crtc = |
a464d618 | 57 | container_of(work, struct tilcdc_crtc, unref_work); |
16ea975e | 58 | struct drm_device *dev = tilcdc_crtc->base.dev; |
16ea975e RC |
59 | |
60 | mutex_lock(&dev->mode_config.mutex); | |
a464d618 | 61 | drm_framebuffer_unreference(val); |
16ea975e RC |
62 | mutex_unlock(&dev->mode_config.mutex); |
63 | } | |
64 | ||
2b2080d7 | 65 | static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) |
16ea975e RC |
66 | { |
67 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
68 | struct drm_device *dev = crtc->dev; | |
16ea975e RC |
69 | struct drm_gem_cma_object *gem; |
70 | unsigned int depth, bpp; | |
2b2080d7 | 71 | dma_addr_t start, end; |
16ea975e RC |
72 | |
73 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); | |
74 | gem = drm_fb_cma_get_gem_obj(fb, 0); | |
75 | ||
2b2080d7 TV |
76 | start = gem->paddr + fb->offsets[0] + |
77 | crtc->y * fb->pitches[0] + | |
78 | crtc->x * bpp / 8; | |
16ea975e | 79 | |
2b2080d7 | 80 | end = start + (crtc->mode.vdisplay * fb->pitches[0]); |
16ea975e | 81 | |
2b2080d7 TV |
82 | tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start); |
83 | tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end); | |
84 | ||
85 | if (tilcdc_crtc->curr_fb) | |
86 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
87 | tilcdc_crtc->curr_fb); | |
88 | ||
89 | tilcdc_crtc->curr_fb = fb; | |
16ea975e RC |
90 | } |
91 | ||
afaf833d JS |
92 | static void tilcdc_crtc_enable_irqs(struct drm_device *dev) |
93 | { | |
94 | struct tilcdc_drm_private *priv = dev->dev_private; | |
95 | ||
96 | tilcdc_clear_irqstatus(dev, 0xffffffff); | |
97 | ||
98 | if (priv->rev == 1) { | |
99 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, | |
100 | LCDC_V1_UNDERFLOW_INT_ENA); | |
101 | } else { | |
102 | tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, | |
103 | LCDC_V2_UNDERFLOW_INT_ENA | | |
104 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
105 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
106 | } | |
107 | } | |
108 | ||
109 | static void tilcdc_crtc_disable_irqs(struct drm_device *dev) | |
110 | { | |
111 | struct tilcdc_drm_private *priv = dev->dev_private; | |
112 | ||
113 | /* disable irqs that we might have enabled: */ | |
114 | if (priv->rev == 1) { | |
115 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, | |
116 | LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); | |
117 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, | |
118 | LCDC_V1_END_OF_FRAME_INT_ENA); | |
119 | } else { | |
120 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, | |
121 | LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | | |
122 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
123 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
124 | } | |
125 | } | |
126 | ||
2efec4f3 | 127 | static void reset(struct drm_crtc *crtc) |
16ea975e RC |
128 | { |
129 | struct drm_device *dev = crtc->dev; | |
130 | struct tilcdc_drm_private *priv = dev->dev_private; | |
131 | ||
2efec4f3 TV |
132 | if (priv->rev != 2) |
133 | return; | |
134 | ||
135 | tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
136 | usleep_range(250, 1000); | |
137 | tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
138 | } | |
139 | ||
47bfd6c0 | 140 | static void tilcdc_crtc_enable(struct drm_crtc *crtc) |
2efec4f3 TV |
141 | { |
142 | struct drm_device *dev = crtc->dev; | |
47bfd6c0 JS |
143 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
144 | ||
145 | if (tilcdc_crtc->enabled) | |
146 | return; | |
147 | ||
148 | pm_runtime_get_sync(dev->dev); | |
2efec4f3 TV |
149 | |
150 | reset(crtc); | |
16ea975e | 151 | |
afaf833d JS |
152 | tilcdc_crtc_enable_irqs(dev); |
153 | ||
2b2080d7 | 154 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); |
16ea975e RC |
155 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); |
156 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); | |
d85f850e JS |
157 | |
158 | drm_crtc_vblank_on(crtc); | |
47bfd6c0 JS |
159 | |
160 | tilcdc_crtc->enabled = true; | |
16ea975e RC |
161 | } |
162 | ||
47bfd6c0 | 163 | void tilcdc_crtc_disable(struct drm_crtc *crtc) |
16ea975e | 164 | { |
2d5be882 | 165 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
16ea975e | 166 | struct drm_device *dev = crtc->dev; |
2d5be882 | 167 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e | 168 | |
47bfd6c0 JS |
169 | if (!tilcdc_crtc->enabled) |
170 | return; | |
171 | ||
2d5be882 | 172 | tilcdc_crtc->frame_done = false; |
16ea975e | 173 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); |
2d5be882 JS |
174 | |
175 | /* | |
176 | * if necessary wait for framedone irq which will still come | |
177 | * before putting things to sleep.. | |
178 | */ | |
179 | if (priv->rev == 2) { | |
180 | int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, | |
181 | tilcdc_crtc->frame_done, | |
437c7d94 | 182 | msecs_to_jiffies(500)); |
2d5be882 JS |
183 | if (ret == 0) |
184 | dev_err(dev->dev, "%s: timeout waiting for framedone\n", | |
185 | __func__); | |
186 | } | |
d85f850e JS |
187 | |
188 | drm_crtc_vblank_off(crtc); | |
afaf833d JS |
189 | |
190 | tilcdc_crtc_disable_irqs(dev); | |
47bfd6c0 JS |
191 | |
192 | pm_runtime_put_sync(dev->dev); | |
193 | ||
194 | if (tilcdc_crtc->next_fb) { | |
195 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
196 | tilcdc_crtc->next_fb); | |
197 | tilcdc_crtc->next_fb = NULL; | |
198 | } | |
199 | ||
200 | if (tilcdc_crtc->curr_fb) { | |
201 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
202 | tilcdc_crtc->curr_fb); | |
203 | tilcdc_crtc->curr_fb = NULL; | |
204 | } | |
205 | ||
206 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); | |
207 | tilcdc_crtc->last_vblank = ktime_set(0, 0); | |
208 | ||
209 | tilcdc_crtc->enabled = false; | |
210 | } | |
211 | ||
212 | static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) | |
213 | { | |
214 | return crtc->state && crtc->state->enable && crtc->state->active; | |
16ea975e RC |
215 | } |
216 | ||
217 | static void tilcdc_crtc_destroy(struct drm_crtc *crtc) | |
218 | { | |
219 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
220 | ||
47bfd6c0 | 221 | tilcdc_crtc_disable(crtc); |
16ea975e | 222 | |
d66284fb | 223 | of_node_put(crtc->port); |
16ea975e | 224 | drm_crtc_cleanup(crtc); |
a464d618 | 225 | drm_flip_work_cleanup(&tilcdc_crtc->unref_work); |
16ea975e RC |
226 | } |
227 | ||
e0e344e6 | 228 | int tilcdc_crtc_update_fb(struct drm_crtc *crtc, |
16ea975e | 229 | struct drm_framebuffer *fb, |
e0e344e6 | 230 | struct drm_pending_vblank_event *event) |
16ea975e RC |
231 | { |
232 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
233 | struct drm_device *dev = crtc->dev; | |
2b2080d7 | 234 | unsigned long flags; |
6f206e9d | 235 | |
16ea975e RC |
236 | if (tilcdc_crtc->event) { |
237 | dev_err(dev->dev, "already pending page flip!\n"); | |
238 | return -EBUSY; | |
239 | } | |
240 | ||
2b2080d7 TV |
241 | drm_framebuffer_reference(fb); |
242 | ||
f4510a27 | 243 | crtc->primary->fb = fb; |
65734a26 | 244 | |
2b3a8cd7 TV |
245 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
246 | ||
0a1fe1b7 JS |
247 | if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) { |
248 | ktime_t next_vblank; | |
249 | s64 tdiff; | |
2b2080d7 | 250 | |
0a1fe1b7 JS |
251 | next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, |
252 | 1000000 / crtc->hwmode.vrefresh); | |
2b3a8cd7 | 253 | |
0a1fe1b7 JS |
254 | tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); |
255 | ||
256 | if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) | |
257 | tilcdc_crtc->next_fb = fb; | |
258 | } | |
259 | ||
260 | if (tilcdc_crtc->next_fb != fb) | |
2b3a8cd7 | 261 | set_scanout(crtc, fb); |
2b2080d7 | 262 | |
2b2080d7 | 263 | tilcdc_crtc->event = event; |
2b3a8cd7 TV |
264 | |
265 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
16ea975e RC |
266 | |
267 | return 0; | |
268 | } | |
269 | ||
16ea975e RC |
270 | static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, |
271 | const struct drm_display_mode *mode, | |
272 | struct drm_display_mode *adjusted_mode) | |
273 | { | |
103cd8bc JS |
274 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
275 | ||
276 | if (!tilcdc_crtc->simulate_vesa_sync) | |
277 | return true; | |
278 | ||
279 | /* | |
280 | * tilcdc does not generate VESA-compliant sync but aligns | |
281 | * VS on the second edge of HS instead of first edge. | |
282 | * We use adjusted_mode, to fixup sync by aligning both rising | |
283 | * edges and add HSKEW offset to fix the sync. | |
284 | */ | |
285 | adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; | |
286 | adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; | |
287 | ||
288 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) { | |
289 | adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
290 | adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; | |
291 | } else { | |
292 | adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
293 | adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; | |
294 | } | |
295 | ||
16ea975e RC |
296 | return true; |
297 | } | |
298 | ||
f6382f18 JS |
299 | static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) |
300 | { | |
301 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
302 | struct drm_device *dev = crtc->dev; | |
303 | struct tilcdc_drm_private *priv = dev->dev_private; | |
304 | const struct tilcdc_panel_info *info = tilcdc_crtc->info; | |
305 | uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; | |
306 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; | |
307 | struct drm_framebuffer *fb = crtc->primary->state->fb; | |
308 | ||
309 | if (WARN_ON(!info)) | |
310 | return; | |
311 | ||
312 | if (WARN_ON(!fb)) | |
313 | return; | |
314 | ||
f6382f18 JS |
315 | /* Configure the Burst Size and fifo threshold of DMA: */ |
316 | reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; | |
317 | switch (info->dma_burst_sz) { | |
318 | case 1: | |
319 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); | |
320 | break; | |
321 | case 2: | |
322 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); | |
323 | break; | |
324 | case 4: | |
325 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); | |
326 | break; | |
327 | case 8: | |
328 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); | |
329 | break; | |
330 | case 16: | |
331 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); | |
332 | break; | |
333 | default: | |
334 | dev_err(dev->dev, "invalid burst size\n"); | |
335 | return; | |
336 | } | |
337 | reg |= (info->fifo_th << 8); | |
338 | tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); | |
339 | ||
340 | /* Configure timings: */ | |
341 | hbp = mode->htotal - mode->hsync_end; | |
342 | hfp = mode->hsync_start - mode->hdisplay; | |
343 | hsw = mode->hsync_end - mode->hsync_start; | |
344 | vbp = mode->vtotal - mode->vsync_end; | |
345 | vfp = mode->vsync_start - mode->vdisplay; | |
346 | vsw = mode->vsync_end - mode->vsync_start; | |
347 | ||
348 | DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", | |
349 | mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); | |
350 | ||
351 | /* Set AC Bias Period and Number of Transitions per Interrupt: */ | |
352 | reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; | |
353 | reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | | |
354 | LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); | |
355 | ||
356 | /* | |
357 | * subtract one from hfp, hbp, hsw because the hardware uses | |
358 | * a value of 0 as 1 | |
359 | */ | |
360 | if (priv->rev == 2) { | |
361 | /* clear bits we're going to set */ | |
362 | reg &= ~0x78000033; | |
363 | reg |= ((hfp-1) & 0x300) >> 8; | |
364 | reg |= ((hbp-1) & 0x300) >> 4; | |
365 | reg |= ((hsw-1) & 0x3c0) << 21; | |
366 | } | |
367 | tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); | |
368 | ||
369 | reg = (((mode->hdisplay >> 4) - 1) << 4) | | |
370 | (((hbp-1) & 0xff) << 24) | | |
371 | (((hfp-1) & 0xff) << 16) | | |
372 | (((hsw-1) & 0x3f) << 10); | |
373 | if (priv->rev == 2) | |
374 | reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; | |
375 | tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); | |
376 | ||
377 | reg = ((mode->vdisplay - 1) & 0x3ff) | | |
378 | ((vbp & 0xff) << 24) | | |
379 | ((vfp & 0xff) << 16) | | |
380 | (((vsw-1) & 0x3f) << 10); | |
381 | tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); | |
382 | ||
383 | /* | |
384 | * be sure to set Bit 10 for the V2 LCDC controller, | |
385 | * otherwise limited to 1024 pixels width, stopping | |
386 | * 1920x1080 being supported. | |
387 | */ | |
388 | if (priv->rev == 2) { | |
389 | if ((mode->vdisplay - 1) & 0x400) { | |
390 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, | |
391 | LCDC_LPP_B10); | |
392 | } else { | |
393 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, | |
394 | LCDC_LPP_B10); | |
395 | } | |
396 | } | |
397 | ||
398 | /* Configure display type: */ | |
399 | reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & | |
400 | ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | | |
401 | LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | | |
402 | 0x000ff000 /* Palette Loading Delay bits */); | |
403 | reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ | |
404 | if (info->tft_alt_mode) | |
405 | reg |= LCDC_TFT_ALT_ENABLE; | |
406 | if (priv->rev == 2) { | |
407 | unsigned int depth, bpp; | |
408 | ||
409 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); | |
410 | switch (bpp) { | |
411 | case 16: | |
412 | break; | |
413 | case 32: | |
414 | reg |= LCDC_V2_TFT_24BPP_UNPACK; | |
415 | /* fallthrough */ | |
416 | case 24: | |
417 | reg |= LCDC_V2_TFT_24BPP_MODE; | |
418 | break; | |
419 | default: | |
420 | dev_err(dev->dev, "invalid pixel format\n"); | |
421 | return; | |
422 | } | |
423 | } | |
424 | reg |= info->fdd < 12; | |
425 | tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); | |
426 | ||
427 | if (info->invert_pxl_clk) | |
428 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
429 | else | |
430 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
431 | ||
432 | if (info->sync_ctrl) | |
433 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
434 | else | |
435 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
436 | ||
437 | if (info->sync_edge) | |
438 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
439 | else | |
440 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
441 | ||
442 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
443 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
444 | else | |
445 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
446 | ||
447 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
448 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
449 | else | |
450 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
451 | ||
452 | if (info->raster_order) | |
453 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
454 | else | |
455 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
456 | ||
457 | drm_framebuffer_reference(fb); | |
458 | ||
459 | set_scanout(crtc, fb); | |
460 | ||
461 | tilcdc_crtc_update_clk(crtc); | |
462 | ||
f6382f18 JS |
463 | crtc->hwmode = crtc->state->adjusted_mode; |
464 | } | |
465 | ||
db380c58 JS |
466 | static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, |
467 | struct drm_crtc_state *state) | |
468 | { | |
469 | struct drm_display_mode *mode = &state->mode; | |
470 | int ret; | |
471 | ||
472 | /* If we are not active we don't care */ | |
473 | if (!state->active) | |
474 | return 0; | |
475 | ||
476 | if (state->state->planes[0].ptr != crtc->primary || | |
477 | state->state->planes[0].state == NULL || | |
478 | state->state->planes[0].state->crtc != crtc) { | |
479 | dev_dbg(crtc->dev->dev, "CRTC primary plane must be present"); | |
480 | return -EINVAL; | |
481 | } | |
482 | ||
483 | ret = tilcdc_crtc_mode_valid(crtc, mode); | |
484 | if (ret) { | |
485 | dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name); | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
16ea975e | 492 | static const struct drm_crtc_funcs tilcdc_crtc_funcs = { |
305198de JS |
493 | .destroy = tilcdc_crtc_destroy, |
494 | .set_config = drm_atomic_helper_set_config, | |
495 | .page_flip = drm_atomic_helper_page_flip, | |
496 | .reset = drm_atomic_helper_crtc_reset, | |
497 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
498 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
16ea975e RC |
499 | }; |
500 | ||
501 | static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { | |
16ea975e | 502 | .mode_fixup = tilcdc_crtc_mode_fixup, |
305198de JS |
503 | .enable = tilcdc_crtc_enable, |
504 | .disable = tilcdc_crtc_disable, | |
db380c58 | 505 | .atomic_check = tilcdc_crtc_atomic_check, |
f6382f18 | 506 | .mode_set_nofb = tilcdc_crtc_mode_set_nofb, |
16ea975e RC |
507 | }; |
508 | ||
509 | int tilcdc_crtc_max_width(struct drm_crtc *crtc) | |
510 | { | |
511 | struct drm_device *dev = crtc->dev; | |
512 | struct tilcdc_drm_private *priv = dev->dev_private; | |
513 | int max_width = 0; | |
514 | ||
515 | if (priv->rev == 1) | |
516 | max_width = 1024; | |
517 | else if (priv->rev == 2) | |
518 | max_width = 2048; | |
519 | ||
520 | return max_width; | |
521 | } | |
522 | ||
523 | int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) | |
524 | { | |
525 | struct tilcdc_drm_private *priv = crtc->dev->dev_private; | |
526 | unsigned int bandwidth; | |
e1c5d0a8 | 527 | uint32_t hbp, hfp, hsw, vbp, vfp, vsw; |
16ea975e | 528 | |
e1c5d0a8 DE |
529 | /* |
530 | * check to see if the width is within the range that | |
531 | * the LCD Controller physically supports | |
532 | */ | |
16ea975e RC |
533 | if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) |
534 | return MODE_VIRTUAL_X; | |
535 | ||
536 | /* width must be multiple of 16 */ | |
537 | if (mode->hdisplay & 0xf) | |
538 | return MODE_VIRTUAL_X; | |
539 | ||
540 | if (mode->vdisplay > 2048) | |
541 | return MODE_VIRTUAL_Y; | |
542 | ||
e1c5d0a8 DE |
543 | DBG("Processing mode %dx%d@%d with pixel clock %d", |
544 | mode->hdisplay, mode->vdisplay, | |
545 | drm_mode_vrefresh(mode), mode->clock); | |
546 | ||
547 | hbp = mode->htotal - mode->hsync_end; | |
548 | hfp = mode->hsync_start - mode->hdisplay; | |
549 | hsw = mode->hsync_end - mode->hsync_start; | |
550 | vbp = mode->vtotal - mode->vsync_end; | |
551 | vfp = mode->vsync_start - mode->vdisplay; | |
552 | vsw = mode->vsync_end - mode->vsync_start; | |
553 | ||
554 | if ((hbp-1) & ~0x3ff) { | |
555 | DBG("Pruning mode: Horizontal Back Porch out of range"); | |
556 | return MODE_HBLANK_WIDE; | |
557 | } | |
558 | ||
559 | if ((hfp-1) & ~0x3ff) { | |
560 | DBG("Pruning mode: Horizontal Front Porch out of range"); | |
561 | return MODE_HBLANK_WIDE; | |
562 | } | |
563 | ||
564 | if ((hsw-1) & ~0x3ff) { | |
565 | DBG("Pruning mode: Horizontal Sync Width out of range"); | |
566 | return MODE_HSYNC_WIDE; | |
567 | } | |
568 | ||
569 | if (vbp & ~0xff) { | |
570 | DBG("Pruning mode: Vertical Back Porch out of range"); | |
571 | return MODE_VBLANK_WIDE; | |
572 | } | |
573 | ||
574 | if (vfp & ~0xff) { | |
575 | DBG("Pruning mode: Vertical Front Porch out of range"); | |
576 | return MODE_VBLANK_WIDE; | |
577 | } | |
578 | ||
579 | if ((vsw-1) & ~0x3f) { | |
580 | DBG("Pruning mode: Vertical Sync Width out of range"); | |
581 | return MODE_VSYNC_WIDE; | |
582 | } | |
583 | ||
4e564346 DE |
584 | /* |
585 | * some devices have a maximum allowed pixel clock | |
586 | * configured from the DT | |
587 | */ | |
588 | if (mode->clock > priv->max_pixelclock) { | |
f7b45756 | 589 | DBG("Pruning mode: pixel clock too high"); |
4e564346 DE |
590 | return MODE_CLOCK_HIGH; |
591 | } | |
592 | ||
593 | /* | |
594 | * some devices further limit the max horizontal resolution | |
595 | * configured from the DT | |
596 | */ | |
597 | if (mode->hdisplay > priv->max_width) | |
598 | return MODE_BAD_WIDTH; | |
599 | ||
16ea975e | 600 | /* filter out modes that would require too much memory bandwidth: */ |
4e564346 DE |
601 | bandwidth = mode->hdisplay * mode->vdisplay * |
602 | drm_mode_vrefresh(mode); | |
603 | if (bandwidth > priv->max_bandwidth) { | |
f7b45756 | 604 | DBG("Pruning mode: exceeds defined bandwidth limit"); |
16ea975e | 605 | return MODE_BAD; |
4e564346 | 606 | } |
16ea975e RC |
607 | |
608 | return MODE_OK; | |
609 | } | |
610 | ||
611 | void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, | |
612 | const struct tilcdc_panel_info *info) | |
613 | { | |
614 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
615 | tilcdc_crtc->info = info; | |
616 | } | |
617 | ||
103cd8bc JS |
618 | void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, |
619 | bool simulate_vesa_sync) | |
620 | { | |
621 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
622 | ||
623 | tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; | |
624 | } | |
625 | ||
16ea975e RC |
626 | void tilcdc_crtc_update_clk(struct drm_crtc *crtc) |
627 | { | |
16ea975e RC |
628 | struct drm_device *dev = crtc->dev; |
629 | struct tilcdc_drm_private *priv = dev->dev_private; | |
3d19306a DE |
630 | unsigned long lcd_clk; |
631 | const unsigned clkdiv = 2; /* using a fixed divider of 2 */ | |
16ea975e RC |
632 | int ret; |
633 | ||
634 | pm_runtime_get_sync(dev->dev); | |
635 | ||
47bfd6c0 | 636 | tilcdc_crtc_disable(crtc); |
16ea975e | 637 | |
3d19306a DE |
638 | /* mode.clock is in KHz, set_rate wants parameter in Hz */ |
639 | ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); | |
640 | if (ret < 0) { | |
16ea975e RC |
641 | dev_err(dev->dev, "failed to set display clock rate to: %d\n", |
642 | crtc->mode.clock); | |
643 | goto out; | |
644 | } | |
645 | ||
646 | lcd_clk = clk_get_rate(priv->clk); | |
16ea975e | 647 | |
3d19306a DE |
648 | DBG("lcd_clk=%lu, mode clock=%d, div=%u", |
649 | lcd_clk, crtc->mode.clock, clkdiv); | |
16ea975e RC |
650 | |
651 | /* Configure the LCD clock divisor. */ | |
3d19306a | 652 | tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | |
16ea975e RC |
653 | LCDC_RASTER_MODE); |
654 | ||
655 | if (priv->rev == 2) | |
656 | tilcdc_set(dev, LCDC_CLK_ENABLE_REG, | |
657 | LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | | |
658 | LCDC_V2_CORE_CLK_EN); | |
659 | ||
47bfd6c0 JS |
660 | if (tilcdc_crtc_is_on(crtc)) |
661 | tilcdc_crtc_enable(crtc); | |
16ea975e RC |
662 | |
663 | out: | |
664 | pm_runtime_put_sync(dev->dev); | |
665 | } | |
666 | ||
5895d08f JS |
667 | #define SYNC_LOST_COUNT_LIMIT 50 |
668 | ||
16ea975e RC |
669 | irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) |
670 | { | |
671 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
672 | struct drm_device *dev = crtc->dev; | |
673 | struct tilcdc_drm_private *priv = dev->dev_private; | |
317aae73 | 674 | uint32_t stat; |
16ea975e | 675 | |
317aae73 TV |
676 | stat = tilcdc_read_irqstatus(dev); |
677 | tilcdc_clear_irqstatus(dev, stat); | |
678 | ||
2b2080d7 | 679 | if (stat & LCDC_END_OF_FRAME0) { |
16ea975e | 680 | unsigned long flags; |
2b3a8cd7 TV |
681 | bool skip_event = false; |
682 | ktime_t now; | |
683 | ||
684 | now = ktime_get(); | |
16ea975e | 685 | |
2b2080d7 | 686 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); |
16ea975e | 687 | |
2b3a8cd7 TV |
688 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
689 | ||
690 | tilcdc_crtc->last_vblank = now; | |
691 | ||
692 | if (tilcdc_crtc->next_fb) { | |
693 | set_scanout(crtc, tilcdc_crtc->next_fb); | |
694 | tilcdc_crtc->next_fb = NULL; | |
695 | skip_event = true; | |
696 | } | |
697 | ||
698 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
699 | ||
099ede83 | 700 | drm_crtc_handle_vblank(crtc); |
16ea975e | 701 | |
2b3a8cd7 TV |
702 | if (!skip_event) { |
703 | struct drm_pending_vblank_event *event; | |
16ea975e | 704 | |
2b3a8cd7 TV |
705 | spin_lock_irqsave(&dev->event_lock, flags); |
706 | ||
707 | event = tilcdc_crtc->event; | |
2b2080d7 | 708 | tilcdc_crtc->event = NULL; |
2b3a8cd7 | 709 | if (event) |
dfebc152 | 710 | drm_crtc_send_vblank_event(crtc, event); |
2b2080d7 | 711 | |
2b3a8cd7 TV |
712 | spin_unlock_irqrestore(&dev->event_lock, flags); |
713 | } | |
5895d08f JS |
714 | |
715 | if (tilcdc_crtc->frame_intact) | |
716 | tilcdc_crtc->sync_lost_count = 0; | |
717 | else | |
718 | tilcdc_crtc->frame_intact = true; | |
16ea975e RC |
719 | } |
720 | ||
14944113 JS |
721 | if (stat & LCDC_FIFO_UNDERFLOW) |
722 | dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow", | |
723 | __func__, stat); | |
724 | ||
725 | /* For revision 2 only */ | |
16ea975e RC |
726 | if (priv->rev == 2) { |
727 | if (stat & LCDC_FRAME_DONE) { | |
728 | tilcdc_crtc->frame_done = true; | |
729 | wake_up(&tilcdc_crtc->frame_done_wq); | |
730 | } | |
16ea975e | 731 | |
1abcdac8 JS |
732 | if (stat & LCDC_SYNC_LOST) { |
733 | dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", | |
734 | __func__, stat); | |
735 | tilcdc_crtc->frame_intact = false; | |
736 | if (tilcdc_crtc->sync_lost_count++ > | |
737 | SYNC_LOST_COUNT_LIMIT) { | |
738 | dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat); | |
739 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, | |
740 | LCDC_SYNC_LOST); | |
741 | } | |
5895d08f | 742 | } |
c0c2baaa | 743 | |
14944113 JS |
744 | /* Indicate to LCDC that the interrupt service routine has |
745 | * completed, see 13.3.6.1.6 in AM335x TRM. | |
746 | */ | |
747 | tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); | |
748 | } | |
c0c2baaa | 749 | |
16ea975e RC |
750 | return IRQ_HANDLED; |
751 | } | |
752 | ||
16ea975e RC |
753 | struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) |
754 | { | |
d66284fb | 755 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e RC |
756 | struct tilcdc_crtc *tilcdc_crtc; |
757 | struct drm_crtc *crtc; | |
758 | int ret; | |
759 | ||
d0ec32ca | 760 | tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); |
16ea975e RC |
761 | if (!tilcdc_crtc) { |
762 | dev_err(dev->dev, "allocation failed\n"); | |
763 | return NULL; | |
764 | } | |
765 | ||
766 | crtc = &tilcdc_crtc->base; | |
767 | ||
47f571c6 JS |
768 | ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); |
769 | if (ret < 0) | |
770 | goto fail; | |
771 | ||
16ea975e RC |
772 | init_waitqueue_head(&tilcdc_crtc->frame_done_wq); |
773 | ||
d7f8db53 | 774 | drm_flip_work_init(&tilcdc_crtc->unref_work, |
a464d618 | 775 | "unref", unref_worker); |
16ea975e | 776 | |
2b3a8cd7 TV |
777 | spin_lock_init(&tilcdc_crtc->irq_lock); |
778 | ||
47f571c6 JS |
779 | ret = drm_crtc_init_with_planes(dev, crtc, |
780 | &tilcdc_crtc->primary, | |
781 | NULL, | |
782 | &tilcdc_crtc_funcs, | |
783 | "tilcdc crtc"); | |
16ea975e RC |
784 | if (ret < 0) |
785 | goto fail; | |
786 | ||
787 | drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); | |
788 | ||
d66284fb JS |
789 | if (priv->is_componentized) { |
790 | struct device_node *ports = | |
791 | of_get_child_by_name(dev->dev->of_node, "ports"); | |
792 | ||
793 | if (ports) { | |
794 | crtc->port = of_get_child_by_name(ports, "port"); | |
795 | of_node_put(ports); | |
796 | } else { | |
797 | crtc->port = | |
798 | of_get_child_by_name(dev->dev->of_node, "port"); | |
799 | } | |
800 | if (!crtc->port) { /* This should never happen */ | |
801 | dev_err(dev->dev, "Port node not found in %s\n", | |
802 | dev->dev->of_node->full_name); | |
803 | goto fail; | |
804 | } | |
805 | } | |
806 | ||
16ea975e RC |
807 | return crtc; |
808 | ||
809 | fail: | |
810 | tilcdc_crtc_destroy(crtc); | |
811 | return NULL; | |
812 | } |