Commit | Line | Data |
---|---|---|
16ea975e RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __TILCDC_DRV_H__ | |
19 | #define __TILCDC_DRV_H__ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/cpufreq.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/pm.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/of.h> | |
29 | #include <linux/of_device.h> | |
30 | #include <linux/list.h> | |
31 | ||
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_gem_cma_helper.h> | |
35 | #include <drm/drm_fb_cma_helper.h> | |
36 | ||
4e564346 DE |
37 | /* Defaulting to pixel clock defined on AM335x */ |
38 | #define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000 | |
39 | /* Defaulting to max width as defined on AM335x */ | |
40 | #define TILCDC_DEFAULT_MAX_WIDTH 2048 | |
41 | /* | |
42 | * This may need some tweaking, but want to allow at least 1280x1024@60 | |
43 | * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to | |
44 | * be supportable | |
45 | */ | |
46 | #define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60) | |
47 | ||
48 | ||
16ea975e RC |
49 | struct tilcdc_drm_private { |
50 | void __iomem *mmio; | |
51 | ||
16ea975e RC |
52 | struct clk *clk; /* functional clock */ |
53 | int rev; /* IP revision */ | |
54 | ||
55 | /* don't attempt resolutions w/ higher W * H * Hz: */ | |
56 | uint32_t max_bandwidth; | |
4e564346 DE |
57 | /* |
58 | * Pixel Clock will be restricted to some value as | |
59 | * defined in the device datasheet measured in KHz | |
60 | */ | |
61 | uint32_t max_pixelclock; | |
62 | /* | |
63 | * Max allowable width is limited on a per device basis | |
64 | * measured in pixels | |
65 | */ | |
66 | uint32_t max_width; | |
16ea975e | 67 | |
bcc5a6f5 JS |
68 | /* Supported pixel formats */ |
69 | const uint32_t *pixelformats; | |
70 | uint32_t num_pixelformats; | |
71 | ||
514d1a1f JS |
72 | /* The context for pm susped/resume cycle is stored here */ |
73 | struct drm_atomic_state *saved_state; | |
16ea975e RC |
74 | |
75 | #ifdef CONFIG_CPU_FREQ | |
76 | struct notifier_block freq_transition; | |
77 | unsigned int lcd_fck_rate; | |
78 | #endif | |
79 | ||
80 | struct workqueue_struct *wq; | |
81 | ||
82 | struct drm_fbdev_cma *fbdev; | |
83 | ||
84 | struct drm_crtc *crtc; | |
85 | ||
86 | unsigned int num_encoders; | |
87 | struct drm_encoder *encoders[8]; | |
88 | ||
89 | unsigned int num_connectors; | |
90 | struct drm_connector *connectors[8]; | |
103cd8bc JS |
91 | const struct drm_connector_helper_funcs *connector_funcs[8]; |
92 | ||
93 | bool is_componentized; | |
16ea975e RC |
94 | }; |
95 | ||
96 | /* Sub-module for display. Since we don't know at compile time what panels | |
97 | * or display adapter(s) might be present (for ex, off chip dvi/tfp410, | |
98 | * hdmi encoder, various lcd panels), the connector/encoder(s) are split into | |
99 | * separate drivers. If they are probed and found to be present, they | |
100 | * register themselves with tilcdc_register_module(). | |
101 | */ | |
102 | struct tilcdc_module; | |
103 | ||
104 | struct tilcdc_module_ops { | |
105 | /* create appropriate encoders/connectors: */ | |
106 | int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev); | |
16ea975e RC |
107 | #ifdef CONFIG_DEBUG_FS |
108 | /* create debugfs nodes (can be NULL): */ | |
109 | int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor); | |
110 | /* cleanup debugfs nodes (can be NULL): */ | |
111 | void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor); | |
112 | #endif | |
113 | }; | |
114 | ||
115 | struct tilcdc_module { | |
116 | const char *name; | |
117 | struct list_head list; | |
118 | const struct tilcdc_module_ops *funcs; | |
119 | }; | |
120 | ||
121 | void tilcdc_module_init(struct tilcdc_module *mod, const char *name, | |
122 | const struct tilcdc_module_ops *funcs); | |
123 | void tilcdc_module_cleanup(struct tilcdc_module *mod); | |
16ea975e RC |
124 | |
125 | /* Panel config that needs to be set in the crtc, but is not coming from | |
126 | * the mode timings. The display module is expected to call | |
127 | * tilcdc_crtc_set_panel_info() to set this during modeset. | |
128 | */ | |
129 | struct tilcdc_panel_info { | |
130 | ||
131 | /* AC Bias Pin Frequency */ | |
132 | uint32_t ac_bias; | |
133 | ||
134 | /* AC Bias Pin Transitions per Interrupt */ | |
135 | uint32_t ac_bias_intrpt; | |
136 | ||
137 | /* DMA burst size */ | |
138 | uint32_t dma_burst_sz; | |
139 | ||
140 | /* Bits per pixel */ | |
141 | uint32_t bpp; | |
142 | ||
143 | /* FIFO DMA Request Delay */ | |
144 | uint32_t fdd; | |
145 | ||
146 | /* TFT Alternative Signal Mapping (Only for active) */ | |
147 | bool tft_alt_mode; | |
148 | ||
149 | /* Invert pixel clock */ | |
150 | bool invert_pxl_clk; | |
151 | ||
152 | /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ | |
153 | uint32_t sync_edge; | |
154 | ||
155 | /* Horizontal and Vertical Sync: Control: 0=ignore */ | |
156 | uint32_t sync_ctrl; | |
157 | ||
158 | /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ | |
159 | uint32_t raster_order; | |
160 | ||
161 | /* DMA FIFO threshold */ | |
162 | uint32_t fifo_th; | |
163 | }; | |
164 | ||
165 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) | |
166 | ||
167 | struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev); | |
16ea975e RC |
168 | irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); |
169 | void tilcdc_crtc_update_clk(struct drm_crtc *crtc); | |
170 | void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, | |
171 | const struct tilcdc_panel_info *info); | |
103cd8bc JS |
172 | void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, |
173 | bool simulate_vesa_sync); | |
16ea975e RC |
174 | int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode); |
175 | int tilcdc_crtc_max_width(struct drm_crtc *crtc); | |
47bfd6c0 | 176 | void tilcdc_crtc_disable(struct drm_crtc *crtc); |
e0e344e6 | 177 | int tilcdc_crtc_update_fb(struct drm_crtc *crtc, |
8c65abb9 | 178 | struct drm_framebuffer *fb, |
e0e344e6 | 179 | struct drm_pending_vblank_event *event); |
16ea975e | 180 | |
b961c48b JS |
181 | int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane); |
182 | ||
16ea975e | 183 | #endif /* __TILCDC_DRV_H__ */ |