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c8b75bca EA |
1 | /* |
2 | * Copyright (C) 2015 Broadcom | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /** | |
10 | * DOC: VC4 CRTC module | |
11 | * | |
12 | * In VC4, the Pixel Valve is what most closely corresponds to the | |
13 | * DRM's concept of a CRTC. The PV generates video timings from the | |
14 | * output's clock plus its configuration. It pulls scaled pixels from | |
15 | * the HVS at that timing, and feeds it to the encoder. | |
16 | * | |
17 | * However, the DRM CRTC also collects the configuration of all the | |
18 | * DRM planes attached to it. As a result, this file also manages | |
19 | * setup of the VC4 HVS's display elements on the CRTC. | |
20 | * | |
21 | * The 2835 has 3 different pixel valves. pv0 in the audio power | |
22 | * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the | |
23 | * image domain can feed either HDMI or the SDTV controller. The | |
24 | * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for | |
25 | * SDTV, etc.) according to which output type is chosen in the mux. | |
26 | * | |
27 | * For power management, the pixel valve's registers are all clocked | |
28 | * by the AXI clock, while the timings and FIFOs make use of the | |
29 | * output-specific clock. Since the encoders also directly consume | |
30 | * the CPRMAN clocks, and know what timings they need, they are the | |
31 | * ones that set the clock. | |
32 | */ | |
33 | ||
34 | #include "drm_atomic.h" | |
35 | #include "drm_atomic_helper.h" | |
36 | #include "drm_crtc_helper.h" | |
37 | #include "linux/clk.h" | |
b501bacc | 38 | #include "drm_fb_cma_helper.h" |
c8b75bca EA |
39 | #include "linux/component.h" |
40 | #include "linux/of_device.h" | |
41 | #include "vc4_drv.h" | |
42 | #include "vc4_regs.h" | |
43 | ||
44 | struct vc4_crtc { | |
45 | struct drm_crtc base; | |
46 | const struct vc4_crtc_data *data; | |
47 | void __iomem *regs; | |
48 | ||
49 | /* Which HVS channel we're using for our CRTC. */ | |
50 | int channel; | |
51 | ||
e582b6c7 EA |
52 | u8 lut_r[256]; |
53 | u8 lut_g[256]; | |
54 | u8 lut_b[256]; | |
55 | ||
c8b75bca EA |
56 | struct drm_pending_vblank_event *event; |
57 | }; | |
58 | ||
d8dbf44f EA |
59 | struct vc4_crtc_state { |
60 | struct drm_crtc_state base; | |
61 | /* Dlist area for this CRTC configuration. */ | |
62 | struct drm_mm_node mm; | |
63 | }; | |
64 | ||
c8b75bca EA |
65 | static inline struct vc4_crtc * |
66 | to_vc4_crtc(struct drm_crtc *crtc) | |
67 | { | |
68 | return (struct vc4_crtc *)crtc; | |
69 | } | |
70 | ||
d8dbf44f EA |
71 | static inline struct vc4_crtc_state * |
72 | to_vc4_crtc_state(struct drm_crtc_state *crtc_state) | |
73 | { | |
74 | return (struct vc4_crtc_state *)crtc_state; | |
75 | } | |
76 | ||
c8b75bca EA |
77 | struct vc4_crtc_data { |
78 | /* Which channel of the HVS this pixelvalve sources from. */ | |
79 | int hvs_channel; | |
80 | ||
81 | enum vc4_encoder_type encoder0_type; | |
82 | enum vc4_encoder_type encoder1_type; | |
83 | }; | |
84 | ||
85 | #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) | |
86 | #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) | |
87 | ||
88 | #define CRTC_REG(reg) { reg, #reg } | |
89 | static const struct { | |
90 | u32 reg; | |
91 | const char *name; | |
92 | } crtc_regs[] = { | |
93 | CRTC_REG(PV_CONTROL), | |
94 | CRTC_REG(PV_V_CONTROL), | |
c31806fb | 95 | CRTC_REG(PV_VSYNCD_EVEN), |
c8b75bca EA |
96 | CRTC_REG(PV_HORZA), |
97 | CRTC_REG(PV_HORZB), | |
98 | CRTC_REG(PV_VERTA), | |
99 | CRTC_REG(PV_VERTB), | |
100 | CRTC_REG(PV_VERTA_EVEN), | |
101 | CRTC_REG(PV_VERTB_EVEN), | |
102 | CRTC_REG(PV_INTEN), | |
103 | CRTC_REG(PV_INTSTAT), | |
104 | CRTC_REG(PV_STAT), | |
105 | CRTC_REG(PV_HACT_ACT), | |
106 | }; | |
107 | ||
108 | static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc) | |
109 | { | |
110 | int i; | |
111 | ||
112 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
113 | DRM_INFO("0x%04x (%s): 0x%08x\n", | |
114 | crtc_regs[i].reg, crtc_regs[i].name, | |
115 | CRTC_READ(crtc_regs[i].reg)); | |
116 | } | |
117 | } | |
118 | ||
119 | #ifdef CONFIG_DEBUG_FS | |
120 | int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) | |
121 | { | |
122 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
123 | struct drm_device *dev = node->minor->dev; | |
124 | int crtc_index = (uintptr_t)node->info_ent->data; | |
125 | struct drm_crtc *crtc; | |
126 | struct vc4_crtc *vc4_crtc; | |
127 | int i; | |
128 | ||
129 | i = 0; | |
130 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
131 | if (i == crtc_index) | |
132 | break; | |
133 | i++; | |
134 | } | |
135 | if (!crtc) | |
136 | return 0; | |
137 | vc4_crtc = to_vc4_crtc(crtc); | |
138 | ||
139 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
140 | seq_printf(m, "%s (0x%04x): 0x%08x\n", | |
141 | crtc_regs[i].name, crtc_regs[i].reg, | |
142 | CRTC_READ(crtc_regs[i].reg)); | |
143 | } | |
144 | ||
145 | return 0; | |
146 | } | |
147 | #endif | |
148 | ||
149 | static void vc4_crtc_destroy(struct drm_crtc *crtc) | |
150 | { | |
151 | drm_crtc_cleanup(crtc); | |
152 | } | |
153 | ||
e582b6c7 EA |
154 | static void |
155 | vc4_crtc_lut_load(struct drm_crtc *crtc) | |
156 | { | |
157 | struct drm_device *dev = crtc->dev; | |
158 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
159 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
160 | u32 i; | |
161 | ||
162 | /* The LUT memory is laid out with each HVS channel in order, | |
163 | * each of which takes 256 writes for R, 256 for G, then 256 | |
164 | * for B. | |
165 | */ | |
166 | HVS_WRITE(SCALER_GAMADDR, | |
167 | SCALER_GAMADDR_AUTOINC | | |
168 | (vc4_crtc->channel * 3 * crtc->gamma_size)); | |
169 | ||
170 | for (i = 0; i < crtc->gamma_size; i++) | |
171 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); | |
172 | for (i = 0; i < crtc->gamma_size; i++) | |
173 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); | |
174 | for (i = 0; i < crtc->gamma_size; i++) | |
175 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); | |
176 | } | |
177 | ||
178 | static void | |
179 | vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
180 | uint32_t start, uint32_t size) | |
181 | { | |
182 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
183 | u32 i; | |
184 | ||
185 | for (i = start; i < start + size; i++) { | |
186 | vc4_crtc->lut_r[i] = r[i] >> 8; | |
187 | vc4_crtc->lut_g[i] = g[i] >> 8; | |
188 | vc4_crtc->lut_b[i] = b[i] >> 8; | |
189 | } | |
190 | ||
191 | vc4_crtc_lut_load(crtc); | |
192 | } | |
193 | ||
c8b75bca EA |
194 | static u32 vc4_get_fifo_full_level(u32 format) |
195 | { | |
196 | static const u32 fifo_len_bytes = 64; | |
197 | static const u32 hvs_latency_pix = 6; | |
198 | ||
199 | switch (format) { | |
200 | case PV_CONTROL_FORMAT_DSIV_16: | |
201 | case PV_CONTROL_FORMAT_DSIC_16: | |
202 | return fifo_len_bytes - 2 * hvs_latency_pix; | |
203 | case PV_CONTROL_FORMAT_DSIV_18: | |
204 | return fifo_len_bytes - 14; | |
205 | case PV_CONTROL_FORMAT_24: | |
206 | case PV_CONTROL_FORMAT_DSIV_24: | |
207 | default: | |
208 | return fifo_len_bytes - 3 * hvs_latency_pix; | |
209 | } | |
210 | } | |
211 | ||
212 | /* | |
213 | * Returns the clock select bit for the connector attached to the | |
214 | * CRTC. | |
215 | */ | |
216 | static int vc4_get_clock_select(struct drm_crtc *crtc) | |
217 | { | |
218 | struct drm_connector *connector; | |
219 | ||
220 | drm_for_each_connector(connector, crtc->dev) { | |
2fa8e904 | 221 | if (connector->state->crtc == crtc) { |
c8b75bca EA |
222 | struct drm_encoder *encoder = connector->encoder; |
223 | struct vc4_encoder *vc4_encoder = | |
224 | to_vc4_encoder(encoder); | |
225 | ||
226 | return vc4_encoder->clock_select; | |
227 | } | |
228 | } | |
229 | ||
230 | return -1; | |
231 | } | |
232 | ||
233 | static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
234 | { | |
6a609209 EA |
235 | struct drm_device *dev = crtc->dev; |
236 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
c8b75bca EA |
237 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
238 | struct drm_crtc_state *state = crtc->state; | |
239 | struct drm_display_mode *mode = &state->adjusted_mode; | |
240 | bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
241 | u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0)); | |
242 | u32 format = PV_CONTROL_FORMAT_24; | |
243 | bool debug_dump_regs = false; | |
244 | int clock_select = vc4_get_clock_select(crtc); | |
245 | ||
246 | if (debug_dump_regs) { | |
247 | DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); | |
248 | vc4_crtc_dump_regs(vc4_crtc); | |
249 | } | |
250 | ||
251 | /* Reset the PV fifo. */ | |
252 | CRTC_WRITE(PV_CONTROL, 0); | |
253 | CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); | |
254 | CRTC_WRITE(PV_CONTROL, 0); | |
255 | ||
256 | CRTC_WRITE(PV_HORZA, | |
257 | VC4_SET_FIELD(mode->htotal - mode->hsync_end, | |
258 | PV_HORZA_HBP) | | |
259 | VC4_SET_FIELD(mode->hsync_end - mode->hsync_start, | |
260 | PV_HORZA_HSYNC)); | |
261 | CRTC_WRITE(PV_HORZB, | |
262 | VC4_SET_FIELD(mode->hsync_start - mode->hdisplay, | |
263 | PV_HORZB_HFP) | | |
264 | VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE)); | |
265 | ||
a7c5047d EA |
266 | CRTC_WRITE(PV_VERTA, |
267 | VC4_SET_FIELD(mode->vtotal - mode->vsync_end, | |
268 | PV_VERTA_VBP) | | |
269 | VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, | |
270 | PV_VERTA_VSYNC)); | |
271 | CRTC_WRITE(PV_VERTB, | |
272 | VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, | |
273 | PV_VERTB_VFP) | | |
274 | VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE)); | |
275 | ||
c8b75bca EA |
276 | if (interlace) { |
277 | CRTC_WRITE(PV_VERTA_EVEN, | |
278 | VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1, | |
279 | PV_VERTA_VBP) | | |
280 | VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, | |
281 | PV_VERTA_VSYNC)); | |
282 | CRTC_WRITE(PV_VERTB_EVEN, | |
283 | VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, | |
284 | PV_VERTB_VFP) | | |
285 | VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE)); | |
286 | } | |
287 | ||
288 | CRTC_WRITE(PV_HACT_ACT, mode->hdisplay); | |
289 | ||
290 | CRTC_WRITE(PV_V_CONTROL, | |
291 | PV_VCONTROL_CONTINUOUS | | |
292 | (interlace ? PV_VCONTROL_INTERLACE : 0)); | |
293 | ||
294 | CRTC_WRITE(PV_CONTROL, | |
295 | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | | |
296 | VC4_SET_FIELD(vc4_get_fifo_full_level(format), | |
297 | PV_CONTROL_FIFO_LEVEL) | | |
298 | PV_CONTROL_CLR_AT_START | | |
299 | PV_CONTROL_TRIGGER_UNDERFLOW | | |
300 | PV_CONTROL_WAIT_HSTART | | |
301 | VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) | | |
302 | PV_CONTROL_FIFO_CLR | | |
303 | PV_CONTROL_EN); | |
304 | ||
6a609209 EA |
305 | HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), |
306 | SCALER_DISPBKGND_AUTOHS | | |
e582b6c7 | 307 | SCALER_DISPBKGND_GAMMA | |
6a609209 EA |
308 | (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); |
309 | ||
e582b6c7 EA |
310 | /* Reload the LUT, since the SRAMs would have been disabled if |
311 | * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. | |
312 | */ | |
313 | vc4_crtc_lut_load(crtc); | |
314 | ||
c8b75bca EA |
315 | if (debug_dump_regs) { |
316 | DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc)); | |
317 | vc4_crtc_dump_regs(vc4_crtc); | |
318 | } | |
319 | } | |
320 | ||
321 | static void require_hvs_enabled(struct drm_device *dev) | |
322 | { | |
323 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
324 | ||
325 | WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != | |
326 | SCALER_DISPCTRL_ENABLE); | |
327 | } | |
328 | ||
329 | static void vc4_crtc_disable(struct drm_crtc *crtc) | |
330 | { | |
331 | struct drm_device *dev = crtc->dev; | |
332 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
333 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
334 | u32 chan = vc4_crtc->channel; | |
335 | int ret; | |
336 | require_hvs_enabled(dev); | |
337 | ||
338 | CRTC_WRITE(PV_V_CONTROL, | |
339 | CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); | |
340 | ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); | |
341 | WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); | |
342 | ||
343 | if (HVS_READ(SCALER_DISPCTRLX(chan)) & | |
344 | SCALER_DISPCTRLX_ENABLE) { | |
345 | HVS_WRITE(SCALER_DISPCTRLX(chan), | |
346 | SCALER_DISPCTRLX_RESET); | |
347 | ||
348 | /* While the docs say that reset is self-clearing, it | |
349 | * seems it doesn't actually. | |
350 | */ | |
351 | HVS_WRITE(SCALER_DISPCTRLX(chan), 0); | |
352 | } | |
353 | ||
354 | /* Once we leave, the scaler should be disabled and its fifo empty. */ | |
355 | ||
356 | WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); | |
357 | ||
358 | WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), | |
359 | SCALER_DISPSTATX_MODE) != | |
360 | SCALER_DISPSTATX_MODE_DISABLED); | |
361 | ||
362 | WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & | |
363 | (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != | |
364 | SCALER_DISPSTATX_EMPTY); | |
365 | } | |
366 | ||
367 | static void vc4_crtc_enable(struct drm_crtc *crtc) | |
368 | { | |
369 | struct drm_device *dev = crtc->dev; | |
370 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
371 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
372 | struct drm_crtc_state *state = crtc->state; | |
373 | struct drm_display_mode *mode = &state->adjusted_mode; | |
374 | ||
375 | require_hvs_enabled(dev); | |
376 | ||
377 | /* Turn on the scaler, which will wait for vstart to start | |
378 | * compositing. | |
379 | */ | |
380 | HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), | |
381 | VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) | | |
382 | VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) | | |
383 | SCALER_DISPCTRLX_ENABLE); | |
384 | ||
385 | /* Turn on the pixel valve, which will emit the vstart signal. */ | |
386 | CRTC_WRITE(PV_V_CONTROL, | |
387 | CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); | |
388 | } | |
389 | ||
390 | static int vc4_crtc_atomic_check(struct drm_crtc *crtc, | |
391 | struct drm_crtc_state *state) | |
392 | { | |
d8dbf44f | 393 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); |
c8b75bca EA |
394 | struct drm_device *dev = crtc->dev; |
395 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
396 | struct drm_plane *plane; | |
d8dbf44f | 397 | unsigned long flags; |
c8b75bca | 398 | u32 dlist_count = 0; |
d8dbf44f | 399 | int ret; |
c8b75bca EA |
400 | |
401 | /* The pixelvalve can only feed one encoder (and encoders are | |
402 | * 1:1 with connectors.) | |
403 | */ | |
14de6c44 | 404 | if (hweight32(state->connector_mask) > 1) |
c8b75bca EA |
405 | return -EINVAL; |
406 | ||
407 | drm_atomic_crtc_state_for_each_plane(plane, state) { | |
408 | struct drm_plane_state *plane_state = | |
409 | state->state->plane_states[drm_plane_index(plane)]; | |
410 | ||
411 | /* plane might not have changed, in which case take | |
412 | * current state: | |
413 | */ | |
414 | if (!plane_state) | |
415 | plane_state = plane->state; | |
416 | ||
417 | dlist_count += vc4_plane_dlist_size(plane_state); | |
418 | } | |
419 | ||
420 | dlist_count++; /* Account for SCALER_CTL0_END. */ | |
421 | ||
d8dbf44f EA |
422 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); |
423 | ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, | |
424 | dlist_count, 1, 0); | |
425 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); | |
426 | if (ret) | |
427 | return ret; | |
c8b75bca EA |
428 | |
429 | return 0; | |
430 | } | |
431 | ||
432 | static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, | |
433 | struct drm_crtc_state *old_state) | |
434 | { | |
435 | struct drm_device *dev = crtc->dev; | |
436 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
437 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
d8dbf44f | 438 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); |
c8b75bca EA |
439 | struct drm_plane *plane; |
440 | bool debug_dump_regs = false; | |
d8dbf44f EA |
441 | u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; |
442 | u32 __iomem *dlist_next = dlist_start; | |
c8b75bca EA |
443 | |
444 | if (debug_dump_regs) { | |
445 | DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); | |
446 | vc4_hvs_dump_state(dev); | |
447 | } | |
448 | ||
d8dbf44f | 449 | /* Copy all the active planes' dlist contents to the hardware dlist. */ |
c8b75bca EA |
450 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
451 | dlist_next += vc4_plane_write_dlist(plane, dlist_next); | |
452 | } | |
453 | ||
d8dbf44f EA |
454 | writel(SCALER_CTL0_END, dlist_next); |
455 | dlist_next++; | |
456 | ||
457 | WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); | |
458 | ||
c8b75bca EA |
459 | if (crtc->state->event) { |
460 | unsigned long flags; | |
461 | ||
462 | crtc->state->event->pipe = drm_crtc_index(crtc); | |
463 | ||
464 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
465 | ||
466 | spin_lock_irqsave(&dev->event_lock, flags); | |
467 | vc4_crtc->event = crtc->state->event; | |
c8b75bca | 468 | crtc->state->event = NULL; |
56d1fe09 MK |
469 | |
470 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
471 | vc4_state->mm.start); | |
472 | ||
473 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
474 | } else { | |
475 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
476 | vc4_state->mm.start); | |
477 | } | |
478 | ||
479 | if (debug_dump_regs) { | |
480 | DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); | |
481 | vc4_hvs_dump_state(dev); | |
c8b75bca EA |
482 | } |
483 | } | |
484 | ||
1f43710a | 485 | int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id) |
c8b75bca EA |
486 | { |
487 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
488 | struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; | |
489 | ||
490 | CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
1f43710a | 495 | void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id) |
c8b75bca EA |
496 | { |
497 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
498 | struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; | |
499 | ||
500 | CRTC_WRITE(PV_INTEN, 0); | |
501 | } | |
502 | ||
503 | static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) | |
504 | { | |
505 | struct drm_crtc *crtc = &vc4_crtc->base; | |
506 | struct drm_device *dev = crtc->dev; | |
56d1fe09 MK |
507 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
508 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); | |
509 | u32 chan = vc4_crtc->channel; | |
c8b75bca EA |
510 | unsigned long flags; |
511 | ||
512 | spin_lock_irqsave(&dev->event_lock, flags); | |
56d1fe09 MK |
513 | if (vc4_crtc->event && |
514 | (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) { | |
c8b75bca EA |
515 | drm_crtc_send_vblank_event(crtc, vc4_crtc->event); |
516 | vc4_crtc->event = NULL; | |
ee7c10e1 | 517 | drm_crtc_vblank_put(crtc); |
c8b75bca EA |
518 | } |
519 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
520 | } | |
521 | ||
522 | static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) | |
523 | { | |
524 | struct vc4_crtc *vc4_crtc = data; | |
525 | u32 stat = CRTC_READ(PV_INTSTAT); | |
526 | irqreturn_t ret = IRQ_NONE; | |
527 | ||
528 | if (stat & PV_INT_VFP_START) { | |
529 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); | |
530 | drm_crtc_handle_vblank(&vc4_crtc->base); | |
531 | vc4_crtc_handle_page_flip(vc4_crtc); | |
532 | ret = IRQ_HANDLED; | |
533 | } | |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
b501bacc EA |
538 | struct vc4_async_flip_state { |
539 | struct drm_crtc *crtc; | |
540 | struct drm_framebuffer *fb; | |
541 | struct drm_pending_vblank_event *event; | |
542 | ||
543 | struct vc4_seqno_cb cb; | |
544 | }; | |
545 | ||
546 | /* Called when the V3D execution for the BO being flipped to is done, so that | |
547 | * we can actually update the plane's address to point to it. | |
548 | */ | |
549 | static void | |
550 | vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) | |
551 | { | |
552 | struct vc4_async_flip_state *flip_state = | |
553 | container_of(cb, struct vc4_async_flip_state, cb); | |
554 | struct drm_crtc *crtc = flip_state->crtc; | |
555 | struct drm_device *dev = crtc->dev; | |
556 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
557 | struct drm_plane *plane = crtc->primary; | |
558 | ||
559 | vc4_plane_async_set_fb(plane, flip_state->fb); | |
560 | if (flip_state->event) { | |
561 | unsigned long flags; | |
562 | ||
563 | spin_lock_irqsave(&dev->event_lock, flags); | |
564 | drm_crtc_send_vblank_event(crtc, flip_state->event); | |
565 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
566 | } | |
567 | ||
ee7c10e1 | 568 | drm_crtc_vblank_put(crtc); |
b501bacc EA |
569 | drm_framebuffer_unreference(flip_state->fb); |
570 | kfree(flip_state); | |
571 | ||
572 | up(&vc4->async_modeset); | |
573 | } | |
574 | ||
575 | /* Implements async (non-vblank-synced) page flips. | |
576 | * | |
577 | * The page flip ioctl needs to return immediately, so we grab the | |
578 | * modeset semaphore on the pipe, and queue the address update for | |
579 | * when V3D is done with the BO being flipped to. | |
580 | */ | |
581 | static int vc4_async_page_flip(struct drm_crtc *crtc, | |
582 | struct drm_framebuffer *fb, | |
583 | struct drm_pending_vblank_event *event, | |
584 | uint32_t flags) | |
585 | { | |
586 | struct drm_device *dev = crtc->dev; | |
587 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
588 | struct drm_plane *plane = crtc->primary; | |
589 | int ret = 0; | |
590 | struct vc4_async_flip_state *flip_state; | |
591 | struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); | |
592 | struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); | |
593 | ||
594 | flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); | |
595 | if (!flip_state) | |
596 | return -ENOMEM; | |
597 | ||
598 | drm_framebuffer_reference(fb); | |
599 | flip_state->fb = fb; | |
600 | flip_state->crtc = crtc; | |
601 | flip_state->event = event; | |
602 | ||
603 | /* Make sure all other async modesetes have landed. */ | |
604 | ret = down_interruptible(&vc4->async_modeset); | |
605 | if (ret) { | |
48627eb8 | 606 | drm_framebuffer_unreference(fb); |
b501bacc EA |
607 | kfree(flip_state); |
608 | return ret; | |
609 | } | |
610 | ||
ee7c10e1 MK |
611 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
612 | ||
b501bacc EA |
613 | /* Immediately update the plane's legacy fb pointer, so that later |
614 | * modeset prep sees the state that will be present when the semaphore | |
615 | * is released. | |
616 | */ | |
617 | drm_atomic_set_fb_for_plane(plane->state, fb); | |
618 | plane->fb = fb; | |
619 | ||
620 | vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, | |
621 | vc4_async_page_flip_complete); | |
622 | ||
623 | /* Driver takes ownership of state on successful async commit. */ | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int vc4_page_flip(struct drm_crtc *crtc, | |
628 | struct drm_framebuffer *fb, | |
629 | struct drm_pending_vblank_event *event, | |
630 | uint32_t flags) | |
631 | { | |
632 | if (flags & DRM_MODE_PAGE_FLIP_ASYNC) | |
633 | return vc4_async_page_flip(crtc, fb, event, flags); | |
634 | else | |
635 | return drm_atomic_helper_page_flip(crtc, fb, event, flags); | |
636 | } | |
637 | ||
d8dbf44f EA |
638 | static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) |
639 | { | |
640 | struct vc4_crtc_state *vc4_state; | |
641 | ||
642 | vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); | |
643 | if (!vc4_state) | |
644 | return NULL; | |
645 | ||
646 | __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); | |
647 | return &vc4_state->base; | |
648 | } | |
649 | ||
650 | static void vc4_crtc_destroy_state(struct drm_crtc *crtc, | |
651 | struct drm_crtc_state *state) | |
652 | { | |
653 | struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); | |
654 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); | |
655 | ||
656 | if (vc4_state->mm.allocated) { | |
657 | unsigned long flags; | |
658 | ||
659 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); | |
660 | drm_mm_remove_node(&vc4_state->mm); | |
661 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); | |
662 | ||
663 | } | |
664 | ||
ec2dc6a0 | 665 | __drm_atomic_helper_crtc_destroy_state(state); |
d8dbf44f EA |
666 | } |
667 | ||
c8b75bca EA |
668 | static const struct drm_crtc_funcs vc4_crtc_funcs = { |
669 | .set_config = drm_atomic_helper_set_config, | |
670 | .destroy = vc4_crtc_destroy, | |
b501bacc | 671 | .page_flip = vc4_page_flip, |
c8b75bca EA |
672 | .set_property = NULL, |
673 | .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ | |
674 | .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ | |
675 | .reset = drm_atomic_helper_crtc_reset, | |
d8dbf44f EA |
676 | .atomic_duplicate_state = vc4_crtc_duplicate_state, |
677 | .atomic_destroy_state = vc4_crtc_destroy_state, | |
e582b6c7 | 678 | .gamma_set = vc4_crtc_gamma_set, |
c8b75bca EA |
679 | }; |
680 | ||
681 | static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { | |
682 | .mode_set_nofb = vc4_crtc_mode_set_nofb, | |
683 | .disable = vc4_crtc_disable, | |
684 | .enable = vc4_crtc_enable, | |
685 | .atomic_check = vc4_crtc_atomic_check, | |
686 | .atomic_flush = vc4_crtc_atomic_flush, | |
687 | }; | |
688 | ||
c8b75bca EA |
689 | static const struct vc4_crtc_data pv0_data = { |
690 | .hvs_channel = 0, | |
691 | .encoder0_type = VC4_ENCODER_TYPE_DSI0, | |
692 | .encoder1_type = VC4_ENCODER_TYPE_DPI, | |
693 | }; | |
694 | ||
695 | static const struct vc4_crtc_data pv1_data = { | |
696 | .hvs_channel = 2, | |
697 | .encoder0_type = VC4_ENCODER_TYPE_DSI1, | |
698 | .encoder1_type = VC4_ENCODER_TYPE_SMI, | |
699 | }; | |
700 | ||
701 | static const struct vc4_crtc_data pv2_data = { | |
702 | .hvs_channel = 1, | |
703 | .encoder0_type = VC4_ENCODER_TYPE_VEC, | |
704 | .encoder1_type = VC4_ENCODER_TYPE_HDMI, | |
705 | }; | |
706 | ||
707 | static const struct of_device_id vc4_crtc_dt_match[] = { | |
708 | { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data }, | |
709 | { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data }, | |
710 | { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data }, | |
711 | {} | |
712 | }; | |
713 | ||
714 | static void vc4_set_crtc_possible_masks(struct drm_device *drm, | |
715 | struct drm_crtc *crtc) | |
716 | { | |
717 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
718 | struct drm_encoder *encoder; | |
719 | ||
720 | drm_for_each_encoder(encoder, drm) { | |
721 | struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); | |
722 | ||
723 | if (vc4_encoder->type == vc4_crtc->data->encoder0_type) { | |
724 | vc4_encoder->clock_select = 0; | |
725 | encoder->possible_crtcs |= drm_crtc_mask(crtc); | |
726 | } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) { | |
727 | vc4_encoder->clock_select = 1; | |
728 | encoder->possible_crtcs |= drm_crtc_mask(crtc); | |
729 | } | |
730 | } | |
731 | } | |
732 | ||
733 | static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) | |
734 | { | |
735 | struct platform_device *pdev = to_platform_device(dev); | |
736 | struct drm_device *drm = dev_get_drvdata(master); | |
737 | struct vc4_dev *vc4 = to_vc4_dev(drm); | |
738 | struct vc4_crtc *vc4_crtc; | |
739 | struct drm_crtc *crtc; | |
fc2d6f1e | 740 | struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp; |
c8b75bca | 741 | const struct of_device_id *match; |
fc2d6f1e | 742 | int ret, i; |
c8b75bca EA |
743 | |
744 | vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); | |
745 | if (!vc4_crtc) | |
746 | return -ENOMEM; | |
747 | crtc = &vc4_crtc->base; | |
748 | ||
749 | match = of_match_device(vc4_crtc_dt_match, dev); | |
750 | if (!match) | |
751 | return -ENODEV; | |
752 | vc4_crtc->data = match->data; | |
753 | ||
754 | vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); | |
755 | if (IS_ERR(vc4_crtc->regs)) | |
756 | return PTR_ERR(vc4_crtc->regs); | |
757 | ||
758 | /* For now, we create just the primary and the legacy cursor | |
759 | * planes. We should be able to stack more planes on easily, | |
760 | * but to do that we would need to compute the bandwidth | |
761 | * requirement of the plane configuration, and reject ones | |
762 | * that will take too much. | |
763 | */ | |
764 | primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); | |
79513237 | 765 | if (IS_ERR(primary_plane)) { |
c8b75bca EA |
766 | dev_err(dev, "failed to construct primary plane\n"); |
767 | ret = PTR_ERR(primary_plane); | |
768 | goto err; | |
769 | } | |
770 | ||
fc2d6f1e | 771 | drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, |
f9882876 | 772 | &vc4_crtc_funcs, NULL); |
c8b75bca EA |
773 | drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); |
774 | primary_plane->crtc = crtc; | |
c8b75bca EA |
775 | vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc; |
776 | vc4_crtc->channel = vc4_crtc->data->hvs_channel; | |
e582b6c7 | 777 | drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); |
c8b75bca | 778 | |
fc2d6f1e EA |
779 | /* Set up some arbitrary number of planes. We're not limited |
780 | * by a set number of physical registers, just the space in | |
781 | * the HVS (16k) and how small an plane can be (28 bytes). | |
782 | * However, each plane we set up takes up some memory, and | |
783 | * increases the cost of looping over planes, which atomic | |
784 | * modesetting does quite a bit. As a result, we pick a | |
785 | * modest number of planes to expose, that should hopefully | |
786 | * still cover any sane usecase. | |
787 | */ | |
788 | for (i = 0; i < 8; i++) { | |
789 | struct drm_plane *plane = | |
790 | vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY); | |
791 | ||
792 | if (IS_ERR(plane)) | |
793 | continue; | |
794 | ||
795 | plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
796 | } | |
797 | ||
798 | /* Set up the legacy cursor after overlay initialization, | |
799 | * since we overlay planes on the CRTC in the order they were | |
800 | * initialized. | |
801 | */ | |
802 | cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); | |
803 | if (!IS_ERR(cursor_plane)) { | |
804 | cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
805 | cursor_plane->crtc = crtc; | |
806 | crtc->cursor = cursor_plane; | |
807 | } | |
808 | ||
c8b75bca EA |
809 | CRTC_WRITE(PV_INTEN, 0); |
810 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); | |
811 | ret = devm_request_irq(dev, platform_get_irq(pdev, 0), | |
812 | vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc); | |
813 | if (ret) | |
fc2d6f1e | 814 | goto err_destroy_planes; |
c8b75bca EA |
815 | |
816 | vc4_set_crtc_possible_masks(drm, crtc); | |
817 | ||
e582b6c7 EA |
818 | for (i = 0; i < crtc->gamma_size; i++) { |
819 | vc4_crtc->lut_r[i] = i; | |
820 | vc4_crtc->lut_g[i] = i; | |
821 | vc4_crtc->lut_b[i] = i; | |
822 | } | |
823 | ||
c8b75bca EA |
824 | platform_set_drvdata(pdev, vc4_crtc); |
825 | ||
826 | return 0; | |
827 | ||
fc2d6f1e EA |
828 | err_destroy_planes: |
829 | list_for_each_entry_safe(destroy_plane, temp, | |
830 | &drm->mode_config.plane_list, head) { | |
831 | if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc)) | |
832 | destroy_plane->funcs->destroy(destroy_plane); | |
833 | } | |
c8b75bca EA |
834 | err: |
835 | return ret; | |
836 | } | |
837 | ||
838 | static void vc4_crtc_unbind(struct device *dev, struct device *master, | |
839 | void *data) | |
840 | { | |
841 | struct platform_device *pdev = to_platform_device(dev); | |
842 | struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); | |
843 | ||
844 | vc4_crtc_destroy(&vc4_crtc->base); | |
845 | ||
846 | CRTC_WRITE(PV_INTEN, 0); | |
847 | ||
848 | platform_set_drvdata(pdev, NULL); | |
849 | } | |
850 | ||
851 | static const struct component_ops vc4_crtc_ops = { | |
852 | .bind = vc4_crtc_bind, | |
853 | .unbind = vc4_crtc_unbind, | |
854 | }; | |
855 | ||
856 | static int vc4_crtc_dev_probe(struct platform_device *pdev) | |
857 | { | |
858 | return component_add(&pdev->dev, &vc4_crtc_ops); | |
859 | } | |
860 | ||
861 | static int vc4_crtc_dev_remove(struct platform_device *pdev) | |
862 | { | |
863 | component_del(&pdev->dev, &vc4_crtc_ops); | |
864 | return 0; | |
865 | } | |
866 | ||
867 | struct platform_driver vc4_crtc_driver = { | |
868 | .probe = vc4_crtc_dev_probe, | |
869 | .remove = vc4_crtc_dev_remove, | |
870 | .driver = { | |
871 | .name = "vc4_crtc", | |
872 | .of_match_table = vc4_crtc_dt_match, | |
873 | }, | |
874 | }; |