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d5b1a78a EA |
1 | /* |
2 | * Copyright © 2014 Broadcom | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/platform_device.h> | |
001bdb55 | 26 | #include <linux/pm_runtime.h> |
d5b1a78a EA |
27 | #include <linux/device.h> |
28 | #include <linux/io.h> | |
29 | ||
30 | #include "uapi/drm/vc4_drm.h" | |
31 | #include "vc4_drv.h" | |
32 | #include "vc4_regs.h" | |
33 | #include "vc4_trace.h" | |
34 | ||
35 | static void | |
36 | vc4_queue_hangcheck(struct drm_device *dev) | |
37 | { | |
38 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
39 | ||
40 | mod_timer(&vc4->hangcheck.timer, | |
41 | round_jiffies_up(jiffies + msecs_to_jiffies(100))); | |
42 | } | |
43 | ||
21461365 EA |
44 | struct vc4_hang_state { |
45 | struct drm_vc4_get_hang_state user_state; | |
46 | ||
47 | u32 bo_count; | |
48 | struct drm_gem_object **bo; | |
49 | }; | |
50 | ||
51 | static void | |
52 | vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state) | |
53 | { | |
54 | unsigned int i; | |
55 | ||
21461365 | 56 | for (i = 0; i < state->user_state.bo_count; i++) |
db369729 | 57 | drm_gem_object_unreference_unlocked(state->bo[i]); |
21461365 EA |
58 | |
59 | kfree(state); | |
60 | } | |
61 | ||
62 | int | |
63 | vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, | |
64 | struct drm_file *file_priv) | |
65 | { | |
66 | struct drm_vc4_get_hang_state *get_state = data; | |
67 | struct drm_vc4_get_hang_state_bo *bo_state; | |
68 | struct vc4_hang_state *kernel_state; | |
69 | struct drm_vc4_get_hang_state *state; | |
70 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
71 | unsigned long irqflags; | |
72 | u32 i; | |
65c4777d | 73 | int ret = 0; |
21461365 EA |
74 | |
75 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
76 | kernel_state = vc4->hang_state; | |
77 | if (!kernel_state) { | |
78 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
79 | return -ENOENT; | |
80 | } | |
81 | state = &kernel_state->user_state; | |
82 | ||
83 | /* If the user's array isn't big enough, just return the | |
84 | * required array size. | |
85 | */ | |
86 | if (get_state->bo_count < state->bo_count) { | |
87 | get_state->bo_count = state->bo_count; | |
88 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
89 | return 0; | |
90 | } | |
91 | ||
92 | vc4->hang_state = NULL; | |
93 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
94 | ||
95 | /* Save the user's BO pointer, so we don't stomp it with the memcpy. */ | |
96 | state->bo = get_state->bo; | |
97 | memcpy(get_state, state, sizeof(*state)); | |
98 | ||
99 | bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL); | |
100 | if (!bo_state) { | |
101 | ret = -ENOMEM; | |
102 | goto err_free; | |
103 | } | |
104 | ||
105 | for (i = 0; i < state->bo_count; i++) { | |
106 | struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]); | |
107 | u32 handle; | |
108 | ||
109 | ret = drm_gem_handle_create(file_priv, kernel_state->bo[i], | |
110 | &handle); | |
111 | ||
112 | if (ret) { | |
113 | state->bo_count = i - 1; | |
114 | goto err; | |
115 | } | |
116 | bo_state[i].handle = handle; | |
117 | bo_state[i].paddr = vc4_bo->base.paddr; | |
118 | bo_state[i].size = vc4_bo->base.base.size; | |
119 | } | |
120 | ||
65c4777d DC |
121 | if (copy_to_user((void __user *)(uintptr_t)get_state->bo, |
122 | bo_state, | |
123 | state->bo_count * sizeof(*bo_state))) | |
124 | ret = -EFAULT; | |
125 | ||
21461365 EA |
126 | kfree(bo_state); |
127 | ||
128 | err_free: | |
129 | ||
130 | vc4_free_hang_state(dev, kernel_state); | |
131 | ||
132 | err: | |
133 | return ret; | |
134 | } | |
135 | ||
136 | static void | |
137 | vc4_save_hang_state(struct drm_device *dev) | |
138 | { | |
139 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
140 | struct drm_vc4_get_hang_state *state; | |
141 | struct vc4_hang_state *kernel_state; | |
ca26d28b | 142 | struct vc4_exec_info *exec[2]; |
21461365 EA |
143 | struct vc4_bo *bo; |
144 | unsigned long irqflags; | |
ca26d28b | 145 | unsigned int i, j, unref_list_count, prev_idx; |
21461365 | 146 | |
7e5082fb | 147 | kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL); |
21461365 EA |
148 | if (!kernel_state) |
149 | return; | |
150 | ||
151 | state = &kernel_state->user_state; | |
152 | ||
153 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
ca26d28b VG |
154 | exec[0] = vc4_first_bin_job(vc4); |
155 | exec[1] = vc4_first_render_job(vc4); | |
156 | if (!exec[0] && !exec[1]) { | |
21461365 EA |
157 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); |
158 | return; | |
159 | } | |
160 | ||
ca26d28b VG |
161 | /* Get the bos from both binner and renderer into hang state. */ |
162 | state->bo_count = 0; | |
163 | for (i = 0; i < 2; i++) { | |
164 | if (!exec[i]) | |
165 | continue; | |
166 | ||
167 | unref_list_count = 0; | |
168 | list_for_each_entry(bo, &exec[i]->unref_list, unref_head) | |
169 | unref_list_count++; | |
170 | state->bo_count += exec[i]->bo_count + unref_list_count; | |
171 | } | |
172 | ||
173 | kernel_state->bo = kcalloc(state->bo_count, | |
174 | sizeof(*kernel_state->bo), GFP_ATOMIC); | |
21461365 | 175 | |
21461365 EA |
176 | if (!kernel_state->bo) { |
177 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
178 | return; | |
179 | } | |
180 | ||
ca26d28b VG |
181 | prev_idx = 0; |
182 | for (i = 0; i < 2; i++) { | |
183 | if (!exec[i]) | |
184 | continue; | |
21461365 | 185 | |
ca26d28b VG |
186 | for (j = 0; j < exec[i]->bo_count; j++) { |
187 | drm_gem_object_reference(&exec[i]->bo[j]->base); | |
188 | kernel_state->bo[j + prev_idx] = &exec[i]->bo[j]->base; | |
189 | } | |
190 | ||
191 | list_for_each_entry(bo, &exec[i]->unref_list, unref_head) { | |
192 | drm_gem_object_reference(&bo->base.base); | |
193 | kernel_state->bo[j + prev_idx] = &bo->base.base; | |
194 | j++; | |
195 | } | |
196 | prev_idx = j + 1; | |
21461365 EA |
197 | } |
198 | ||
ca26d28b VG |
199 | if (exec[0]) |
200 | state->start_bin = exec[0]->ct0ca; | |
201 | if (exec[1]) | |
202 | state->start_render = exec[1]->ct1ca; | |
21461365 EA |
203 | |
204 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
205 | ||
206 | state->ct0ca = V3D_READ(V3D_CTNCA(0)); | |
207 | state->ct0ea = V3D_READ(V3D_CTNEA(0)); | |
208 | ||
209 | state->ct1ca = V3D_READ(V3D_CTNCA(1)); | |
210 | state->ct1ea = V3D_READ(V3D_CTNEA(1)); | |
211 | ||
212 | state->ct0cs = V3D_READ(V3D_CTNCS(0)); | |
213 | state->ct1cs = V3D_READ(V3D_CTNCS(1)); | |
214 | ||
215 | state->ct0ra0 = V3D_READ(V3D_CT00RA0); | |
216 | state->ct1ra0 = V3D_READ(V3D_CT01RA0); | |
217 | ||
218 | state->bpca = V3D_READ(V3D_BPCA); | |
219 | state->bpcs = V3D_READ(V3D_BPCS); | |
220 | state->bpoa = V3D_READ(V3D_BPOA); | |
221 | state->bpos = V3D_READ(V3D_BPOS); | |
222 | ||
223 | state->vpmbase = V3D_READ(V3D_VPMBASE); | |
224 | ||
225 | state->dbge = V3D_READ(V3D_DBGE); | |
226 | state->fdbgo = V3D_READ(V3D_FDBGO); | |
227 | state->fdbgb = V3D_READ(V3D_FDBGB); | |
228 | state->fdbgr = V3D_READ(V3D_FDBGR); | |
229 | state->fdbgs = V3D_READ(V3D_FDBGS); | |
230 | state->errstat = V3D_READ(V3D_ERRSTAT); | |
231 | ||
232 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
233 | if (vc4->hang_state) { | |
234 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
235 | vc4_free_hang_state(dev, kernel_state); | |
236 | } else { | |
237 | vc4->hang_state = kernel_state; | |
238 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
239 | } | |
240 | } | |
241 | ||
d5b1a78a EA |
242 | static void |
243 | vc4_reset(struct drm_device *dev) | |
244 | { | |
245 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
246 | ||
247 | DRM_INFO("Resetting GPU.\n"); | |
36cb6253 EA |
248 | |
249 | mutex_lock(&vc4->power_lock); | |
250 | if (vc4->power_refcount) { | |
251 | /* Power the device off and back on the by dropping the | |
252 | * reference on runtime PM. | |
253 | */ | |
254 | pm_runtime_put_sync_suspend(&vc4->v3d->pdev->dev); | |
255 | pm_runtime_get_sync(&vc4->v3d->pdev->dev); | |
256 | } | |
257 | mutex_unlock(&vc4->power_lock); | |
d5b1a78a EA |
258 | |
259 | vc4_irq_reset(dev); | |
260 | ||
261 | /* Rearm the hangcheck -- another job might have been waiting | |
262 | * for our hung one to get kicked off, and vc4_irq_reset() | |
263 | * would have started it. | |
264 | */ | |
265 | vc4_queue_hangcheck(dev); | |
266 | } | |
267 | ||
268 | static void | |
269 | vc4_reset_work(struct work_struct *work) | |
270 | { | |
271 | struct vc4_dev *vc4 = | |
272 | container_of(work, struct vc4_dev, hangcheck.reset_work); | |
273 | ||
21461365 EA |
274 | vc4_save_hang_state(vc4->dev); |
275 | ||
d5b1a78a EA |
276 | vc4_reset(vc4->dev); |
277 | } | |
278 | ||
279 | static void | |
280 | vc4_hangcheck_elapsed(unsigned long data) | |
281 | { | |
282 | struct drm_device *dev = (struct drm_device *)data; | |
283 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
284 | uint32_t ct0ca, ct1ca; | |
c4ce60dc | 285 | unsigned long irqflags; |
ca26d28b | 286 | struct vc4_exec_info *bin_exec, *render_exec; |
c4ce60dc EA |
287 | |
288 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
ca26d28b VG |
289 | |
290 | bin_exec = vc4_first_bin_job(vc4); | |
291 | render_exec = vc4_first_render_job(vc4); | |
d5b1a78a EA |
292 | |
293 | /* If idle, we can stop watching for hangs. */ | |
ca26d28b | 294 | if (!bin_exec && !render_exec) { |
c4ce60dc | 295 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); |
d5b1a78a | 296 | return; |
c4ce60dc | 297 | } |
d5b1a78a EA |
298 | |
299 | ct0ca = V3D_READ(V3D_CTNCA(0)); | |
300 | ct1ca = V3D_READ(V3D_CTNCA(1)); | |
301 | ||
302 | /* If we've made any progress in execution, rearm the timer | |
303 | * and wait. | |
304 | */ | |
ca26d28b VG |
305 | if ((bin_exec && ct0ca != bin_exec->last_ct0ca) || |
306 | (render_exec && ct1ca != render_exec->last_ct1ca)) { | |
307 | if (bin_exec) | |
308 | bin_exec->last_ct0ca = ct0ca; | |
309 | if (render_exec) | |
310 | render_exec->last_ct1ca = ct1ca; | |
c4ce60dc | 311 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); |
d5b1a78a EA |
312 | vc4_queue_hangcheck(dev); |
313 | return; | |
314 | } | |
315 | ||
c4ce60dc EA |
316 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); |
317 | ||
d5b1a78a EA |
318 | /* We've gone too long with no progress, reset. This has to |
319 | * be done from a work struct, since resetting can sleep and | |
320 | * this timer hook isn't allowed to. | |
321 | */ | |
322 | schedule_work(&vc4->hangcheck.reset_work); | |
323 | } | |
324 | ||
325 | static void | |
326 | submit_cl(struct drm_device *dev, uint32_t thread, uint32_t start, uint32_t end) | |
327 | { | |
328 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
329 | ||
330 | /* Set the current and end address of the control list. | |
331 | * Writing the end register is what starts the job. | |
332 | */ | |
333 | V3D_WRITE(V3D_CTNCA(thread), start); | |
334 | V3D_WRITE(V3D_CTNEA(thread), end); | |
335 | } | |
336 | ||
337 | int | |
338 | vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, uint64_t timeout_ns, | |
339 | bool interruptible) | |
340 | { | |
341 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
342 | int ret = 0; | |
343 | unsigned long timeout_expire; | |
344 | DEFINE_WAIT(wait); | |
345 | ||
346 | if (vc4->finished_seqno >= seqno) | |
347 | return 0; | |
348 | ||
349 | if (timeout_ns == 0) | |
350 | return -ETIME; | |
351 | ||
352 | timeout_expire = jiffies + nsecs_to_jiffies(timeout_ns); | |
353 | ||
354 | trace_vc4_wait_for_seqno_begin(dev, seqno, timeout_ns); | |
355 | for (;;) { | |
356 | prepare_to_wait(&vc4->job_wait_queue, &wait, | |
357 | interruptible ? TASK_INTERRUPTIBLE : | |
358 | TASK_UNINTERRUPTIBLE); | |
359 | ||
360 | if (interruptible && signal_pending(current)) { | |
361 | ret = -ERESTARTSYS; | |
362 | break; | |
363 | } | |
364 | ||
365 | if (vc4->finished_seqno >= seqno) | |
366 | break; | |
367 | ||
368 | if (timeout_ns != ~0ull) { | |
369 | if (time_after_eq(jiffies, timeout_expire)) { | |
370 | ret = -ETIME; | |
371 | break; | |
372 | } | |
373 | schedule_timeout(timeout_expire - jiffies); | |
374 | } else { | |
375 | schedule(); | |
376 | } | |
377 | } | |
378 | ||
379 | finish_wait(&vc4->job_wait_queue, &wait); | |
380 | trace_vc4_wait_for_seqno_end(dev, seqno); | |
381 | ||
13cf8909 | 382 | return ret; |
d5b1a78a EA |
383 | } |
384 | ||
385 | static void | |
386 | vc4_flush_caches(struct drm_device *dev) | |
387 | { | |
388 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
389 | ||
390 | /* Flush the GPU L2 caches. These caches sit on top of system | |
391 | * L3 (the 128kb or so shared with the CPU), and are | |
392 | * non-allocating in the L3. | |
393 | */ | |
394 | V3D_WRITE(V3D_L2CACTL, | |
395 | V3D_L2CACTL_L2CCLR); | |
396 | ||
397 | V3D_WRITE(V3D_SLCACTL, | |
398 | VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | | |
399 | VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | | |
400 | VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | | |
401 | VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); | |
402 | } | |
403 | ||
404 | /* Sets the registers for the next job to be actually be executed in | |
405 | * the hardware. | |
406 | * | |
407 | * The job_lock should be held during this. | |
408 | */ | |
409 | void | |
ca26d28b | 410 | vc4_submit_next_bin_job(struct drm_device *dev) |
d5b1a78a EA |
411 | { |
412 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
ca26d28b | 413 | struct vc4_exec_info *exec; |
d5b1a78a | 414 | |
ca26d28b VG |
415 | again: |
416 | exec = vc4_first_bin_job(vc4); | |
d5b1a78a EA |
417 | if (!exec) |
418 | return; | |
419 | ||
420 | vc4_flush_caches(dev); | |
421 | ||
ca26d28b VG |
422 | /* Either put the job in the binner if it uses the binner, or |
423 | * immediately move it to the to-be-rendered queue. | |
424 | */ | |
425 | if (exec->ct0ca != exec->ct0ea) { | |
d5b1a78a | 426 | submit_cl(dev, 0, exec->ct0ca, exec->ct0ea); |
ca26d28b VG |
427 | } else { |
428 | vc4_move_job_to_render(dev, exec); | |
429 | goto again; | |
430 | } | |
431 | } | |
432 | ||
433 | void | |
434 | vc4_submit_next_render_job(struct drm_device *dev) | |
435 | { | |
436 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
437 | struct vc4_exec_info *exec = vc4_first_render_job(vc4); | |
438 | ||
439 | if (!exec) | |
440 | return; | |
441 | ||
d5b1a78a EA |
442 | submit_cl(dev, 1, exec->ct1ca, exec->ct1ea); |
443 | } | |
444 | ||
ca26d28b VG |
445 | void |
446 | vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec) | |
447 | { | |
448 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
449 | bool was_empty = list_empty(&vc4->render_job_list); | |
450 | ||
451 | list_move_tail(&exec->head, &vc4->render_job_list); | |
452 | if (was_empty) | |
453 | vc4_submit_next_render_job(dev); | |
454 | } | |
455 | ||
d5b1a78a EA |
456 | static void |
457 | vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno) | |
458 | { | |
459 | struct vc4_bo *bo; | |
460 | unsigned i; | |
461 | ||
462 | for (i = 0; i < exec->bo_count; i++) { | |
463 | bo = to_vc4_bo(&exec->bo[i]->base); | |
464 | bo->seqno = seqno; | |
465 | } | |
466 | ||
467 | list_for_each_entry(bo, &exec->unref_list, unref_head) { | |
468 | bo->seqno = seqno; | |
469 | } | |
470 | } | |
471 | ||
472 | /* Queues a struct vc4_exec_info for execution. If no job is | |
473 | * currently executing, then submits it. | |
474 | * | |
475 | * Unlike most GPUs, our hardware only handles one command list at a | |
476 | * time. To queue multiple jobs at once, we'd need to edit the | |
477 | * previous command list to have a jump to the new one at the end, and | |
478 | * then bump the end address. That's a change for a later date, | |
479 | * though. | |
480 | */ | |
481 | static void | |
482 | vc4_queue_submit(struct drm_device *dev, struct vc4_exec_info *exec) | |
483 | { | |
484 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
485 | uint64_t seqno; | |
486 | unsigned long irqflags; | |
487 | ||
488 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
489 | ||
490 | seqno = ++vc4->emit_seqno; | |
491 | exec->seqno = seqno; | |
492 | vc4_update_bo_seqnos(exec, seqno); | |
493 | ||
ca26d28b | 494 | list_add_tail(&exec->head, &vc4->bin_job_list); |
d5b1a78a EA |
495 | |
496 | /* If no job was executing, kick ours off. Otherwise, it'll | |
ca26d28b | 497 | * get started when the previous job's flush done interrupt |
d5b1a78a EA |
498 | * occurs. |
499 | */ | |
ca26d28b VG |
500 | if (vc4_first_bin_job(vc4) == exec) { |
501 | vc4_submit_next_bin_job(dev); | |
d5b1a78a EA |
502 | vc4_queue_hangcheck(dev); |
503 | } | |
504 | ||
505 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
506 | } | |
507 | ||
508 | /** | |
509 | * Looks up a bunch of GEM handles for BOs and stores the array for | |
510 | * use in the command validator that actually writes relocated | |
511 | * addresses pointing to them. | |
512 | */ | |
513 | static int | |
514 | vc4_cl_lookup_bos(struct drm_device *dev, | |
515 | struct drm_file *file_priv, | |
516 | struct vc4_exec_info *exec) | |
517 | { | |
518 | struct drm_vc4_submit_cl *args = exec->args; | |
519 | uint32_t *handles; | |
520 | int ret = 0; | |
521 | int i; | |
522 | ||
523 | exec->bo_count = args->bo_handle_count; | |
524 | ||
525 | if (!exec->bo_count) { | |
526 | /* See comment on bo_index for why we have to check | |
527 | * this. | |
528 | */ | |
529 | DRM_ERROR("Rendering requires BOs to validate\n"); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
ece7267d EA |
533 | exec->bo = drm_calloc_large(exec->bo_count, |
534 | sizeof(struct drm_gem_cma_object *)); | |
d5b1a78a EA |
535 | if (!exec->bo) { |
536 | DRM_ERROR("Failed to allocate validated BO pointers\n"); | |
537 | return -ENOMEM; | |
538 | } | |
539 | ||
540 | handles = drm_malloc_ab(exec->bo_count, sizeof(uint32_t)); | |
541 | if (!handles) { | |
542 | DRM_ERROR("Failed to allocate incoming GEM handles\n"); | |
543 | goto fail; | |
544 | } | |
545 | ||
546 | ret = copy_from_user(handles, | |
547 | (void __user *)(uintptr_t)args->bo_handles, | |
548 | exec->bo_count * sizeof(uint32_t)); | |
549 | if (ret) { | |
550 | DRM_ERROR("Failed to copy in GEM handles\n"); | |
551 | goto fail; | |
552 | } | |
553 | ||
554 | spin_lock(&file_priv->table_lock); | |
555 | for (i = 0; i < exec->bo_count; i++) { | |
556 | struct drm_gem_object *bo = idr_find(&file_priv->object_idr, | |
557 | handles[i]); | |
558 | if (!bo) { | |
559 | DRM_ERROR("Failed to look up GEM BO %d: %d\n", | |
560 | i, handles[i]); | |
561 | ret = -EINVAL; | |
562 | spin_unlock(&file_priv->table_lock); | |
563 | goto fail; | |
564 | } | |
565 | drm_gem_object_reference(bo); | |
566 | exec->bo[i] = (struct drm_gem_cma_object *)bo; | |
567 | } | |
568 | spin_unlock(&file_priv->table_lock); | |
569 | ||
570 | fail: | |
d5fb46e0 | 571 | drm_free_large(handles); |
552416c1 | 572 | return ret; |
d5b1a78a EA |
573 | } |
574 | ||
575 | static int | |
576 | vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) | |
577 | { | |
578 | struct drm_vc4_submit_cl *args = exec->args; | |
579 | void *temp = NULL; | |
580 | void *bin; | |
581 | int ret = 0; | |
582 | uint32_t bin_offset = 0; | |
583 | uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size, | |
584 | 16); | |
585 | uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size; | |
586 | uint32_t exec_size = uniforms_offset + args->uniforms_size; | |
587 | uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) * | |
588 | args->shader_rec_count); | |
589 | struct vc4_bo *bo; | |
590 | ||
591 | if (uniforms_offset < shader_rec_offset || | |
592 | exec_size < uniforms_offset || | |
593 | args->shader_rec_count >= (UINT_MAX / | |
594 | sizeof(struct vc4_shader_state)) || | |
595 | temp_size < exec_size) { | |
596 | DRM_ERROR("overflow in exec arguments\n"); | |
597 | goto fail; | |
598 | } | |
599 | ||
600 | /* Allocate space where we'll store the copied in user command lists | |
601 | * and shader records. | |
602 | * | |
603 | * We don't just copy directly into the BOs because we need to | |
604 | * read the contents back for validation, and I think the | |
605 | * bo->vaddr is uncached access. | |
606 | */ | |
ece7267d | 607 | temp = drm_malloc_ab(temp_size, 1); |
d5b1a78a EA |
608 | if (!temp) { |
609 | DRM_ERROR("Failed to allocate storage for copying " | |
610 | "in bin/render CLs.\n"); | |
611 | ret = -ENOMEM; | |
612 | goto fail; | |
613 | } | |
614 | bin = temp + bin_offset; | |
615 | exec->shader_rec_u = temp + shader_rec_offset; | |
616 | exec->uniforms_u = temp + uniforms_offset; | |
617 | exec->shader_state = temp + exec_size; | |
618 | exec->shader_state_size = args->shader_rec_count; | |
619 | ||
65c4777d DC |
620 | if (copy_from_user(bin, |
621 | (void __user *)(uintptr_t)args->bin_cl, | |
622 | args->bin_cl_size)) { | |
623 | ret = -EFAULT; | |
d5b1a78a EA |
624 | goto fail; |
625 | } | |
626 | ||
65c4777d DC |
627 | if (copy_from_user(exec->shader_rec_u, |
628 | (void __user *)(uintptr_t)args->shader_rec, | |
629 | args->shader_rec_size)) { | |
630 | ret = -EFAULT; | |
d5b1a78a EA |
631 | goto fail; |
632 | } | |
633 | ||
65c4777d DC |
634 | if (copy_from_user(exec->uniforms_u, |
635 | (void __user *)(uintptr_t)args->uniforms, | |
636 | args->uniforms_size)) { | |
637 | ret = -EFAULT; | |
d5b1a78a EA |
638 | goto fail; |
639 | } | |
640 | ||
641 | bo = vc4_bo_create(dev, exec_size, true); | |
2c68f1fc | 642 | if (IS_ERR(bo)) { |
d5b1a78a | 643 | DRM_ERROR("Couldn't allocate BO for binning\n"); |
2c68f1fc | 644 | ret = PTR_ERR(bo); |
d5b1a78a EA |
645 | goto fail; |
646 | } | |
647 | exec->exec_bo = &bo->base; | |
648 | ||
649 | list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head, | |
650 | &exec->unref_list); | |
651 | ||
652 | exec->ct0ca = exec->exec_bo->paddr + bin_offset; | |
653 | ||
654 | exec->bin_u = bin; | |
655 | ||
656 | exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset; | |
657 | exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset; | |
658 | exec->shader_rec_size = args->shader_rec_size; | |
659 | ||
660 | exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset; | |
661 | exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset; | |
662 | exec->uniforms_size = args->uniforms_size; | |
663 | ||
664 | ret = vc4_validate_bin_cl(dev, | |
665 | exec->exec_bo->vaddr + bin_offset, | |
666 | bin, | |
667 | exec); | |
668 | if (ret) | |
669 | goto fail; | |
670 | ||
671 | ret = vc4_validate_shader_recs(dev, exec); | |
672 | ||
673 | fail: | |
ece7267d | 674 | drm_free_large(temp); |
d5b1a78a EA |
675 | return ret; |
676 | } | |
677 | ||
678 | static void | |
679 | vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec) | |
680 | { | |
001bdb55 | 681 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
d5b1a78a EA |
682 | unsigned i; |
683 | ||
d5b1a78a EA |
684 | if (exec->bo) { |
685 | for (i = 0; i < exec->bo_count; i++) | |
db369729 | 686 | drm_gem_object_unreference_unlocked(&exec->bo[i]->base); |
ece7267d | 687 | drm_free_large(exec->bo); |
d5b1a78a EA |
688 | } |
689 | ||
690 | while (!list_empty(&exec->unref_list)) { | |
691 | struct vc4_bo *bo = list_first_entry(&exec->unref_list, | |
692 | struct vc4_bo, unref_head); | |
693 | list_del(&bo->unref_head); | |
db369729 | 694 | drm_gem_object_unreference_unlocked(&bo->base.base); |
d5b1a78a | 695 | } |
d5b1a78a | 696 | |
36cb6253 EA |
697 | mutex_lock(&vc4->power_lock); |
698 | if (--vc4->power_refcount == 0) | |
699 | pm_runtime_put(&vc4->v3d->pdev->dev); | |
700 | mutex_unlock(&vc4->power_lock); | |
001bdb55 | 701 | |
d5b1a78a EA |
702 | kfree(exec); |
703 | } | |
704 | ||
705 | void | |
706 | vc4_job_handle_completed(struct vc4_dev *vc4) | |
707 | { | |
708 | unsigned long irqflags; | |
b501bacc | 709 | struct vc4_seqno_cb *cb, *cb_temp; |
d5b1a78a EA |
710 | |
711 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
712 | while (!list_empty(&vc4->job_done_list)) { | |
713 | struct vc4_exec_info *exec = | |
714 | list_first_entry(&vc4->job_done_list, | |
715 | struct vc4_exec_info, head); | |
716 | list_del(&exec->head); | |
717 | ||
718 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
719 | vc4_complete_exec(vc4->dev, exec); | |
720 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
721 | } | |
b501bacc EA |
722 | |
723 | list_for_each_entry_safe(cb, cb_temp, &vc4->seqno_cb_list, work.entry) { | |
724 | if (cb->seqno <= vc4->finished_seqno) { | |
725 | list_del_init(&cb->work.entry); | |
726 | schedule_work(&cb->work); | |
727 | } | |
728 | } | |
729 | ||
730 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); | |
731 | } | |
732 | ||
733 | static void vc4_seqno_cb_work(struct work_struct *work) | |
734 | { | |
735 | struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work); | |
736 | ||
737 | cb->func(cb); | |
738 | } | |
739 | ||
740 | int vc4_queue_seqno_cb(struct drm_device *dev, | |
741 | struct vc4_seqno_cb *cb, uint64_t seqno, | |
742 | void (*func)(struct vc4_seqno_cb *cb)) | |
743 | { | |
744 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
745 | int ret = 0; | |
746 | unsigned long irqflags; | |
747 | ||
748 | cb->func = func; | |
749 | INIT_WORK(&cb->work, vc4_seqno_cb_work); | |
750 | ||
751 | spin_lock_irqsave(&vc4->job_lock, irqflags); | |
752 | if (seqno > vc4->finished_seqno) { | |
753 | cb->seqno = seqno; | |
754 | list_add_tail(&cb->work.entry, &vc4->seqno_cb_list); | |
755 | } else { | |
756 | schedule_work(&cb->work); | |
757 | } | |
d5b1a78a | 758 | spin_unlock_irqrestore(&vc4->job_lock, irqflags); |
b501bacc EA |
759 | |
760 | return ret; | |
d5b1a78a EA |
761 | } |
762 | ||
763 | /* Scheduled when any job has been completed, this walks the list of | |
764 | * jobs that had completed and unrefs their BOs and frees their exec | |
765 | * structs. | |
766 | */ | |
767 | static void | |
768 | vc4_job_done_work(struct work_struct *work) | |
769 | { | |
770 | struct vc4_dev *vc4 = | |
771 | container_of(work, struct vc4_dev, job_done_work); | |
772 | ||
773 | vc4_job_handle_completed(vc4); | |
774 | } | |
775 | ||
776 | static int | |
777 | vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev, | |
778 | uint64_t seqno, | |
779 | uint64_t *timeout_ns) | |
780 | { | |
781 | unsigned long start = jiffies; | |
782 | int ret = vc4_wait_for_seqno(dev, seqno, *timeout_ns, true); | |
783 | ||
784 | if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) { | |
785 | uint64_t delta = jiffies_to_nsecs(jiffies - start); | |
786 | ||
787 | if (*timeout_ns >= delta) | |
788 | *timeout_ns -= delta; | |
789 | } | |
790 | ||
791 | return ret; | |
792 | } | |
793 | ||
794 | int | |
795 | vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, | |
796 | struct drm_file *file_priv) | |
797 | { | |
798 | struct drm_vc4_wait_seqno *args = data; | |
799 | ||
800 | return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno, | |
801 | &args->timeout_ns); | |
802 | } | |
803 | ||
804 | int | |
805 | vc4_wait_bo_ioctl(struct drm_device *dev, void *data, | |
806 | struct drm_file *file_priv) | |
807 | { | |
808 | int ret; | |
809 | struct drm_vc4_wait_bo *args = data; | |
810 | struct drm_gem_object *gem_obj; | |
811 | struct vc4_bo *bo; | |
812 | ||
e0015236 EA |
813 | if (args->pad != 0) |
814 | return -EINVAL; | |
815 | ||
a8ad0bd8 | 816 | gem_obj = drm_gem_object_lookup(file_priv, args->handle); |
d5b1a78a EA |
817 | if (!gem_obj) { |
818 | DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); | |
819 | return -EINVAL; | |
820 | } | |
821 | bo = to_vc4_bo(gem_obj); | |
822 | ||
823 | ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, | |
824 | &args->timeout_ns); | |
825 | ||
826 | drm_gem_object_unreference_unlocked(gem_obj); | |
827 | return ret; | |
828 | } | |
829 | ||
830 | /** | |
831 | * Submits a command list to the VC4. | |
832 | * | |
833 | * This is what is called batchbuffer emitting on other hardware. | |
834 | */ | |
835 | int | |
836 | vc4_submit_cl_ioctl(struct drm_device *dev, void *data, | |
837 | struct drm_file *file_priv) | |
838 | { | |
839 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
840 | struct drm_vc4_submit_cl *args = data; | |
841 | struct vc4_exec_info *exec; | |
36cb6253 | 842 | int ret = 0; |
d5b1a78a EA |
843 | |
844 | if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) { | |
845 | DRM_ERROR("Unknown flags: 0x%02x\n", args->flags); | |
846 | return -EINVAL; | |
847 | } | |
848 | ||
849 | exec = kcalloc(1, sizeof(*exec), GFP_KERNEL); | |
850 | if (!exec) { | |
851 | DRM_ERROR("malloc failure on exec struct\n"); | |
852 | return -ENOMEM; | |
853 | } | |
854 | ||
36cb6253 EA |
855 | mutex_lock(&vc4->power_lock); |
856 | if (vc4->power_refcount++ == 0) | |
857 | ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev); | |
858 | mutex_unlock(&vc4->power_lock); | |
001bdb55 EA |
859 | if (ret < 0) { |
860 | kfree(exec); | |
861 | return ret; | |
862 | } | |
863 | ||
d5b1a78a EA |
864 | exec->args = args; |
865 | INIT_LIST_HEAD(&exec->unref_list); | |
866 | ||
867 | ret = vc4_cl_lookup_bos(dev, file_priv, exec); | |
868 | if (ret) | |
869 | goto fail; | |
870 | ||
871 | if (exec->args->bin_cl_size != 0) { | |
872 | ret = vc4_get_bcl(dev, exec); | |
873 | if (ret) | |
874 | goto fail; | |
875 | } else { | |
876 | exec->ct0ca = 0; | |
877 | exec->ct0ea = 0; | |
878 | } | |
879 | ||
880 | ret = vc4_get_rcl(dev, exec); | |
881 | if (ret) | |
882 | goto fail; | |
883 | ||
884 | /* Clear this out of the struct we'll be putting in the queue, | |
885 | * since it's part of our stack. | |
886 | */ | |
887 | exec->args = NULL; | |
888 | ||
889 | vc4_queue_submit(dev, exec); | |
890 | ||
891 | /* Return the seqno for our job. */ | |
892 | args->seqno = vc4->emit_seqno; | |
893 | ||
894 | return 0; | |
895 | ||
896 | fail: | |
897 | vc4_complete_exec(vc4->dev, exec); | |
898 | ||
899 | return ret; | |
900 | } | |
901 | ||
902 | void | |
903 | vc4_gem_init(struct drm_device *dev) | |
904 | { | |
905 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
906 | ||
ca26d28b VG |
907 | INIT_LIST_HEAD(&vc4->bin_job_list); |
908 | INIT_LIST_HEAD(&vc4->render_job_list); | |
d5b1a78a | 909 | INIT_LIST_HEAD(&vc4->job_done_list); |
b501bacc | 910 | INIT_LIST_HEAD(&vc4->seqno_cb_list); |
d5b1a78a EA |
911 | spin_lock_init(&vc4->job_lock); |
912 | ||
913 | INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work); | |
914 | setup_timer(&vc4->hangcheck.timer, | |
915 | vc4_hangcheck_elapsed, | |
916 | (unsigned long)dev); | |
917 | ||
918 | INIT_WORK(&vc4->job_done_work, vc4_job_done_work); | |
36cb6253 EA |
919 | |
920 | mutex_init(&vc4->power_lock); | |
d5b1a78a EA |
921 | } |
922 | ||
923 | void | |
924 | vc4_gem_destroy(struct drm_device *dev) | |
925 | { | |
926 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
927 | ||
928 | /* Waiting for exec to finish would need to be done before | |
929 | * unregistering V3D. | |
930 | */ | |
931 | WARN_ON(vc4->emit_seqno != vc4->finished_seqno); | |
932 | ||
933 | /* V3D should already have disabled its interrupt and cleared | |
934 | * the overflow allocation registers. Now free the object. | |
935 | */ | |
936 | if (vc4->overflow_mem) { | |
937 | drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base); | |
938 | vc4->overflow_mem = NULL; | |
939 | } | |
940 | ||
21461365 EA |
941 | if (vc4->hang_state) |
942 | vc4_free_hang_state(dev, vc4->hang_state); | |
def96527 EA |
943 | |
944 | vc4_bo_cache_destroy(dev); | |
d5b1a78a | 945 | } |