Commit | Line | Data |
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22f579c6 | 1 | /* via_dma.c -- DMA support for the VIA Unichrome/Pro |
b5e89ed5 | 2 | * |
22f579c6 DA |
3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. | |
7 | * All Rights Reserved. | |
b5e89ed5 | 8 | * |
22f579c6 DA |
9 | * Copyright 2004 The Unichrome project. |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the | |
20 | * next paragraph) shall be included in all copies or substantial portions | |
21 | * of the Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
b5e89ed5 DA |
26 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
27 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
28 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
22f579c6 DA |
29 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
30 | * | |
b5e89ed5 DA |
31 | * Authors: |
32 | * Tungsten Graphics, | |
33 | * Erdi Chen, | |
22f579c6 DA |
34 | * Thomas Hellstrom. |
35 | */ | |
36 | ||
760285e7 DH |
37 | #include <drm/drmP.h> |
38 | #include <drm/via_drm.h> | |
22f579c6 DA |
39 | #include "via_drv.h" |
40 | #include "via_3d_reg.h" | |
41 | ||
42 | #define CMDBUF_ALIGNMENT_SIZE (0x100) | |
43 | #define CMDBUF_ALIGNMENT_MASK (0x0ff) | |
44 | ||
45 | /* defines for VIA 3D registers */ | |
46 | #define VIA_REG_STATUS 0x400 | |
47 | #define VIA_REG_TRANSET 0x43C | |
48 | #define VIA_REG_TRANSPACE 0x440 | |
49 | ||
50 | /* VIA_REG_STATUS(0x400): Engine Status */ | |
51 | #define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ | |
52 | #define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ | |
53 | #define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ | |
54 | #define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ | |
55 | ||
56 | #define SetReg2DAGP(nReg, nData) { \ | |
57 | *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \ | |
58 | *((uint32_t *)(vb) + 1) = (nData); \ | |
59 | vb = ((uint32_t *)vb) + 2; \ | |
58c1e85a | 60 | dev_priv->dma_low += 8; \ |
22f579c6 DA |
61 | } |
62 | ||
85b2331b | 63 | #define via_flush_write_combine() mb() |
22f579c6 | 64 | |
58c1e85a | 65 | #define VIA_OUT_RING_QW(w1, w2) do { \ |
22f579c6 DA |
66 | *vb++ = (w1); \ |
67 | *vb++ = (w2); \ | |
58c1e85a NK |
68 | dev_priv->dma_low += 8; \ |
69 | } while (0) | |
22f579c6 | 70 | |
58c1e85a NK |
71 | static void via_cmdbuf_start(drm_via_private_t *dev_priv); |
72 | static void via_cmdbuf_pause(drm_via_private_t *dev_priv); | |
73 | static void via_cmdbuf_reset(drm_via_private_t *dev_priv); | |
74 | static void via_cmdbuf_rewind(drm_via_private_t *dev_priv); | |
75 | static int via_wait_idle(drm_via_private_t *dev_priv); | |
76 | static void via_pad_cache(drm_via_private_t *dev_priv, int qwords); | |
22f579c6 DA |
77 | |
78 | /* | |
79 | * Free space in command buffer. | |
80 | */ | |
81 | ||
58c1e85a | 82 | static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) |
22f579c6 | 83 | { |
b5e89ed5 | 84 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
22f579c6 | 85 | uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; |
b5e89ed5 DA |
86 | |
87 | return ((hw_addr <= dev_priv->dma_low) ? | |
88 | (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : | |
22f579c6 DA |
89 | (hw_addr - dev_priv->dma_low)); |
90 | } | |
91 | ||
92 | /* | |
93 | * How much does the command regulator lag behind? | |
94 | */ | |
95 | ||
58c1e85a | 96 | static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv) |
22f579c6 | 97 | { |
b5e89ed5 | 98 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
22f579c6 | 99 | uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; |
b5e89ed5 DA |
100 | |
101 | return ((hw_addr <= dev_priv->dma_low) ? | |
102 | (dev_priv->dma_low - hw_addr) : | |
22f579c6 DA |
103 | (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); |
104 | } | |
105 | ||
106 | /* | |
107 | * Check that the given size fits in the buffer, otherwise wait. | |
108 | */ | |
109 | ||
110 | static inline int | |
58c1e85a | 111 | via_cmdbuf_wait(drm_via_private_t *dev_priv, unsigned int size) |
22f579c6 DA |
112 | { |
113 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
114 | uint32_t cur_addr, hw_addr, next_addr; | |
115 | volatile uint32_t *hw_addr_ptr; | |
116 | uint32_t count; | |
117 | hw_addr_ptr = dev_priv->hw_addr_ptr; | |
118 | cur_addr = dev_priv->dma_low; | |
b5e89ed5 | 119 | next_addr = cur_addr + size + 512 * 1024; |
22f579c6 DA |
120 | count = 1000000; |
121 | do { | |
b5e89ed5 | 122 | hw_addr = *hw_addr_ptr - agp_base; |
22f579c6 | 123 | if (count-- == 0) { |
b5e89ed5 DA |
124 | DRM_ERROR |
125 | ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n", | |
126 | hw_addr, cur_addr, next_addr); | |
22f579c6 DA |
127 | return -1; |
128 | } | |
f0fb6d77 TH |
129 | if ((cur_addr < hw_addr) && (next_addr >= hw_addr)) |
130 | msleep(1); | |
22f579c6 DA |
131 | } while ((cur_addr < hw_addr) && (next_addr >= hw_addr)); |
132 | return 0; | |
133 | } | |
134 | ||
22f579c6 DA |
135 | /* |
136 | * Checks whether buffer head has reach the end. Rewind the ring buffer | |
137 | * when necessary. | |
138 | * | |
139 | * Returns virtual pointer to ring buffer. | |
140 | */ | |
141 | ||
142 | static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, | |
143 | unsigned int size) | |
144 | { | |
b5e89ed5 DA |
145 | if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) > |
146 | dev_priv->dma_high) { | |
22f579c6 DA |
147 | via_cmdbuf_rewind(dev_priv); |
148 | } | |
58c1e85a | 149 | if (via_cmdbuf_wait(dev_priv, size) != 0) |
22f579c6 | 150 | return NULL; |
22f579c6 DA |
151 | |
152 | return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); | |
153 | } | |
154 | ||
58c1e85a | 155 | int via_dma_cleanup(struct drm_device *dev) |
22f579c6 DA |
156 | { |
157 | if (dev->dev_private) { | |
158 | drm_via_private_t *dev_priv = | |
b5e89ed5 | 159 | (drm_via_private_t *) dev->dev_private; |
22f579c6 DA |
160 | |
161 | if (dev_priv->ring.virtual_start) { | |
162 | via_cmdbuf_reset(dev_priv); | |
163 | ||
86c1fbd5 | 164 | drm_legacy_ioremapfree(&dev_priv->ring.map, dev); |
22f579c6 DA |
165 | dev_priv->ring.virtual_start = NULL; |
166 | } | |
167 | ||
168 | } | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
58c1e85a NK |
173 | static int via_initialize(struct drm_device *dev, |
174 | drm_via_private_t *dev_priv, | |
175 | drm_via_dma_init_t *init) | |
22f579c6 DA |
176 | { |
177 | if (!dev_priv || !dev_priv->mmio) { | |
178 | DRM_ERROR("via_dma_init called before via_map_init\n"); | |
20caafa6 | 179 | return -EFAULT; |
22f579c6 DA |
180 | } |
181 | ||
182 | if (dev_priv->ring.virtual_start != NULL) { | |
3e684eae | 183 | DRM_ERROR("called again without calling cleanup\n"); |
20caafa6 | 184 | return -EFAULT; |
22f579c6 DA |
185 | } |
186 | ||
187 | if (!dev->agp || !dev->agp->base) { | |
3e684eae | 188 | DRM_ERROR("called with no agp memory available\n"); |
20caafa6 | 189 | return -EFAULT; |
22f579c6 DA |
190 | } |
191 | ||
756db73d TH |
192 | if (dev_priv->chipset == VIA_DX9_0) { |
193 | DRM_ERROR("AGP DMA is not supported on this chip\n"); | |
20caafa6 | 194 | return -EINVAL; |
756db73d TH |
195 | } |
196 | ||
22f579c6 DA |
197 | dev_priv->ring.map.offset = dev->agp->base + init->offset; |
198 | dev_priv->ring.map.size = init->size; | |
199 | dev_priv->ring.map.type = 0; | |
200 | dev_priv->ring.map.flags = 0; | |
201 | dev_priv->ring.map.mtrr = 0; | |
202 | ||
86c1fbd5 | 203 | drm_legacy_ioremap(&dev_priv->ring.map, dev); |
22f579c6 DA |
204 | |
205 | if (dev_priv->ring.map.handle == NULL) { | |
206 | via_dma_cleanup(dev); | |
207 | DRM_ERROR("can not ioremap virtual address for" | |
208 | " ring buffer\n"); | |
20caafa6 | 209 | return -ENOMEM; |
22f579c6 DA |
210 | } |
211 | ||
212 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
213 | ||
214 | dev_priv->dma_ptr = dev_priv->ring.virtual_start; | |
215 | dev_priv->dma_low = 0; | |
216 | dev_priv->dma_high = init->size; | |
217 | dev_priv->dma_wrap = init->size; | |
218 | dev_priv->dma_offset = init->offset; | |
219 | dev_priv->last_pause_ptr = NULL; | |
92514243 DA |
220 | dev_priv->hw_addr_ptr = |
221 | (volatile uint32_t *)((char *)dev_priv->mmio->handle + | |
222 | init->reg_pause_addr); | |
22f579c6 DA |
223 | |
224 | via_cmdbuf_start(dev_priv); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
c153f45f | 229 | static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv) |
22f579c6 | 230 | { |
22f579c6 | 231 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; |
c153f45f | 232 | drm_via_dma_init_t *init = data; |
22f579c6 DA |
233 | int retcode = 0; |
234 | ||
c153f45f | 235 | switch (init->func) { |
22f579c6 | 236 | case VIA_INIT_DMA: |
4cda878b | 237 | if (!capable(CAP_SYS_ADMIN)) |
20caafa6 | 238 | retcode = -EPERM; |
22f579c6 | 239 | else |
c153f45f | 240 | retcode = via_initialize(dev, dev_priv, init); |
22f579c6 DA |
241 | break; |
242 | case VIA_CLEANUP_DMA: | |
4cda878b | 243 | if (!capable(CAP_SYS_ADMIN)) |
20caafa6 | 244 | retcode = -EPERM; |
22f579c6 DA |
245 | else |
246 | retcode = via_dma_cleanup(dev); | |
247 | break; | |
b5e89ed5 DA |
248 | case VIA_DMA_INITIALIZED: |
249 | retcode = (dev_priv->ring.virtual_start != NULL) ? | |
20caafa6 | 250 | 0 : -EFAULT; |
b5e89ed5 | 251 | break; |
22f579c6 | 252 | default: |
20caafa6 | 253 | retcode = -EINVAL; |
22f579c6 DA |
254 | break; |
255 | } | |
256 | ||
257 | return retcode; | |
258 | } | |
259 | ||
58c1e85a | 260 | static int via_dispatch_cmdbuffer(struct drm_device *dev, drm_via_cmdbuffer_t *cmd) |
22f579c6 DA |
261 | { |
262 | drm_via_private_t *dev_priv; | |
263 | uint32_t *vb; | |
264 | int ret; | |
265 | ||
266 | dev_priv = (drm_via_private_t *) dev->dev_private; | |
267 | ||
268 | if (dev_priv->ring.virtual_start == NULL) { | |
3e684eae | 269 | DRM_ERROR("called without initializing AGP ring buffer.\n"); |
20caafa6 | 270 | return -EFAULT; |
22f579c6 DA |
271 | } |
272 | ||
58c1e85a | 273 | if (cmd->size > VIA_PCI_BUF_SIZE) |
20caafa6 | 274 | return -ENOMEM; |
22f579c6 | 275 | |
1d6ac185 | 276 | if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size)) |
20caafa6 | 277 | return -EFAULT; |
22f579c6 DA |
278 | |
279 | /* | |
280 | * Running this function on AGP memory is dead slow. Therefore | |
281 | * we run it on a temporary cacheable system memory buffer and | |
282 | * copy it to AGP memory when ready. | |
283 | */ | |
284 | ||
b5e89ed5 DA |
285 | if ((ret = |
286 | via_verify_command_stream((uint32_t *) dev_priv->pci_buf, | |
287 | cmd->size, dev, 1))) { | |
22f579c6 DA |
288 | return ret; |
289 | } | |
b5e89ed5 | 290 | |
22f579c6 | 291 | vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); |
58c1e85a | 292 | if (vb == NULL) |
20caafa6 | 293 | return -EAGAIN; |
22f579c6 DA |
294 | |
295 | memcpy(vb, dev_priv->pci_buf, cmd->size); | |
b5e89ed5 | 296 | |
22f579c6 DA |
297 | dev_priv->dma_low += cmd->size; |
298 | ||
299 | /* | |
300 | * Small submissions somehow stalls the CPU. (AGP cache effects?) | |
301 | * pad to greater size. | |
302 | */ | |
303 | ||
304 | if (cmd->size < 0x100) | |
b5e89ed5 | 305 | via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3); |
22f579c6 DA |
306 | via_cmdbuf_pause(dev_priv); |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
58c1e85a | 311 | int via_driver_dma_quiescent(struct drm_device *dev) |
22f579c6 DA |
312 | { |
313 | drm_via_private_t *dev_priv = dev->dev_private; | |
314 | ||
58c1e85a | 315 | if (!via_wait_idle(dev_priv)) |
20caafa6 | 316 | return -EBUSY; |
22f579c6 DA |
317 | return 0; |
318 | } | |
319 | ||
c153f45f | 320 | static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) |
22f579c6 | 321 | { |
22f579c6 | 322 | |
6c340eac | 323 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
22f579c6 DA |
324 | |
325 | return via_driver_dma_quiescent(dev); | |
326 | } | |
327 | ||
c153f45f | 328 | static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) |
22f579c6 | 329 | { |
c153f45f | 330 | drm_via_cmdbuffer_t *cmdbuf = data; |
22f579c6 DA |
331 | int ret; |
332 | ||
6c340eac | 333 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
22f579c6 | 334 | |
3e684eae | 335 | DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size); |
22f579c6 | 336 | |
c153f45f | 337 | ret = via_dispatch_cmdbuffer(dev, cmdbuf); |
58c1e85a | 338 | return ret; |
22f579c6 DA |
339 | } |
340 | ||
58c1e85a NK |
341 | static int via_dispatch_pci_cmdbuffer(struct drm_device *dev, |
342 | drm_via_cmdbuffer_t *cmd) | |
22f579c6 DA |
343 | { |
344 | drm_via_private_t *dev_priv = dev->dev_private; | |
345 | int ret; | |
346 | ||
58c1e85a | 347 | if (cmd->size > VIA_PCI_BUF_SIZE) |
20caafa6 | 348 | return -ENOMEM; |
1d6ac185 | 349 | if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size)) |
20caafa6 | 350 | return -EFAULT; |
b5e89ed5 DA |
351 | |
352 | if ((ret = | |
353 | via_verify_command_stream((uint32_t *) dev_priv->pci_buf, | |
354 | cmd->size, dev, 0))) { | |
22f579c6 DA |
355 | return ret; |
356 | } | |
b5e89ed5 DA |
357 | |
358 | ret = | |
359 | via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, | |
360 | cmd->size); | |
22f579c6 DA |
361 | return ret; |
362 | } | |
363 | ||
c153f45f | 364 | static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) |
22f579c6 | 365 | { |
c153f45f | 366 | drm_via_cmdbuffer_t *cmdbuf = data; |
22f579c6 DA |
367 | int ret; |
368 | ||
6c340eac | 369 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
22f579c6 | 370 | |
3e684eae | 371 | DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size); |
22f579c6 | 372 | |
c153f45f | 373 | ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf); |
58c1e85a | 374 | return ret; |
22f579c6 DA |
375 | } |
376 | ||
58c1e85a | 377 | static inline uint32_t *via_align_buffer(drm_via_private_t *dev_priv, |
22f579c6 DA |
378 | uint32_t * vb, int qw_count) |
379 | { | |
58c1e85a | 380 | for (; qw_count > 0; --qw_count) |
22f579c6 | 381 | VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY); |
22f579c6 DA |
382 | return vb; |
383 | } | |
384 | ||
22f579c6 | 385 | /* |
8dfba4d7 | 386 | * This function is used internally by ring buffer management code. |
22f579c6 DA |
387 | * |
388 | * Returns virtual pointer to ring buffer. | |
389 | */ | |
58c1e85a | 390 | static inline uint32_t *via_get_dma(drm_via_private_t *dev_priv) |
22f579c6 DA |
391 | { |
392 | return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); | |
393 | } | |
394 | ||
395 | /* | |
396 | * Hooks a segment of data into the tail of the ring-buffer by | |
397 | * modifying the pause address stored in the buffer itself. If | |
398 | * the regulator has already paused, restart it. | |
399 | */ | |
58c1e85a | 400 | static int via_hook_segment(drm_via_private_t *dev_priv, |
22f579c6 DA |
401 | uint32_t pause_addr_hi, uint32_t pause_addr_lo, |
402 | int no_pci_fire) | |
403 | { | |
404 | int paused, count; | |
405 | volatile uint32_t *paused_at = dev_priv->last_pause_ptr; | |
58c1e85a | 406 | uint32_t reader, ptr; |
f0fb6d77 | 407 | uint32_t diff; |
22f579c6 | 408 | |
a0a6dd0b | 409 | paused = 0; |
22f579c6 | 410 | via_flush_write_combine(); |
58c1e85a | 411 | (void) *(volatile uint32_t *)(via_get_dma(dev_priv) - 1); |
f0fb6d77 | 412 | |
ef68d295 | 413 | *paused_at = pause_addr_lo; |
22f579c6 | 414 | via_flush_write_combine(); |
ef68d295 | 415 | (void) *paused_at; |
f0fb6d77 | 416 | |
a0a6dd0b TH |
417 | reader = *(dev_priv->hw_addr_ptr); |
418 | ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + | |
419 | dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; | |
f0fb6d77 | 420 | |
22f579c6 | 421 | dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; |
22f579c6 | 422 | |
f0fb6d77 | 423 | /* |
58c1e85a | 424 | * If there is a possibility that the command reader will |
f0fb6d77 TH |
425 | * miss the new pause address and pause on the old one, |
426 | * In that case we need to program the new start address | |
427 | * using PCI. | |
428 | */ | |
429 | ||
430 | diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; | |
431 | count = 10000000; | |
58c1e85a | 432 | while (diff == 0 && count--) { |
f0fb6d77 | 433 | paused = (VIA_READ(0x41c) & 0x80000000); |
58c1e85a | 434 | if (paused) |
f0fb6d77 TH |
435 | break; |
436 | reader = *(dev_priv->hw_addr_ptr); | |
437 | diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; | |
22f579c6 | 438 | } |
b5e89ed5 | 439 | |
f0fb6d77 TH |
440 | paused = VIA_READ(0x41c) & 0x80000000; |
441 | ||
22f579c6 | 442 | if (paused && !no_pci_fire) { |
a0a6dd0b | 443 | reader = *(dev_priv->hw_addr_ptr); |
f0fb6d77 TH |
444 | diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; |
445 | diff &= (dev_priv->dma_high - 1); | |
446 | if (diff != 0 && diff < (dev_priv->dma_high >> 1)) { | |
447 | DRM_ERROR("Paused at incorrect address. " | |
448 | "0x%08x, 0x%08x 0x%08x\n", | |
449 | ptr, reader, dev_priv->dma_diff); | |
450 | } else if (diff == 0) { | |
a0a6dd0b TH |
451 | /* |
452 | * There is a concern that these writes may stall the PCI bus | |
453 | * if the GPU is not idle. However, idling the GPU first | |
454 | * doesn't make a difference. | |
455 | */ | |
b5e89ed5 | 456 | |
22f579c6 DA |
457 | VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); |
458 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); | |
459 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); | |
76f62551 | 460 | VIA_READ(VIA_REG_TRANSPACE); |
b5e89ed5 | 461 | } |
22f579c6 DA |
462 | } |
463 | return paused; | |
464 | } | |
465 | ||
58c1e85a | 466 | static int via_wait_idle(drm_via_private_t *dev_priv) |
22f579c6 DA |
467 | { |
468 | int count = 10000000; | |
a0a6dd0b | 469 | |
d9c6f546 RK |
470 | while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count) |
471 | ; | |
a0a6dd0b | 472 | |
d9c6f546 | 473 | while (count && (VIA_READ(VIA_REG_STATUS) & |
22f579c6 | 474 | (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | |
d9c6f546 RK |
475 | VIA_3D_ENG_BUSY))) |
476 | --count; | |
22f579c6 DA |
477 | return count; |
478 | } | |
479 | ||
58c1e85a NK |
480 | static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type, |
481 | uint32_t addr, uint32_t *cmd_addr_hi, | |
482 | uint32_t *cmd_addr_lo, int skip_wait) | |
22f579c6 DA |
483 | { |
484 | uint32_t agp_base; | |
485 | uint32_t cmd_addr, addr_lo, addr_hi; | |
486 | uint32_t *vb; | |
487 | uint32_t qw_pad_count; | |
488 | ||
489 | if (!skip_wait) | |
b5e89ed5 | 490 | via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE); |
22f579c6 DA |
491 | |
492 | vb = via_get_dma(dev_priv); | |
b5e89ed5 DA |
493 | VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) | |
494 | (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16); | |
22f579c6 DA |
495 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
496 | qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) - | |
b5e89ed5 | 497 | ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); |
22f579c6 | 498 | |
b5e89ed5 DA |
499 | cmd_addr = (addr) ? addr : |
500 | agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3); | |
22f579c6 DA |
501 | addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) | |
502 | (cmd_addr & HC_HAGPBpL_MASK)); | |
503 | addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24)); | |
504 | ||
505 | vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1); | |
b5e89ed5 | 506 | VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo); |
22f579c6 DA |
507 | return vb; |
508 | } | |
509 | ||
58c1e85a | 510 | static void via_cmdbuf_start(drm_via_private_t *dev_priv) |
22f579c6 DA |
511 | { |
512 | uint32_t pause_addr_lo, pause_addr_hi; | |
513 | uint32_t start_addr, start_addr_lo; | |
514 | uint32_t end_addr, end_addr_lo; | |
515 | uint32_t command; | |
516 | uint32_t agp_base; | |
a0a6dd0b TH |
517 | uint32_t ptr; |
518 | uint32_t reader; | |
519 | int count; | |
22f579c6 | 520 | |
22f579c6 DA |
521 | dev_priv->dma_low = 0; |
522 | ||
523 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
524 | start_addr = agp_base; | |
525 | end_addr = agp_base + dev_priv->dma_high; | |
526 | ||
527 | start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF)); | |
528 | end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF)); | |
529 | command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) | | |
530 | ((end_addr & 0xff000000) >> 16)); | |
531 | ||
b5e89ed5 DA |
532 | dev_priv->last_pause_ptr = |
533 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, | |
534 | &pause_addr_hi, &pause_addr_lo, 1) - 1; | |
22f579c6 DA |
535 | |
536 | via_flush_write_combine(); | |
ef68d295 | 537 | (void) *(volatile uint32_t *)dev_priv->last_pause_ptr; |
22f579c6 DA |
538 | |
539 | VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); | |
540 | VIA_WRITE(VIA_REG_TRANSPACE, command); | |
541 | VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo); | |
542 | VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo); | |
543 | ||
544 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); | |
545 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); | |
85b2331b | 546 | wmb(); |
22f579c6 | 547 | VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); |
76f62551 | 548 | VIA_READ(VIA_REG_TRANSPACE); |
a0a6dd0b TH |
549 | |
550 | dev_priv->dma_diff = 0; | |
551 | ||
552 | count = 10000000; | |
553 | while (!(VIA_READ(0x41c) & 0x80000000) && count--); | |
554 | ||
555 | reader = *(dev_priv->hw_addr_ptr); | |
556 | ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + | |
557 | dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; | |
558 | ||
559 | /* | |
560 | * This is the difference between where we tell the | |
561 | * command reader to pause and where it actually pauses. | |
562 | * This differs between hw implementation so we need to | |
563 | * detect it. | |
564 | */ | |
565 | ||
566 | dev_priv->dma_diff = ptr - reader; | |
22f579c6 DA |
567 | } |
568 | ||
58c1e85a | 569 | static void via_pad_cache(drm_via_private_t *dev_priv, int qwords) |
22f579c6 DA |
570 | { |
571 | uint32_t *vb; | |
572 | ||
573 | via_cmdbuf_wait(dev_priv, qwords + 2); | |
574 | vb = via_get_dma(dev_priv); | |
b5e89ed5 DA |
575 | VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16); |
576 | via_align_buffer(dev_priv, vb, qwords); | |
22f579c6 DA |
577 | } |
578 | ||
58c1e85a | 579 | static inline void via_dummy_bitblt(drm_via_private_t *dev_priv) |
22f579c6 DA |
580 | { |
581 | uint32_t *vb = via_get_dma(dev_priv); | |
582 | SetReg2DAGP(0x0C, (0 | (0 << 16))); | |
583 | SetReg2DAGP(0x10, 0 | (0 << 16)); | |
b5e89ed5 | 584 | SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); |
22f579c6 DA |
585 | } |
586 | ||
58c1e85a | 587 | static void via_cmdbuf_jump(drm_via_private_t *dev_priv) |
22f579c6 DA |
588 | { |
589 | uint32_t agp_base; | |
590 | uint32_t pause_addr_lo, pause_addr_hi; | |
591 | uint32_t jump_addr_lo, jump_addr_hi; | |
592 | volatile uint32_t *last_pause_ptr; | |
f0fb6d77 | 593 | uint32_t dma_low_save1, dma_low_save2; |
22f579c6 DA |
594 | |
595 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
b5e89ed5 | 596 | via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, |
22f579c6 | 597 | &jump_addr_lo, 0); |
22f579c6 | 598 | |
b5e89ed5 | 599 | dev_priv->dma_wrap = dev_priv->dma_low; |
22f579c6 DA |
600 | |
601 | /* | |
602 | * Wrap command buffer to the beginning. | |
603 | */ | |
604 | ||
605 | dev_priv->dma_low = 0; | |
58c1e85a | 606 | if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) |
22f579c6 | 607 | DRM_ERROR("via_cmdbuf_jump failed\n"); |
22f579c6 DA |
608 | |
609 | via_dummy_bitblt(dev_priv); | |
b5e89ed5 | 610 | via_dummy_bitblt(dev_priv); |
22f579c6 | 611 | |
b5e89ed5 DA |
612 | last_pause_ptr = |
613 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
614 | &pause_addr_lo, 0) - 1; | |
615 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
22f579c6 DA |
616 | &pause_addr_lo, 0); |
617 | ||
618 | *last_pause_ptr = pause_addr_lo; | |
f0fb6d77 | 619 | dma_low_save1 = dev_priv->dma_low; |
22f579c6 | 620 | |
f0fb6d77 TH |
621 | /* |
622 | * Now, set a trap that will pause the regulator if it tries to rerun the old | |
623 | * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause | |
624 | * and reissues the jump command over PCI, while the regulator has already taken the jump | |
625 | * and actually paused at the current buffer end). | |
626 | * There appears to be no other way to detect this condition, since the hw_addr_pointer | |
627 | * does not seem to get updated immediately when a jump occurs. | |
628 | */ | |
629 | ||
630 | last_pause_ptr = | |
631 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
632 | &pause_addr_lo, 0) - 1; | |
633 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
634 | &pause_addr_lo, 0); | |
635 | *last_pause_ptr = pause_addr_lo; | |
636 | ||
637 | dma_low_save2 = dev_priv->dma_low; | |
638 | dev_priv->dma_low = dma_low_save1; | |
639 | via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0); | |
640 | dev_priv->dma_low = dma_low_save2; | |
641 | via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); | |
22f579c6 DA |
642 | } |
643 | ||
a0a6dd0b | 644 | |
58c1e85a | 645 | static void via_cmdbuf_rewind(drm_via_private_t *dev_priv) |
22f579c6 | 646 | { |
b5e89ed5 | 647 | via_cmdbuf_jump(dev_priv); |
22f579c6 DA |
648 | } |
649 | ||
58c1e85a | 650 | static void via_cmdbuf_flush(drm_via_private_t *dev_priv, uint32_t cmd_type) |
22f579c6 DA |
651 | { |
652 | uint32_t pause_addr_lo, pause_addr_hi; | |
653 | ||
654 | via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0); | |
b5e89ed5 | 655 | via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); |
22f579c6 DA |
656 | } |
657 | ||
58c1e85a | 658 | static void via_cmdbuf_pause(drm_via_private_t *dev_priv) |
22f579c6 DA |
659 | { |
660 | via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE); | |
661 | } | |
662 | ||
58c1e85a | 663 | static void via_cmdbuf_reset(drm_via_private_t *dev_priv) |
22f579c6 DA |
664 | { |
665 | via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP); | |
666 | via_wait_idle(dev_priv); | |
667 | } | |
668 | ||
669 | /* | |
670 | * User interface to the space and lag functions. | |
671 | */ | |
672 | ||
c153f45f | 673 | static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv) |
22f579c6 | 674 | { |
c153f45f | 675 | drm_via_cmdbuf_size_t *d_siz = data; |
22f579c6 DA |
676 | int ret = 0; |
677 | uint32_t tmp_size, count; | |
678 | drm_via_private_t *dev_priv; | |
679 | ||
3e684eae | 680 | DRM_DEBUG("\n"); |
6c340eac | 681 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
22f579c6 DA |
682 | |
683 | dev_priv = (drm_via_private_t *) dev->dev_private; | |
684 | ||
685 | if (dev_priv->ring.virtual_start == NULL) { | |
3e684eae | 686 | DRM_ERROR("called without initializing AGP ring buffer.\n"); |
20caafa6 | 687 | return -EFAULT; |
22f579c6 DA |
688 | } |
689 | ||
22f579c6 | 690 | count = 1000000; |
c153f45f EA |
691 | tmp_size = d_siz->size; |
692 | switch (d_siz->func) { | |
22f579c6 | 693 | case VIA_CMDBUF_SPACE: |
c153f45f | 694 | while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size) |
d9c6f546 | 695 | && --count) { |
58c1e85a | 696 | if (!d_siz->wait) |
22f579c6 | 697 | break; |
22f579c6 DA |
698 | } |
699 | if (!count) { | |
700 | DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n"); | |
20caafa6 | 701 | ret = -EAGAIN; |
22f579c6 DA |
702 | } |
703 | break; | |
704 | case VIA_CMDBUF_LAG: | |
c153f45f | 705 | while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size) |
d9c6f546 | 706 | && --count) { |
58c1e85a | 707 | if (!d_siz->wait) |
22f579c6 | 708 | break; |
22f579c6 DA |
709 | } |
710 | if (!count) { | |
711 | DRM_ERROR("VIA_CMDBUF_LAG timed out.\n"); | |
20caafa6 | 712 | ret = -EAGAIN; |
22f579c6 DA |
713 | } |
714 | break; | |
715 | default: | |
20caafa6 | 716 | ret = -EFAULT; |
22f579c6 | 717 | } |
c153f45f | 718 | d_siz->size = tmp_size; |
22f579c6 | 719 | |
22f579c6 DA |
720 | return ret; |
721 | } | |
92514243 | 722 | |
baa70943 | 723 | const struct drm_ioctl_desc via_ioctls[] = { |
1b2f1489 DA |
724 | DRM_IOCTL_DEF_DRV(VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH), |
725 | DRM_IOCTL_DEF_DRV(VIA_FREEMEM, via_mem_free, DRM_AUTH), | |
726 | DRM_IOCTL_DEF_DRV(VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER), | |
727 | DRM_IOCTL_DEF_DRV(VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER), | |
728 | DRM_IOCTL_DEF_DRV(VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER), | |
729 | DRM_IOCTL_DEF_DRV(VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH), | |
730 | DRM_IOCTL_DEF_DRV(VIA_DMA_INIT, via_dma_init, DRM_AUTH), | |
731 | DRM_IOCTL_DEF_DRV(VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH), | |
732 | DRM_IOCTL_DEF_DRV(VIA_FLUSH, via_flush_ioctl, DRM_AUTH), | |
733 | DRM_IOCTL_DEF_DRV(VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH), | |
734 | DRM_IOCTL_DEF_DRV(VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH), | |
735 | DRM_IOCTL_DEF_DRV(VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH), | |
736 | DRM_IOCTL_DEF_DRV(VIA_DMA_BLIT, via_dma_blit, DRM_AUTH), | |
737 | DRM_IOCTL_DEF_DRV(VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH) | |
92514243 DA |
738 | }; |
739 | ||
f95aeb17 | 740 | int via_max_ioctl = ARRAY_SIZE(via_ioctls); |